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URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

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  • This comparison shows the changes necessary to convert path
    /spacewire_light/trunk/syn/streamtest_gr-xc3s1500
    from Rev 5 to Rev 7
    Reverse comparison

Rev 5 → Rev 7

/streamtest.ucf
5,14 → 5,12
TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal
# 3 ns data path + 1 ns source skew + 1 ns destination skew = 5 ns
# fastclk = 200 MHz = 5 ns nominal = 4 ns data path + 1 ns margin
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;
NET "sysclk" MAXSKEW = 1 ns ;
NET "fastclk" MAXSKEW = 1 ns ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns ;
 
# Board clock
NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL;
/Makefile
27,7 → 27,8
$(RTLDIR)/spwxmit.vhd \
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd
$(RTLDIR)/spwrecvfront_fast.vhd \
$(RTLDIR)/syncdff.vhd
 
# For Pender XC3S1500 board
FPGA_TYPE = xc3s1500-fg456-4
55,7 → 56,7
.PHONY : default clean bitfile
 
clean :
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb _xmsgs
$(RM) $(PROJ).xst-script
$(RM) $(PROJ).lso $(PROJ).prj
$(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
65,6 → 66,7
$(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
$(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
$(RM) $(PROJ)_bitgen.xwbt usage_statistics_webtalk.html webtalk.log
 
bitfile : $(PROJ).bit
 
/streamtest_top.vhd
240,6 → 240,7
s_linkdisable <= switch(1);
s_senddata <= switch(2);
s_sendtick <= switch(3);
s_txdivcnt(7 downto 4) <= "0000";
s_txdivcnt(3 downto 0) <= switch(7 downto 4);
 
-- Sticky link error LED

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