OpenCores
URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

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    /spacewire_light/trunk/syn
    from Rev 3 to Rev 5
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Rev 3 → Rev 5

/spwamba_gr-xc3s1500/defconfig
0,0 → 1,306
#
# Automatically generated make config: don't edit
#
 
#
# Synthesis
#
# CONFIG_SYN_INFERRED is not set
# CONFIG_SYN_STRATIX is not set
# CONFIG_SYN_STRATIXII is not set
# CONFIG_SYN_STRATIXIII is not set
# CONFIG_SYN_CYCLONEIII is not set
# CONFIG_SYN_ALTERA is not set
# CONFIG_SYN_AXCEL is not set
# CONFIG_SYN_AXDSP is not set
# CONFIG_SYN_PROASIC is not set
# CONFIG_SYN_PROASICPLUS is not set
# CONFIG_SYN_PROASIC3 is not set
# CONFIG_SYN_IGLOO is not set
# CONFIG_SYN_FUSION is not set
# CONFIG_SYN_UT025CRH is not set
# CONFIG_SYN_ATC18 is not set
# CONFIG_SYN_ATC18RHA is not set
# CONFIG_SYN_CUSTOM1 is not set
# CONFIG_SYN_EASIC90 is not set
# CONFIG_SYN_IHP25 is not set
# CONFIG_SYN_IHP25RH is not set
# CONFIG_SYN_LATTICE is not set
# CONFIG_SYN_ECLIPSE is not set
# CONFIG_SYN_PEREGRINE is not set
# CONFIG_SYN_RH_LIB18T is not set
# CONFIG_SYN_RHUMC is not set
# CONFIG_SYN_SMIC13 is not set
# CONFIG_SYN_SPARTAN2 is not set
CONFIG_SYN_SPARTAN3=y
# CONFIG_SYN_SPARTAN3E is not set
# CONFIG_SYN_SPARTAN6 is not set
# CONFIG_SYN_VIRTEX is not set
# CONFIG_SYN_VIRTEXE is not set
# CONFIG_SYN_VIRTEX2 is not set
# CONFIG_SYN_VIRTEX4 is not set
# CONFIG_SYN_VIRTEX5 is not set
# CONFIG_SYN_VIRTEX6 is not set
# CONFIG_SYN_UMC is not set
# CONFIG_SYN_TSMC90 is not set
# CONFIG_SYN_INFER_RAM is not set
# CONFIG_SYN_INFER_PADS is not set
# CONFIG_SYN_NO_ASYNC is not set
# CONFIG_SYN_SCAN is not set
CONFIG_FPGA_1500=y
# CONFIG_FPGA_2000 is not set
 
#
# Clock generation
#
# CONFIG_CLK_INFERRED is not set
# CONFIG_CLK_HCLKBUF is not set
# CONFIG_CLK_ALTDLL is not set
# CONFIG_CLK_LATDLL is not set
# CONFIG_CLK_PRO3PLL is not set
# CONFIG_CLK_FUSPLL is not set
# CONFIG_CLK_LIB18T is not set
# CONFIG_CLK_RHUMC is not set
# CONFIG_CLK_CLKDLL is not set
CONFIG_CLK_DCM=y
CONFIG_CLK_MUL=4
CONFIG_CLK_DIV=5
# CONFIG_PCI_CLKDLL is not set
# CONFIG_CLK_NOFB is not set
# CONFIG_PCI_SYSCLK is not set
CONFIG_LEON3=y
CONFIG_PROC_NUM=1
 
#
# Processor
#
 
#
# Integer unit
#
CONFIG_IU_NWINDOWS=8
CONFIG_IU_V8MULDIV=y
CONFIG_IU_MUL_LATENCY_2=y
# CONFIG_IU_MUL_LATENCY_4 is not set
# CONFIG_IU_MUL_LATENCY_5 is not set
CONFIG_IU_BP=y
CONFIG_IU_SVT=y
CONFIG_IU_LDELAY=1
CONFIG_IU_WATCHPOINTS=4
# CONFIG_PWD is not set
CONFIG_IU_RSTADDR=00000
 
#
# Floating-point unit
#
# CONFIG_FPU_ENABLE is not set
 
#
# Cache system
#
CONFIG_ICACHE_ENABLE=y
# CONFIG_ICACHE_ASSO1 is not set
CONFIG_ICACHE_ASSO2=y
# CONFIG_ICACHE_ASSO3 is not set
# CONFIG_ICACHE_ASSO4 is not set
# CONFIG_ICACHE_SZ1 is not set
# CONFIG_ICACHE_SZ2 is not set
CONFIG_ICACHE_SZ4=y
# CONFIG_ICACHE_SZ8 is not set
# CONFIG_ICACHE_SZ16 is not set
# CONFIG_ICACHE_SZ32 is not set
# CONFIG_ICACHE_SZ64 is not set
# CONFIG_ICACHE_SZ128 is not set
# CONFIG_ICACHE_SZ256 is not set
# CONFIG_ICACHE_LZ16 is not set
CONFIG_ICACHE_LZ32=y
# CONFIG_ICACHE_ALGORND is not set
# CONFIG_ICACHE_ALGOLRR is not set
CONFIG_ICACHE_ALGOLRU=y
# CONFIG_ICACHE_LOCK is not set
CONFIG_DCACHE_ENABLE=y
CONFIG_DCACHE_ASSO1=y
# CONFIG_DCACHE_ASSO2 is not set
# CONFIG_DCACHE_ASSO3 is not set
# CONFIG_DCACHE_ASSO4 is not set
# CONFIG_DCACHE_SZ1 is not set
# CONFIG_DCACHE_SZ2 is not set
CONFIG_DCACHE_SZ4=y
# CONFIG_DCACHE_SZ8 is not set
# CONFIG_DCACHE_SZ16 is not set
# CONFIG_DCACHE_SZ32 is not set
# CONFIG_DCACHE_SZ64 is not set
# CONFIG_DCACHE_SZ128 is not set
# CONFIG_DCACHE_SZ256 is not set
CONFIG_DCACHE_LZ16=y
# CONFIG_DCACHE_LZ32 is not set
CONFIG_DCACHE_SNOOP=y
# CONFIG_DCACHE_SNOOP_FAST is not set
# CONFIG_DCACHE_SNOOP_SEPTAG is not set
CONFIG_CACHE_FIXED=0
 
#
# MMU
#
CONFIG_MMU_ENABLE=y
# CONFIG_MMU_COMBINED is not set
CONFIG_MMU_SPLIT=y
CONFIG_MMU_REPARRAY=y
# CONFIG_MMU_REPINCREMENT is not set
# CONFIG_MMU_I2 is not set
# CONFIG_MMU_I4 is not set
CONFIG_MMU_I8=y
# CONFIG_MMU_I16 is not set
# CONFIG_MMU_I32 is not set
# CONFIG_MMU_D2 is not set
# CONFIG_MMU_D4 is not set
CONFIG_MMU_D8=y
# CONFIG_MMU_D16 is not set
# CONFIG_MMU_D32 is not set
CONFIG_MMU_FASTWB=y
CONFIG_MMU_PAGE_4K=y
# CONFIG_MMU_PAGE_8K is not set
# CONFIG_MMU_PAGE_16K is not set
# CONFIG_MMU_PAGE_32K is not set
# CONFIG_MMU_PAGE_PROG is not set
 
#
# Debug Support Unit
#
CONFIG_DSU_ENABLE=y
CONFIG_DSU_ITRACE=y
# CONFIG_DSU_ITRACESZ1 is not set
CONFIG_DSU_ITRACESZ2=y
# CONFIG_DSU_ITRACESZ4 is not set
# CONFIG_DSU_ITRACESZ8 is not set
# CONFIG_DSU_ITRACESZ16 is not set
CONFIG_DSU_ATRACE=y
# CONFIG_DSU_ATRACESZ1 is not set
CONFIG_DSU_ATRACESZ2=y
# CONFIG_DSU_ATRACESZ4 is not set
# CONFIG_DSU_ATRACESZ8 is not set
# CONFIG_DSU_ATRACESZ16 is not set
 
#
# Fault-tolerance
#
 
#
# VHDL debug settings
#
# CONFIG_IU_DISAS is not set
# CONFIG_DEBUG_PC32 is not set
 
#
# AMBA configuration
#
CONFIG_AHB_DEFMST=0
CONFIG_AHB_RROBIN=y
# CONFIG_AHB_SPLIT is not set
CONFIG_AHB_IOADDR=FFF
CONFIG_APB_HADDR=800
# CONFIG_AHB_MON is not set
 
#
# Debug Link
#
CONFIG_DSU_UART=y
CONFIG_DSU_JTAG=y
# CONFIG_GRUSB_DCL is not set
CONFIG_DSU_ETH=y
# CONFIG_DSU_ETHSZ1 is not set
CONFIG_DSU_ETHSZ2=y
# CONFIG_DSU_ETHSZ4 is not set
# CONFIG_DSU_ETHSZ8 is not set
# CONFIG_DSU_ETHSZ16 is not set
CONFIG_DSU_IPMSB=C0A8
CONFIG_DSU_IPLSB=0033
CONFIG_DSU_ETHMSB=020000
CONFIG_DSU_ETHLSB=000008
# CONFIG_DSU_ETH_PROG is not set
 
#
# Peripherals
#
 
#
# Memory controller
#
 
#
# Leon2 memory controller
#
CONFIG_MCTRL_LEON2=y
CONFIG_MCTRL_8BIT=y
# CONFIG_MCTRL_16BIT is not set
# CONFIG_MCTRL_5CS is not set
CONFIG_MCTRL_SDRAM=y
# CONFIG_MCTRL_SDRAM_SEPBUS is not set
CONFIG_MCTRL_PAGE=y
# CONFIG_MCTRL_PROGPAGE is not set
# CONFIG_AHBSTAT_ENABLE is not set
 
#
# On-chip RAM/ROM
#
# CONFIG_AHBRAM_ENABLE is not set
 
#
# Ethernet
#
CONFIG_GRETH_ENABLE=y
# CONFIG_GRETH_GIGA is not set
# CONFIG_GRETH_FIFO4 is not set
# CONFIG_GRETH_FIFO8 is not set
CONFIG_GRETH_FIFO16=y
# CONFIG_GRETH_FIFO32 is not set
# CONFIG_GRETH_FIFO64 is not set
 
#
# IDE Disk controller
#
# CONFIG_ATA_ENABLE is not set
 
#
# CAN
#
# CONFIG_CAN_ENABLE is not set
 
#
# USB 2.0 Device Controller
#
# CONFIG_GRUSBDC_ENABLE is not set
 
#
# UART, timer, I/O port and interrupt controller
#
CONFIG_UART1_ENABLE=y
# CONFIG_UA1_FIFO1 is not set
# CONFIG_UA1_FIFO2 is not set
# CONFIG_UA1_FIFO4 is not set
CONFIG_UA1_FIFO8=y
# CONFIG_UA1_FIFO16 is not set
# CONFIG_UA1_FIFO32 is not set
CONFIG_IRQ3_ENABLE=y
# CONFIG_IRQ3_SEC is not set
CONFIG_GPT_ENABLE=y
CONFIG_GPT_NTIM=2
CONFIG_GPT_SW=8
CONFIG_GPT_TW=32
CONFIG_GPT_IRQ=8
CONFIG_GPT_SEPIRQ=y
# CONFIG_GPT_WDOGEN is not set
CONFIG_GRGPIO_ENABLE=y
CONFIG_GRGPIO_WIDTH=8
CONFIG_GRGPIO_IMASK=0000
 
#
# Keybord and VGA interface
#
CONFIG_KBD_ENABLE=y
CONFIG_VGA_ENABLE=y
 
#
# VHDL Debugging
#
# CONFIG_DEBUG_UART is not set
/spwamba_gr-xc3s1500/leon3mp.ucf
0,0 → 1,477
#modified version for gr-xc3s-1550-fg456 board
 
CONFIG stepping="0";
 
NET clk period = 20.000 ;
OFFSET = out : 20.000 : AFTER clk ;
OFFSET = in : 8.000 : BEFORE clk ;
 
NET clk3 period = 40.000 ;
 
NET erx_clk PERIOD = 40.000 ;
OFFSET = in : 10.000 : BEFORE erx_clk ;
NET etx_clk PERIOD = 40.000 ;
OFFSET = out : 20.000 : AFTER etx_clk ;
OFFSET = in : 10.000 : BEFORE etx_clk ;
 
NET usb_clkout period = 16.667;
OFFSET = out : 10.000 : AFTER usb_clkout ;
OFFSET = in : 8.000 : BEFORE usb_clkout ;
 
NET "clkm" TNM_NET = "clkm";
 
# Timing constraints between 200 MHz SpaceWire clock and system clock.
NET "spw_clkl" TNM_NET = "spwclk";
TIMESPEC "TS_spwclk_to_clkm" = FROM "spwclk" TO "clkm" 3 ns DATAPATHONLY;
TIMESPEC "TS_clkm_to_spwclk" = FROM "clkm" TO "spwclk" 3 ns DATAPATHONLY;
NET "clkm" MAXSKEW = 1 ns;
NET "spw_clkl" MAXSKEW = 1 ns;
 
## Input to DCM for 200 MHz SpaceWire clock can not be optimally routed.
PIN "spwclk0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
 
##################################################################
# Enable these is you have enabled the SVGA clock generator
 
NET vid_clock period = 15.000 ;
NET "clk50" TNM_NET = "clk50";
NET "video_clk" TNM_NET = "video_clk";
TIMESPEC "TS_clkm_vidclk" = FROM "clkm" TO "video_clk" TIG;
TIMESPEC "TS_clk50_vidclk" = FROM "clk50" TO "video_clk" TIG;
TIMESPEC "TS_vidclk_clkm" = FROM "video_clk" TO "clkm" TIG;
 
##################################################################
 
INST "clkgen0_xc3s_v_dll0" LOC = DCM_X1Y0;
INST "clkgen0_xc3s_v_sd0_dll1" LOC = DCM_X0Y0;
INST "clkgen0_v_dll0" LOC = DCM_X1Y0;
INST "clkgen0_v_dll1" LOC = DCM_X0Y0;
INST "clkgen0/v/dll0" LOC = DCM_X1Y0;
INST "clkgen0/v/dll1" LOC = DCM_X0Y0;
INST "clkgen0/xc3s.v/dll0" LOC = DCM_X1Y0;
INST "clkgen0/xc3s.v/sd0.dll1" LOC = DCM_X0Y0;
INST "clkgen0.xc3s.v.dll0" LOC = DCM_X1Y0;
INST "clkgen0.xc3s.v.sd0.dll1" LOC = DCM_X0Y0;
 
# ISE/XST constraints
#NET "spw.swloop[0].sw0/rxclki" PERIOD = 10.0 ;
#NET "spw.swloop[1].sw0/rxclki" PERIOD = 10.0 ;
#NET "spw.swloop[2].sw0/rxclki" PERIOD = 10.0 ;
 
# ISE/SYNPLIFY constraints
#NET "spw.swloop.0.sw0/rxclki" PERIOD = 10.0 ;
#NET "spw.swloop.1.sw0/rxclki" PERIOD = 10.0 ;
#NET "spw.swloop.2.sw0/rxclki" PERIOD = 10.0 ;
 
INST "spw.swloop.0.sw0/grspwc0/rxclko" LOC = "SLICE_X0Y62";
INST "spw.swloop[0].sw0/grspwc0/rxclko" LOC = "SLICE_X0Y62";
INST "spw.swloop.1.sw0/grspwc0/rxclko" LOC = "SLICE_X0Y48";
INST "spw.swloop[1].sw0/grspwc0/rxclko" LOC = "SLICE_X0Y48";
INST "spw.swloop.2.sw0/grspwc0/rxclko" LOC = "SLICE_X0Y24";
INST "spw.swloop[2].sw0/grspwc0/rxclko" LOC = "SLICE_X0Y24";
INST "sw00/grspwc0/rxclko" LOC = SLICE_X0Y62;
INST "sw01/grspwc0/rxclko" LOC = SLICE_X0Y48;
INST "sw02/grspwc0/rxclko" LOC = SLICE_X0Y24;
 
NET "address(0)" LOC = "u16" | IOSTANDARD = LVTTL;
NET "address(1)" LOC = "u17" | IOSTANDARD = LVTTL;
NET "address(10)" LOC = "y22" | IOSTANDARD = LVTTL;
NET "address(11)" LOC = "v19" | IOSTANDARD = LVTTL;
NET "address(12)" LOC = "w19" | IOSTANDARD = LVTTL;
NET "address(13)" LOC = "w21" | IOSTANDARD = LVTTL;
NET "address(14)" LOC = "w20" | IOSTANDARD = LVTTL;
NET "address(15)" LOC = "u19" | IOSTANDARD = LVTTL;
NET "address(16)" LOC = "v20" | IOSTANDARD = LVTTL;
NET "address(17)" LOC = "v22" | IOSTANDARD = LVTTL;
NET "address(18)" LOC = "v21" | IOSTANDARD = LVTTL;
NET "address(19)" LOC = "t17" | IOSTANDARD = LVTTL;
NET "address(2)" LOC = "aa20" | IOSTANDARD = LVTTL;
NET "address(20)" LOC = "u18" | IOSTANDARD = LVTTL;
NET "address(21)" LOC = "w13" | IOSTANDARD = LVTTL;
NET "address(22)" LOC = "w14" | IOSTANDARD = LVTTL;
NET "address(23)" LOC = "u14" | IOSTANDARD = LVTTL;
NET "address(24)" LOC = "v14" | IOSTANDARD = LVTTL;
NET "address(25)" LOC = "u13" | IOSTANDARD = LVTTL;
NET "address(26)" LOC = "v13" | IOSTANDARD = LVTTL;
NET "address(27)" LOC = "y13" | IOSTANDARD = LVTTL;
NET "address(3)" LOC = "ab20" | IOSTANDARD = LVTTL;
NET "address(4)" LOC = "aa19" | IOSTANDARD = LVTTL;
NET "address(5)" LOC = "ab19" | IOSTANDARD = LVTTL;
NET "address(6)" LOC = "y21" | IOSTANDARD = LVTTL;
NET "address(7)" LOC = "y20" | IOSTANDARD = LVTTL;
NET "address(8)" LOC = "y19" | IOSTANDARD = LVTTL;
NET "address(9)" LOC = "w22" | IOSTANDARD = LVTTL;
NET "bexcn" LOC = "aa7" | IOSTANDARD = LVTTL;
NET "brdyn" LOC = "ab7" | IOSTANDARD = LVTTL;
NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL;
NET "clk2" LOC = "ab12" | IOSTANDARD = LVTTL;
NET "clk3" LOC = "a11" | IOSTANDARD = LVTTL;
NET "ctsn1" LOC = "l5" | IOSTANDARD = LVTTL;
NET "ctsn2" LOC = "k3" | IOSTANDARD = LVTTL;
NET "data(0)" LOC = "n18" | IOSTANDARD = LVTTL;
NET "data(1)" LOC = "p21" | IOSTANDARD = LVTTL;
NET "data(10)" LOC = "t22" | IOSTANDARD = LVTTL;
NET "data(11)" LOC = "t19" | IOSTANDARD = LVTTL;
NET "data(12)" LOC = "t20" | IOSTANDARD = LVTTL;
NET "data(13)" LOC = "t18" | IOSTANDARD = LVTTL;
NET "data(14)" LOC = "r18" | IOSTANDARD = LVTTL;
NET "data(15)" LOC = "u20" | IOSTANDARD = LVTTL;
NET "data(16)" LOC = "aa18" | IOSTANDARD = LVTTL;
NET "data(17)" LOC = "ab18" | IOSTANDARD = LVTTL;
NET "data(18)" LOC = "ab16" | IOSTANDARD = LVTTL;
NET "data(19)" LOC = "aa15" | IOSTANDARD = LVTTL;
NET "data(2)" LOC = "p22" | IOSTANDARD = LVTTL;
NET "data(20)" LOC = "ab15" | IOSTANDARD = LVTTL;
NET "data(21)" LOC = "ab14" | IOSTANDARD = LVTTL;
NET "data(22)" LOC = "aa13" | IOSTANDARD = LVTTL;
NET "data(23)" LOC = "ab13" | IOSTANDARD = LVTTL;
NET "data(24)" LOC = "aa16" | IOSTANDARD = LVTTL;
NET "data(25)" LOC = "w16" | IOSTANDARD = LVTTL;
NET "data(26)" LOC = "v16" | IOSTANDARD = LVTTL;
NET "data(27)" LOC = "aa17" | IOSTANDARD = LVTTL;
NET "data(28)" LOC = "w17" | IOSTANDARD = LVTTL;
NET "data(29)" LOC = "v17" | IOSTANDARD = LVTTL;
NET "data(3)" LOC = "p17" | IOSTANDARD = LVTTL;
NET "data(30)" LOC = "w18" | IOSTANDARD = LVTTL;
NET "data(31)" LOC = "y18" | IOSTANDARD = LVTTL;
NET "data(4)" LOC = "p18" | IOSTANDARD = LVTTL;
NET "data(5)" LOC = "r19" | IOSTANDARD = LVTTL;
NET "data(6)" LOC = "p19" | IOSTANDARD = LVTTL;
NET "data(7)" LOC = "r21" | IOSTANDARD = LVTTL;
NET "data(8)" LOC = "r22" | IOSTANDARD = LVTTL;
NET "data(9)" LOC = "t21" | IOSTANDARD = LVTTL;
NET "emdint" LOC = "c2" | IOSTANDARD = LVTTL | PULLUP;
NET "emdio" LOC = "c4" | IOSTANDARD = LVTTL | PULLUP;
NET "erx_clk" LOC = "y11" | IOSTANDARD = LVTTL;
NET "erx_col" LOC = "f3" | IOSTANDARD = LVTTL;
NET "erx_crs" LOC = "f4" | IOSTANDARD = LVTTL;
NET "erx_dv" LOC = "e3" | IOSTANDARD = LVTTL;
NET "erx_er" LOC = "f2" | IOSTANDARD = LVTTL;
NET "erxd(0)" LOC = "e4" | IOSTANDARD = LVTTL;
NET "erxd(1)" LOC = "d4" | IOSTANDARD = LVTTL;
NET "erxd(2)" LOC = "d3" | IOSTANDARD = LVTTL;
NET "erxd(3)" LOC = "d2" | IOSTANDARD = LVTTL;
NET "emdc" LOC = "c3" | IOSTANDARD = LVTTL;
NET "etx_clk" LOC = "aa11" | IOSTANDARD = LVTTL;
NET "etx_en" LOC = "f5" | IOSTANDARD = LVTTL;
NET "etx_er" LOC = "g6" | IOSTANDARD = LVTTL;
NET "etxd(0)" LOC = "e1" | IOSTANDARD = LVTTL;
NET "etxd(1)" LOC = "e2" | IOSTANDARD = LVTTL;
NET "etxd(2)" LOC = "d1" | IOSTANDARD = LVTTL;
NET "etxd(3)" LOC = "c1" | IOSTANDARD = LVTTL;
NET "genio(0)" LOC = "m6" | IOSTANDARD = LVTTL;
NET "genio(1)" LOC = "m5" | IOSTANDARD = LVTTL;
NET "genio(10)" LOC = "t6" | IOSTANDARD = LVTTL;
NET "genio(11)" LOC = "t5" | IOSTANDARD = LVTTL;
NET "genio(12)" LOC = "v5" | IOSTANDARD = LVTTL;
NET "genio(13)" LOC = "u5" | IOSTANDARD = LVTTL;
NET "genio(14)" LOC = "w4" | IOSTANDARD = LVTTL;
NET "genio(15)" LOC = "w3" | IOSTANDARD = LVTTL;
NET "genio(16)" LOC = "y3" | IOSTANDARD = LVTTL;
NET "genio(17)" LOC = "y2" | IOSTANDARD = LVTTL;
NET "genio(18)" LOC = "y1" | IOSTANDARD = LVTTL;
NET "genio(19)" LOC = "u6" | IOSTANDARD = LVTTL;
NET "genio(2)" LOC = "n6" | IOSTANDARD = LVTTL;
NET "genio(20)" LOC = "d22" | IOSTANDARD = LVTTL;
NET "genio(21)" LOC = "g17" | IOSTANDARD = LVTTL;
NET "genio(22)" LOC = "e21" | IOSTANDARD = LVTTL;
NET "genio(23)" LOC = "g22" | IOSTANDARD = LVTTL;
NET "genio(24)" LOC = "g21" | IOSTANDARD = LVTTL;
NET "genio(25)" LOC = "g19" | IOSTANDARD = LVTTL;
NET "genio(26)" LOC = "h22" | IOSTANDARD = LVTTL;
NET "genio(27)" LOC = "g18" | IOSTANDARD = LVTTL;
NET "genio(28)" LOC = "j18" | IOSTANDARD = LVTTL;
NET "genio(29)" LOC = "j21" | IOSTANDARD = LVTTL;
NET "genio(3)" LOC = "n5" | IOSTANDARD = LVTTL;
NET "genio(30)" LOC = "j22" | IOSTANDARD = LVTTL;
NET "genio(31)" LOC = "h21" | IOSTANDARD = LVTTL;
NET "genio(32)" LOC = "k22" | IOSTANDARD = LVTTL;
NET "genio(33)" LOC = "k21" | IOSTANDARD = LVTTL;
NET "genio(34)" LOC = "k18" | IOSTANDARD = LVTTL;
NET "genio(35)" LOC = "l19" | IOSTANDARD = LVTTL;
NET "genio(36)" LOC = "l18" | IOSTANDARD = LVTTL;
NET "genio(37)" LOC = "k17" | IOSTANDARD = LVTTL;
NET "genio(38)" LOC = "l17" | IOSTANDARD = LVTTL;
NET "genio(39)" LOC = "j17" | IOSTANDARD = LVTTL;
NET "genio(4)" LOC = "r5" | IOSTANDARD = LVTTL;
NET "genio(40)" LOC = "e19" | IOSTANDARD = LVTTL;
NET "genio(41)" LOC = "f18" | IOSTANDARD = LVTTL;
NET "genio(42)" LOC = "e20" | IOSTANDARD = LVTTL;
NET "genio(43)" LOC = "f19" | IOSTANDARD = LVTTL;
NET "genio(44)" LOC = "f20" | IOSTANDARD = LVTTL;
NET "genio(45)" LOC = "f21" | IOSTANDARD = LVTTL;
NET "genio(46)" LOC = "e22" | IOSTANDARD = LVTTL;
NET "genio(47)" LOC = "e18" | IOSTANDARD = LVTTL;
NET "genio(48)" LOC = "g20" | IOSTANDARD = LVTTL;
NET "genio(49)" LOC = "h19" | IOSTANDARD = LVTTL;
NET "genio(5)" LOC = "p6" | IOSTANDARD = LVTTL;
NET "genio(50)" LOC = "h18" | IOSTANDARD = LVTTL;
NET "genio(51)" LOC = "j19" | IOSTANDARD = LVTTL;
NET "genio(52)" LOC = "k20" | IOSTANDARD = LVTTL;
NET "genio(53)" LOC = "k19" | IOSTANDARD = LVTTL;
NET "genio(54)" LOC = "l20" | IOSTANDARD = LVTTL;
NET "genio(55)" LOC = "l21" | IOSTANDARD = LVTTL;
NET "genio(56)" LOC = "m20" | IOSTANDARD = LVTTL;
NET "genio(57)" LOC = "m19" | IOSTANDARD = LVTTL;
NET "genio(58)" LOC = "m22" | IOSTANDARD = LVTTL;
NET "genio(59)" LOC = "m21" | IOSTANDARD = LVTTL;
NET "genio(6)" LOC = "t2" | IOSTANDARD = LVTTL;
NET "genio(7)" LOC = "t1" | IOSTANDARD = LVTTL;
NET "genio(8)" LOC = "u4" | IOSTANDARD = LVTTL;
NET "genio(9)" LOC = "t4" | IOSTANDARD = LVTTL;
NET "iosn" LOC = "u12" | IOSTANDARD = LVTTL;
#NET "led(0)" LOC = "f11" | IOSTANDARD = LVTTL;
#NET "led(1)" LOC = "e11" | IOSTANDARD = LVTTL;
#NET "led(2)" LOC = "d11" | IOSTANDARD = LVTTL;
#NET "led(3)" LOC = "c11" | IOSTANDARD = LVTTL;
#NET "lvdsion(0)" LOC = "m2" | IOSTANDARD = LVTTL;
#NET "lvdsion(1)" LOC = "m1" | IOSTANDARD = LVTTL;
#NET "lvdsion(10)" LOC = "w2" | IOSTANDARD = LVTTL;
#NET "lvdsion(11)" LOC = "w1" | IOSTANDARD = LVTTL;
#NET "lvdsion(2)" LOC = "v4" | IOSTANDARD = LVTTL;
#NET "lvdsion(3)" LOC = "v3" | IOSTANDARD = LVTTL;
#NET "lvdsion(4)" LOC = "m4" | IOSTANDARD = LVTTL;
#NET "lvdsion(5)" LOC = "m3" | IOSTANDARD = LVTTL;
#NET "lvdsion(6)" LOC = "n2" | IOSTANDARD = LVTTL;
#NET "lvdsion(7)" LOC = "n1" | IOSTANDARD = LVTTL;
#NET "lvdsion(8)" LOC = "n4" | IOSTANDARD = LVTTL;
#NET "lvdsion(9)" LOC = "n3" | IOSTANDARD = LVTTL;
#NET "lvdsiop(0)" LOC = "p2" | IOSTANDARD = LVTTL;
#NET "lvdsiop(1)" LOC = "p1" | IOSTANDARD = LVTTL;
#NET "lvdsiop(10)" LOC = "p5" | IOSTANDARD = LVTTL;
#NET "lvdsiop(11)" LOC = "p4" | IOSTANDARD = LVTTL;
#NET "lvdsiop(2)" LOC = "r2" | IOSTANDARD = LVTTL;
#NET "lvdsiop(3)" LOC = "r1" | IOSTANDARD = LVTTL;
#NET "lvdsiop(4)" LOC = "t3" | IOSTANDARD = LVTTL;
#NET "lvdsiop(5)" LOC = "r4" | IOSTANDARD = LVTTL;
#NET "lvdsiop(6)" LOC = "v2" | IOSTANDARD = LVTTL;
#NET "lvdsiop(7)" LOC = "v1" | IOSTANDARD = LVTTL;
#NET "lvdsiop(8)" LOC = "u3" | IOSTANDARD = LVTTL;
#NET "lvdsiop(9)" LOC = "u2" | IOSTANDARD = LVTTL;
NET "oen" LOC = "ab4" | IOSTANDARD = LVTTL;
NET "pio(0)" LOC = "h5" | IOSTANDARD = LVTTL;
NET "pio(1)" LOC = "g5" | IOSTANDARD = LVTTL;
NET "pio(10)" LOC = "j5" | IOSTANDARD = LVTTL;
NET "pio(11)" LOC = "j6" | IOSTANDARD = LVTTL;
NET "pio(12)" LOC = "j1" | IOSTANDARD = LVTTL;
NET "pio(13)" LOC = "j2" | IOSTANDARD = LVTTL;
NET "pio(14)" LOC = "k5" | IOSTANDARD = LVTTL;
NET "pio(15)" LOC = "k6" | IOSTANDARD = LVTTL;
NET "pio(2)" LOC = "g3" | IOSTANDARD = LVTTL;
NET "pio(3)" LOC = "g4" | IOSTANDARD = LVTTL;
NET "pio(4)" LOC = "g1" | IOSTANDARD = LVTTL;
NET "pio(5)" LOC = "g2" | IOSTANDARD = LVTTL;
NET "pio(6)" LOC = "h1" | IOSTANDARD = LVTTL;
NET "pio(7)" LOC = "h2" | IOSTANDARD = LVTTL;
NET "pio(8)" LOC = "j4" | IOSTANDARD = LVTTL;
NET "pio(9)" LOC = "h4" | IOSTANDARD = LVTTL;
NET "pllref" LOC = "v8" | IOSTANDARD = LVTTL;# sdclkfb
NET "ps2clk(0)" LOC = "b10" | IOSTANDARD = LVTTL;
NET "ps2clk(1)" LOC = "e10" | IOSTANDARD = LVTTL;
NET "ps2data(0)" LOC = "c10" | IOSTANDARD = LVTTL;
NET "ps2data(1)" LOC = "f10" | IOSTANDARD = LVTTL;
NET "ramoen(0)" LOC = "u10" | IOSTANDARD = LVTTL;
NET "ramoen(1)" LOC = "u11" | IOSTANDARD = LVTTL;
NET "ramoen(2)" LOC = "v10" | IOSTANDARD = LVTTL;
NET "ramoen(3)" LOC = "u9" | IOSTANDARD = LVTTL;
NET "ramoen(4)" LOC = "u7" | IOSTANDARD = LVTTL;
NET "ramsn(0)" LOC = "aa4" | IOSTANDARD = LVTTL;
NET "ramsn(1)" LOC = "y5" | IOSTANDARD = LVTTL;
NET "ramsn(2)" LOC = "w5" | IOSTANDARD = LVTTL;
NET "ramsn(3)" LOC = "ab5" | IOSTANDARD = LVTTL;
NET "ramsn(4)" LOC = "aa5" | IOSTANDARD = LVTTL;
NET "read" LOC = "v12" | IOSTANDARD = LVTTL;
NET "resetn" LOC = "l2" | IOSTANDARD = LVTTL;
NET "romsn(0)" LOC = "y4" | IOSTANDARD = LVTTL;
NET "romsn(1)" LOC = "v7" | IOSTANDARD = LVTTL;
NET "rtsn1" LOC = "l6" | IOSTANDARD = LVTTL;
NET "rtsn2" LOC = "k4" | IOSTANDARD = LVTTL;
NET "rwen(0)" LOC = "aa6" | IOSTANDARD = LVTTL;
NET "rwen(1)" LOC = "y7" | IOSTANDARD = LVTTL;
NET "rwen(2)" LOC = "y6" | IOSTANDARD = LVTTL;
NET "rwen(3)" LOC = "w7" | IOSTANDARD = LVTTL;
NET "rxd1" LOC = "l3" | IOSTANDARD = LVTTL;
NET "rxd2" LOC = "k1" | IOSTANDARD = LVTTL;
NET "sdcasn" LOC = "ab9" | IOSTANDARD = LVTTL;
NET "sdclk" LOC = "w8" | IOSTANDARD = LVTTL;
NET "sdcsn(0)" LOC = "ab8" | IOSTANDARD = LVTTL;
NET "sdcsn(1)" LOC = "w9" | IOSTANDARD = LVTTL;
NET "sddqm(0)" LOC = "aa8" | IOSTANDARD = LVTTL;
NET "sddqm(1)" LOC = "v11" | IOSTANDARD = LVTTL;
NET "sddqm(2)" LOC = "ab10" | IOSTANDARD = LVTTL;
NET "sddqm(3)" LOC = "w10" | IOSTANDARD = LVTTL;
NET "sdrasn" LOC = "aa9" | IOSTANDARD = LVTTL;
NET "sdwen" LOC = "aa10" | IOSTANDARD = LVTTL;
 
NET "spw_rxdp(0)" LOC = "m1";# | IOSTANDARD = LVDS_25;
NET "spw_rxdn(0)" LOC = "m2";# | IOSTANDARD = LVDS_25;
NET "spw_rxsp(0)" LOC = "m3";# | IOSTANDARD = LVDS_25;
NET "spw_rxsn(0)" LOC = "m4";# | IOSTANDARD = LVDS_25;
NET "spw_txdp(0)" LOC = "n1";# | IOSTANDARD = LVDS_25;
NET "spw_txdn(0)" LOC = "n2";# | IOSTANDARD = LVDS_25;
NET "spw_txsp(0)" LOC = "n3";# | IOSTANDARD = LVDS_25;
NET "spw_txsn(0)" LOC = "n4";# | IOSTANDARD = LVDS_25;
NET "spw_rxdp(1)" LOC = "p1";# | IOSTANDARD = LVDS_25;
NET "spw_rxdn(1)" LOC = "p2";# | IOSTANDARD = LVDS_25;
NET "spw_rxsp(1)" LOC = "p4";# | IOSTANDARD = LVDS_25;
NET "spw_rxsn(1)" LOC = "p5";# | IOSTANDARD = LVDS_25;
NET "spw_txdp(1)" LOC = "r1";# | IOSTANDARD = LVDS_25;
NET "spw_txdn(1)" LOC = "r2";# | IOSTANDARD = LVDS_25;
NET "spw_txsp(1)" LOC = "r4";# | IOSTANDARD = LVDS_25;
NET "spw_txsn(1)" LOC = "t3";# | IOSTANDARD = LVDS_25;
NET "spw_rxdp(2)" LOC = "v1";# | IOSTANDARD = LVDS_25;
NET "spw_rxdn(2)" LOC = "v2";# | IOSTANDARD = LVDS_25;
NET "spw_rxsp(2)" LOC = "u2";# | IOSTANDARD = LVDS_25;
NET "spw_rxsn(2)" LOC = "u3";# | IOSTANDARD = LVDS_25;
NET "spw_txdp(2)" LOC = "w1";# | IOSTANDARD = LVDS_25;
NET "spw_txdn(2)" LOC = "w2";# | IOSTANDARD = LVDS_25;
NET "spw_txsp(2)" LOC = "v3";# | IOSTANDARD = LVDS_25;
NET "spw_txsn(2)" LOC = "v4";# | IOSTANDARD = LVDS_25;
 
NET "switch(0)" LOC = "f16" | IOSTANDARD = LVTTL;
NET "switch(1)" LOC = "f13" | IOSTANDARD = LVTTL;
#NET "pio(0)" LOC = "f16" | IOSTANDARD = LVTTL;
#NET "pio(1)" LOC = "f13" | IOSTANDARD = LVTTL;
NET "switch(2)" LOC = "f12" | IOSTANDARD = LVTTL;
NET "switch(3)" LOC = "e16" | IOSTANDARD = LVTTL;
NET "switch(4)" LOC = "c22" | IOSTANDARD = LVTTL;
NET "switch(5)" LOC = "c20" | IOSTANDARD = LVTTL;
NET "switch(6)" LOC = "c21" | IOSTANDARD = LVTTL;
#NET "switch(7)" LOC = "d20" | IOSTANDARD = LVTTL;
NET "switch(8)" LOC = "d19" | IOSTANDARD = LVTTL;
#NET "switch(9)" LOC = "d21" | IOSTANDARD = LVTTL;
NET "txd1" LOC = "l4" | IOSTANDARD = LVTTL;
NET "txd2" LOC = "k2" | IOSTANDARD = LVTTL;
NET "usb_clkout" LOC = "c12" | IOSTANDARD = LVTTL;
NET "usb_clock" LOC = "b12" | IOSTANDARD = LVTTL;
NET "usb_d(0)" LOC = "c13" | IOSTANDARD = LVTTL;
NET "usb_d(1)" LOC = "b14" | IOSTANDARD = LVTTL;
NET "usb_d(10)" LOC = "a16" | IOSTANDARD = LVTTL;
NET "usb_d(11)" LOC = "d16" | IOSTANDARD = LVTTL;
NET "usb_d(12)" LOC = "c16" | IOSTANDARD = LVTTL;
NET "usb_d(13)" LOC = "c17" | IOSTANDARD = LVTTL;
NET "usb_d(14)" LOC = "b17" | IOSTANDARD = LVTTL;
NET "usb_d(15)" LOC = "e17" | IOSTANDARD = LVTTL;
NET "usb_d(2)" LOC = "a14" | IOSTANDARD = LVTTL;
NET "usb_d(3)" LOC = "e14" | IOSTANDARD = LVTTL;
NET "usb_d(4)" LOC = "d14" | IOSTANDARD = LVTTL;
NET "usb_d(5)" LOC = "a15" | IOSTANDARD = LVTTL;
NET "usb_d(6)" LOC = "b15" | IOSTANDARD = LVTTL;
NET "usb_d(7)" LOC = "e15" | IOSTANDARD = LVTTL;
NET "usb_d(8)" LOC = "d15" | IOSTANDARD = LVTTL;
NET "usb_d(9)" LOC = "b16" | IOSTANDARD = LVTTL;
NET "usb_enablen" LOC = "b18" | IOSTANDARD = LVTTL;
NET "usb_faultn" LOC = "c19" | IOSTANDARD = LVTTL;
NET "usb_linestate(0)" LOC = "a19" | IOSTANDARD = LVTTL;
NET "usb_linestate(1)" LOC = "b19" | IOSTANDARD = LVTTL;
NET "usb_opmode(0)" LOC = "d18" | IOSTANDARD = LVTTL;
NET "usb_opmode(1)" LOC = "c18" | IOSTANDARD = LVTTL;
NET "usb_reset" LOC = "b20" | IOSTANDARD = LVTTL;
NET "usb_rxactive" LOC = "b13" | IOSTANDARD = LVTTL;
NET "usb_rxerror" LOC = "a13" | IOSTANDARD = LVTTL;
NET "usb_rxvalid" LOC = "f17" | IOSTANDARD = LVTTL;
NET "usb_suspend" LOC = "a18" | IOSTANDARD = LVTTL;
NET "usb_termsel" LOC = "d13" | IOSTANDARD = LVTTL;
NET "usb_txready" LOC = "e13" | IOSTANDARD = LVTTL;
NET "usb_txvalid" LOC = "f14" | IOSTANDARD = LVTTL;
NET "usb_validh" LOC = "e12" | IOSTANDARD = LVTTL;
NET "usb_vbus" LOC = "a12" | IOSTANDARD = LVTTL;
NET "usb_xcvrsel" LOC = "d12" | IOSTANDARD = LVTTL;
NET "vid_b(0)" LOC = "a7" | IOSTANDARD = LVTTL;
NET "vid_b(1)" LOC = "e8" | IOSTANDARD = LVTTL;
NET "vid_b(2)" LOC = "d8" | IOSTANDARD = LVTTL;
NET "vid_b(3)" LOC = "b8" | IOSTANDARD = LVTTL;
NET "vid_b(4)" LOC = "a8" | IOSTANDARD = LVTTL;
NET "vid_b(5)" LOC = "f9" | IOSTANDARD = LVTTL;
NET "vid_b(6)" LOC = "e9" | IOSTANDARD = LVTTL;
NET "vid_b(7)" LOC = "b9" | IOSTANDARD = LVTTL;
NET "vid_blankn" LOC = "b7" | IOSTANDARD = LVTTL;
NET "vid_clock" LOC = "b11" | IOSTANDARD = LVTTL;
NET "vid_g(0)" LOC = "b5" | IOSTANDARD = LVTTL;
NET "vid_g(1)" LOC = "a5" | IOSTANDARD = LVTTL;
NET "vid_g(2)" LOC = "e6" | IOSTANDARD = LVTTL;
NET "vid_g(3)" LOC = "d6" | IOSTANDARD = LVTTL;
NET "vid_g(4)" LOC = "c6" | IOSTANDARD = LVTTL;
NET "vid_g(5)" LOC = "b6" | IOSTANDARD = LVTTL;
NET "vid_g(6)" LOC = "e7" | IOSTANDARD = LVTTL;
NET "vid_g(7)" LOC = "d7" | IOSTANDARD = LVTTL;
NET "vid_hsync" LOC = "c7" | IOSTANDARD = LVTTL;
NET "vid_r(0)" LOC = "a10" | IOSTANDARD = LVTTL;
NET "vid_r(1)" LOC = "d10" | IOSTANDARD = LVTTL;
NET "vid_r(2)" LOC = "d9" | IOSTANDARD = LVTTL;
NET "vid_r(3)" LOC = "f6" | IOSTANDARD = LVTTL;
NET "vid_r(4)" LOC = "b4" | IOSTANDARD = LVTTL;
NET "vid_r(5)" LOC = "a4" | IOSTANDARD = LVTTL;
NET "vid_r(6)" LOC = "d5" | IOSTANDARD = LVTTL;
NET "vid_r(7)" LOC = "c5" | IOSTANDARD = LVTTL;
NET "vid_sda" LOC = "a3" | IOSTANDARD = LVTTL;
NET "vid_sdc" LOC = "a9" | IOSTANDARD = LVTTL;
NET "vid_syncn" LOC = "f7" | IOSTANDARD = LVTTL;
NET "vid_vsync" LOC = "e5" | IOSTANDARD = LVTTL;
NET "wdogn" LOC = "l1" | IOSTANDARD = LVTTL;
NET "writen" LOC = "aa3" | IOSTANDARD = LVTTL;
 
#NET "dsutx" LOC = "l4" | IOSTANDARD = LVTTL ;#txd1
#NET "dsurx" LOC = "l3" | IOSTANDARD = LVTTL ;#rxd1
NET "dsuen" LOC = "d20" | IOSTANDARD = LVTTL ;#switch(7)
NET "dsubre" LOC = "d21" | IOSTANDARD = LVTTL ;#switch(9)
NET "dsuact" LOC = "e11" | IOSTANDARD = LVTTL ;#led(1)
NET "errorn" LOC = "f11" | IOSTANDARD = LVTTL ; #led(0)
NET "pio(16)" LOC = "d11" | IOSTANDARD = LVTTL; # led(2)
NET "pio(17)" LOC = "c11" | IOSTANDARD = LVTTL; # led(3)
 
#NET "can_stb(2)" LOC = "h5" | IOSTANDARD = LVTTL; #pio(0)
#NET "can_rxd(2)" LOC = "g5" | IOSTANDARD = LVTTL; #pio(1)
#NET "can_txd(2)" LOC = "g3" | IOSTANDARD = LVTTL; #pio(2)
#NET "can_stb(1)" LOC = "g4" | IOSTANDARD = LVTTL; #pio(3)
#NET "can_rxd(1)" LOC = "g1" | IOSTANDARD = LVTTL; #pio(4)
#NET "can_txd(1)" LOC = "g2" | IOSTANDARD = LVTTL; #pio(5)
 
NET "ata_rstn" LOC = "d22" | IOSTANDARD = LVTTL; #genio(20)
NET "ata_data(7)" LOC = "g17" | IOSTANDARD = LVTTL; #genio(21)
NET "ata_data(6)" LOC = "e21" | IOSTANDARD = LVTTL; #genio(22)
NET "ata_data(5)" LOC = "g22" | IOSTANDARD = LVTTL; #genio(23)
NET "ata_data(4)" LOC = "g21" | IOSTANDARD = LVTTL; #genio(24)
NET "ata_data(3)" LOC = "g19" | IOSTANDARD = LVTTL; #genio(25)
NET "ata_data(2)" LOC = "h22" | IOSTANDARD = LVTTL; #genio(26)
NET "ata_data(1)" LOC = "g18" | IOSTANDARD = LVTTL; #genio(27)
NET "ata_data(0)" LOC = "j18" | IOSTANDARD = LVTTL; #genio(28)
#NET "genio(29)" LOC = "j21" | IOSTANDARD = LVTTL; #genio(29) / not used
NET "ata_dmarq" LOC = "j22" | IOSTANDARD = LVTTL | PULLDOWN; #genio(30) / DMARQ
NET "ata_diow" LOC = "h21" | IOSTANDARD = LVTTL; #genio(31) / nDIOW
NET "ata_dior" LOC = "k22" | IOSTANDARD = LVTTL; #genio(32) / DIOR
NET "ata_iordy" LOC = "k21" | IOSTANDARD = LVTTL | PULLUP; #genio(33) / IORDY
NET "ata_dmack" LOC = "k18" | IOSTANDARD = LVTTL; #genio(34) / nDMACK
NET "ata_intrq" LOC = "l19" | IOSTANDARD = LVTTL | PULLDOWN; #genio(35) / INTRQ
NET "ata_da(1)" LOC = "l18" | IOSTANDARD = LVTTL; #genio(36) / DA1
NET "ata_da(0)" LOC = "k17" | IOSTANDARD = LVTTL; #genio(37) / DA0
NET "ata_cs0" LOC = "l17" | IOSTANDARD = LVTTL; #genio(38) / nCS0
NET "ata_dasp" LOC = "j17" | IOSTANDARD = LVTTL; #genio(39) / nDASP
 
#NET "genio(40)" LOC = "e19" | IOSTANDARD = LVTTL; #genio(40) / not used
NET "ata_data(8)" LOC = "f18" | IOSTANDARD = LVTTL; #genio(41)
NET "ata_data(9)" LOC = "e20" | IOSTANDARD = LVTTL; #genio(42)
NET "ata_data(10)" LOC = "f19" | IOSTANDARD = LVTTL; #genio(43)
NET "ata_data(11)" LOC = "f20" | IOSTANDARD = LVTTL; #genio(44)
NET "ata_data(12)" LOC = "f21" | IOSTANDARD = LVTTL; #genio(45)
NET "ata_data(13)" LOC = "e22" | IOSTANDARD = LVTTL; #genio(46)
NET "ata_data(14)" LOC = "e18" | IOSTANDARD = LVTTL; #genio(47)
NET "ata_data(15)" LOC = "g20" | IOSTANDARD = LVTTL; #genio(48)
#NET "genio(49)" LOC = "h19" | IOSTANDARD = LVTTL; #genio(49) / not used
#NET "genio(50)" LOC = "h18" | IOSTANDARD = LVTTL; #genio(50) / not used
#NET "genio(51)" LOC = "j19" | IOSTANDARD = LVTTL; #genio(51) / not used
#NET "genio(52)" LOC = "k20" | IOSTANDARD = LVTTL; #genio(52) / not used
NET "ata_csel" LOC = "k19" | IOSTANDARD = LVTTL; #genio(53) / Cable SEL
#NET "genio(54)" LOC = "l20" | IOSTANDARD = LVTTL; #genio(54) / not used
#NET "genio(55)" LOC = "l21" | IOSTANDARD = LVTTL; #genio(55) / not used
#NET "genio(56)" LOC = "m20" | IOSTANDARD = LVTTL; #genio(56) / nPDIAG
NET "ata_da(2)" LOC = "m19" | IOSTANDARD = LVTTL; #genio(57)
NET "ata_cs1" LOC = "m22" | IOSTANDARD = LVTTL; #genio(58)
#NET "genio(59)" LOC = "m21" | IOSTANDARD = LVTTL; #genio(59)
 
 
CONFIG PROHIBIT = "aa14"; #"fpgadata"
CONFIG PROHIBIT = "w12"; #"fpgainit"
 
 
 
/spwamba_gr-xc3s1500/config.in
0,0 → 1,100
 
# LEON3 configuration written in linux configuration language
#
# Written by Jiri Gaisler, Gaisler Research
#
# Comments and bug reports to jiri@gaisler.com
#
#
 
#define_bool CONFIG_MCTRL_RMW y
 
mainmenu_name "LEON3MP Design Configuration"
 
mainmenu_option next_comment
comment 'Synthesis '
source lib/techmap/gencomp/tech.in
choice 'FPGA type ' \
"XC3S-1500 CONFIG_FPGA_1500 \
XC3S-2000 CONFIG_FPGA_2000" XC3S-1500
 
endmenu
 
mainmenu_option next_comment
comment 'Clock generation'
source lib/techmap/clocks/clkgen.in
endmenu
 
source lib/gaisler/leon3/leon3.in
source lib/grlib/amba/amba.in
 
mainmenu_option next_comment
comment 'Debug Link '
source lib/gaisler/uart/dcom.in
source lib/gaisler/jtag/jtag.in
source lib/gaisler/usb/grusb_dcl.in
source lib/gaisler/net/edcl.in
endmenu
 
mainmenu_option next_comment
comment 'Peripherals '
 
mainmenu_option next_comment
comment 'Memory controller '
source lib/esa/memoryctrl/mctrl.in
source lib/gaisler/misc/ahbstat.in
endmenu
 
mainmenu_option next_comment
comment 'On-chip RAM/ROM '
# source lib/gaisler/misc/ahbrom.in
source lib/gaisler/misc/ahbram.in
endmenu
 
mainmenu_option next_comment
comment 'Ethernet '
source lib/gaisler/greth/greth.in
endmenu
 
mainmenu_option next_comment
comment 'IDE Disk controller '
source lib/gaisler/ata/ata.in
endmenu
 
mainmenu_option next_comment
comment 'CAN '
source lib/gaisler/can/can_mc.in
endmenu
 
mainmenu_option next_comment
comment 'USB 2.0 Device Controller '
source lib/gaisler/usb/grusbdc.in
endmenu
 
mainmenu_option next_comment
comment 'UART, timer, I/O port and interrupt controller'
source lib/gaisler/uart/uart1.in
if [ "$CONFIG_DSU_UART" != "y" ]; then
source lib/gaisler/uart/uart2.in
fi
source lib/gaisler/leon3/irqmp.in
source lib/gaisler/misc/gptimer.in
source lib/gaisler/misc/grgpio.in
endmenu
 
# NOTE: Gaisler SpaceWire core removed to make room for SpaceWire Light
# mainmenu_option next_comment
# comment 'Spacewire '
# source lib/gaisler/spacewire/spacewire.in
# endmenu
 
mainmenu_option next_comment
comment 'Keybord and VGA interface'
source lib/gaisler/misc/ps2vga.in
endmenu
endmenu
 
mainmenu_option next_comment
comment 'VHDL Debugging '
source lib/grlib/util/debug.in
endmenu
/spwamba_gr-xc3s1500/config.vhd.in
0,0 → 1,20
#include "config.h"
#include "tkconfig.h"
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
 
 
library techmap;
use techmap.gencomp.all;
 
package config is
 
#include "config.vhd.h"
 
-- SpaceWire Light always enabled (one link)
constant CFG_SPW_EN: integer := 1;
constant CFG_SPW_NUM: integer := 1;
 
end;
/spwamba_gr-xc3s1500/Makefile
0,0 → 1,48
#
# Makefile for a LEON3 with SpaceWire Light on a Pender GR-XC3S1500 board.
#
 
-include .config
 
# Change this to your local GRLIB directory.
GRLIB = /data/leon3/grlib-gpl-1.0.22-b4095
 
TOP=leon3mp
BOARD=gr-xc3s-1500
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=leon3mp.ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=high
ISEMAPOPT=-timing
XSTOPT=
SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
SDCFILE=default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
VCOMOPT=-explicit
TECHLIBS = unisim
 
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
tmtc openchip hynix cypress ihp gleichmann gsi fmf spansion
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest ddr \
haps ascs slink coremp7
FILESKIP = grcan.vhd
 
RTLDIR = ../../rtl/vhdl
VHDLSYNFILES = config.vhd leon3mp.vhd \
$(RTLDIR)/spwpkg.vhd \
$(RTLDIR)/spwlink.vhd \
$(RTLDIR)/spwrecv.vhd \
$(RTLDIR)/spwxmit.vhd \
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd \
$(RTLDIR)/spwambapkg.vhd \
$(RTLDIR)/spwamba.vhd \
$(RTLDIR)/spwahbmst.vhd \
 
include $(GRLIB)/bin/Makefile
 
.config:
cp -a defconfig .config
 
/spwamba_gr-xc3s1500/leon3mp.vhd
0,0 → 1,892
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- Modified by Joris van Rantwijk for use with SpaceWire Light.
------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
use gaisler.ata.all;
 
library esa;
use esa.memoryctrl.all;
 
library unisim;
use unisim.vcomponents.DCM;
 
use work.config.all;
use work.spwpkg.all;
use work.spwambapkg.all;
 
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk3 : in std_ulogic; -- 25 MHz ethernet clock
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
 
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
 
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
 
pio : inout std_logic_vector(17 downto 0); -- I/O port
 
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
 
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
 
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
 
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxsp : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txdp : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txsp : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
 
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic;
 
ata_rstn : out std_logic;
ata_data : inout std_logic_vector(15 downto 0);
ata_da : out std_logic_vector(2 downto 0);
ata_cs0 : out std_logic;
ata_cs1 : out std_logic;
ata_dior : out std_logic;
ata_diow : out std_logic;
ata_iordy : in std_logic;
ata_intrq : in std_logic;
ata_dmarq : in std_logic;
ata_dmack : out std_logic;
--ata_dasp : in std_logic
ata_csel : out std_logic
 
);
end;
 
architecture rtl of leon3mp is
 
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
 
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
CFG_ATA+CFG_GRUSBDC;
 
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
 
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
 
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
 
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
 
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
 
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
 
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
 
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
 
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
 
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
 
signal lclk, rst, ndsuact, wdogl : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
 
signal ethclk : std_ulogic;
 
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
 
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_ATA + CFG_GRUSBDC;
 
signal stati : ahbstat_in_type;
 
signal spw_clkl : std_ulogic;
signal spw_tick_in: std_logic;
signal spw_di: std_logic;
signal spw_si: std_logic;
signal spw_do: std_logic;
signal spw_so: std_logic;
 
signal uclk : std_ulogic;
signal usbi : grusb_in_type;
signal usbo : grusb_out_type;
 
signal idei : ata_in_type;
signal ideo : ata_out_type;
 
constant SPW_LOOP_BACK : integer := 0;
 
signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute keep of spw_clkl : signal is true;
 
begin
 
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
 
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
 
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
 
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, cgo.clklock, rstn, rstraw);
 
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
 
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
 
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
 
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
 
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
 
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
 
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
 
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
 
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
 
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
 
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
 
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
 
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate
apbo(9) <= apb_none; rtsn2 <= '0';
end generate;
 
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
 
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
end generate;
 
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
 
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
 
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
video_clk <= not ethclk;
end generate;
-- Note: SVGA graphics support removed to make room for SpaceWire Light
assert CFG_SVGA_ENABLE = 0 report "SVGA graphics not supported";
svga : if CFG_SVGA_ENABLE /= 0 generate
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) <= ahbm_none;
apbo(6) <= apb_none;
vgao <= vgao_none;
video_clk <= not clkm;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
end generate;
 
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
video_clk <= not clkm;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
 
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 17 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
 
end generate;
 
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
 
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
 
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 13, paddr => 13, pirq => 13, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
end generate;
 
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
 
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
 
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
 
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
 
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
 
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd(0), vcc(0), can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd(0), vcc(0), can_lrx(1));
end generate;
end generate;
 
-- standby controlled by pio(3) and pio(0)
 
-----------------------------------------------------------------------
--- SpaceWire Light --------------------------------------------------
-----------------------------------------------------------------------
 
spw0: spwamba
generic map (
tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 10,
paddr => 10,
pirq => 10,
sysfreq => real(CPU_FREQ) * 1000.0,
txclkfreq => 200.0e6,
rximpl => impl_fast,
rxchunk => 4,
tximpl => impl_fast,
timecodegen => true,
rxfifosize => 8,
txfifosize => 8,
desctablesize => 10,
maxburst => 3 )
port map (
clk => clkm,
rxclk => spw_clkl,
txclk => spw_clkl,
rstn => rstn,
apbi => apbi,
apbo => apbo(10),
ahbi => ahbmi,
ahbo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
tick_in => spw_tick_in,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
spw_so => spw_so );
 
spw_rxd_pad: inpad_ds
generic map (padtech, lvds, x25v)
port map (spw_rxdp(0), spw_rxdn(0), spw_di);
spw_rxs_pad: inpad_ds
generic map (padtech, lvds, x25v)
port map (spw_rxsp(0), spw_rxsn(0), spw_si);
spw_txd_pad: outpad_ds
generic map (padtech, lvds, x25v)
port map (spw_txdp(0), spw_txdn(0), spw_do, '0');
spw_txs_pad: outpad_ds
generic map (padtech, lvds, x25v)
port map (spw_txsp(0), spw_txsn(0), spw_so, '0');
 
-- Use 2nd GPTIMER unit to generate external tick_in signal.
spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';
 
-- Generate 200 MHz clock for fast receiver/transmitter.
spwclk0: DCM
generic map (
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLK_FEEDBACK => "NONE",
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
STARTUP_WAIT => false )
port map (
CLKIN => lclk,
RST => not rstraw,
CLKFX => spw_clkl );
 
-------------------------------------------------------------------------------
--- USB -----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) /= 0 generate
usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (usb_clkout, uclk);
usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
usb_txready_pad : inpad generic map (tech => padtech)
port map (usb_txready,usbi.txready);
usb_rxvalid_pad : inpad generic map (tech => padtech)
port map (usb_rxvalid,usbi.rxvalid);
usb_rxerror_pad : inpad generic map (tech => padtech)
port map (usb_rxerror,usbi.rxerror);
usb_rxactive_pad : inpad generic map (tech => padtech)
port map (usb_rxactive,usbi.rxactive);
usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
port map (usb_linestate,usbi.linestate);
usb_vbus_pad : inpad generic map (tech => padtech)
port map (usb_vbus, usbi.vbusvalid);
usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_reset,usbo.reset);
usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_suspend,usbo.suspendm);
usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_termsel,usbo.termselect);
usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_xcvrsel,usbo.xcvrselect(0));
usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_txvalid,usbo.txvalid);
usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
port map (usb_opmode,usbo.opmode);
 
usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
 
end generate;
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 5, hirq => 9, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech)
port map(
uclk => uclk,
usbi => usbi,
usbo => usbo,
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
ahbsi => ahbsi,
ahbso => ahbso(5)
);
end generate usbdc0;
 
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
port map (
uclk, usbi, usbo, clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
CFG_SPW_NUM*CFG_SPW_EN));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- AHB ATA ----------------------------------------------------------
-----------------------------------------------------------------------
 
ata0 : if CFG_ATA = 1 generate
atac0 : atactrl
generic map(
tech => 0, fdepth => CFG_ATAFIFO,
mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
CFG_GRUSBDC,
shindex => 3, haddr => 16#A00#, hmask => 16#fff#, pirq => CFG_ATAIRQ,
mwdma => CFG_ATADMA, TWIDTH => 8,
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 => 6, -- 70ns
PIO_mode0_T2 => 28, -- 290ns
PIO_mode0_T4 => 2, -- 30ns
PIO_mode0_Teoc => 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
)
port map(
rst => rstn, arst => vcc(0), clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+
CFG_GRUSB_DCL+CFG_GRUSBDC),
ahbsi => ahbsi, ahbso => ahbso(3), atai => idei, atao => ideo);
ata_rstn_pad : outpad generic map (tech => padtech)
port map (ata_rstn, ideo.rstn);
ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
port map (ata_data, ideo.ddo, ideo.oen, idei.ddi);
ata_da_pad : outpadv generic map (tech => padtech, width => 3)
port map (ata_da, ideo.da);
ata_cs0_pad : outpad generic map (tech => padtech)
port map (ata_cs0, ideo.cs0);
ata_cs1_pad : outpad generic map (tech => padtech)
port map (ata_cs1, ideo.cs1);
ata_dior_pad : outpad generic map (tech => padtech)
port map (ata_dior, ideo.dior);
ata_diow_pad : outpad generic map (tech => padtech)
port map (ata_diow, ideo.diow);
iordy_pad : inpad generic map (tech => padtech)
port map (ata_iordy, idei.iordy);
intrq_pad : inpad generic map (tech => padtech)
port map (ata_intrq, idei.intrq);
dmarq_pad : inpad generic map (tech => padtech)
port map (ata_dmarq, idei.dmarq);
dmack_pad : outpad generic map (tech => padtech)
port map (ata_dmack, ideo.dmack);
ata_csel <= '0';
end generate;
 
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
 
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
 
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
 
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
/streamtest_gr-xc3s1500/streamtest.ucf
5,11 → 5,14
TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal, - 1 ns margin = 4 ns
# fastclk = 200 MHz = 5 ns nominal
# 3 ns data path + 1 ns source skew + 1 ns destination skew = 5 ns
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;
NET "sysclk" MAXSKEW = 1 ns ;
NET "fastclk" MAXSKEW = 1 ns ;
 
# Board clock
NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL;

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