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URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

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  • This comparison shows the changes necessary to convert path
    /spacewire_light/trunk/syn
    from Rev 5 to Rev 6
    Reverse comparison

Rev 5 → Rev 6

/spwamba_gr-xc3s1500/leon3mp.vhd
45,8 → 45,16
use unisim.vcomponents.DCM;
 
use work.config.all;
 
-- These statements are used in case SpaceWire Light is synthesized locally,
-- separate from the rest of GRLIB.
use work.spwpkg.all;
use work.spwambapkg.all;
---- The following statements should be used instead if SpaceWire Light
---- has been integrated into GRLIB.
-- library opencores;
-- use opencores.spwpkg.all;
-- use opencores.spwambapkg.all;
 
entity leon3mp is
generic (
/streamtest_digilent-xc3s200/streamtest.ucf
5,11 → 5,11
TIMESPEC "TS_clk" = PERIOD "clk50" 18.0 ns ;
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal, - 1 ns margin = 4 ns
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns ;
# fastclk = 200 MHz = 5 ns = 3 ns delay + 2 ns skew
NET "sysclk" TNM_NET = "sysclk" | MAXSKEW = 1 ns;
NET "fastclk" TNM_NET = "fastclk" | MAXSKEW = 1 ns;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;
 
NET "clk50" LOC = "T9" ;
NET "led(0)" LOC = "K12" | DRIVE = 6 ;

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