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URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

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  • This comparison shows the changes necessary to convert path 
    /spi_master_slave/trunk/rtl
    from Rev 8 to Rev 10
    ↔ Reverse comparison
  •

Rev 8 → Rev 10

/spi_loopback.vhd
19,22 → 19,12
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
 
entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
/spi_slave.vhd
12,6 → 12,8
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
-- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
--
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch
104,6 → 106,8
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/06/17 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--
--
-----------------------------------------------------------------------------------------------------------------------
122,7 → 126,7
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2); -- prefetch lookahead cycles
PREFETCH : positive := 3); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
139,16 → 143,21
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
wren_ack_o : out std_logic; -- debug: wren ack from state machine
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (5 downto 0) -- debug: internal state register
-- sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
 
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- the spi bus and core registers are synchronous to the 'spi_sck_i' clock.
-- the parallel write/read interface is synchronous to the 'clk_i' clock.
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
--================================================================================================================
 
architecture RTL of spi_slave is
-- constants to control FlipFlop synthesis
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA);
371,6 → 380,6
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
wren_ack_o_proc: wren_ack_o <= wren_ack_reg;
-- sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture RTL;
 
/spi_master.vhd
133,11 → 133,11
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
-- > verify the receive interface in silicon, and determine the top usable frequency.
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
146,6 → 146,8
use ieee.std_logic_unsigned.all;
 
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
193,7 → 195,7
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
architecture RTL of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
375,13 → 377,13
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
-- REDUCED DEMAND ON MISO SETUP TIME.
--
rx_bit_proc : process (sclk_i) is
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
-- if sclk_i'event and sclk_i = '1' then
-- if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
end if;
end if;
-- end if;
-- end if;
end process rx_bit_proc;
 
--=============================================================================================
562,5 → 564,5
core_ce_o_proc: core_ce_o <= core_ce;
core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
 
end architecture rtl;
end architecture RTL;
 
/readme.txt
34,7 → 34,8
 
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer.
 
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at http://opencores.org/project,spi_master_slave,bugtracker.
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
http://opencores.org/project,spi_master_slave,bugtracker.
 
 
In any case, thank you for testing and using this core.
43,6 → 44,3
Jonny Doin
jdoin@opencores.org
 
 
 
 

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