URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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- This comparison shows the changes necessary to convert path
/spi_master_slave/trunk
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/rtl/spi_slave.vhd
127,8 → 127,9
-- data, the last data word is repeated. |
-- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word, |
-- the slave will send (others => '0') instead. |
-- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'. |
-- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
-- ==== |
174,6 → 175,8
-- circuitry. |
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the |
-- synthesis tool will remove the receive logic from the generated circuitry. |
-- Alternatively, you can remove these ports and related circuitry once the core is verified and |
-- integrated to your circuit. |
--================================================================================================================ |
|
architecture rtl of spi_slave is |
188,7 → 191,7
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can |
-- reduce the usability of the slice registers, due to the need to share the control |
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. |
-- By using GSR for the initialization, and reducing RESET local init to the bare |
-- By using GSR for the initialization, and reducing RESET local init to the really |
-- essential, the model achieves better LUT/FF packing and CLB usability. |
------------------------------------------------------------------------------------------ |
-- internal state signals for register and combinatorial stages |
198,9 → 201,10
signal sh_next : std_logic_vector (N-1 downto 0); |
signal sh_reg : std_logic_vector (N-1 downto 0); |
-- mosi and miso connections |
signal rx_bit_next : std_logic; |
signal rx_bit_next : std_logic; -- sample of MOSI input |
signal tx_bit_next : std_logic; |
signal tx_bit_reg : std_logic; |
signal tx_bit_reg : std_logic; -- drives MISO during sequential logic |
signal preload_miso : std_logic; -- controls the MISO MUX |
-- buffered di_i data signals for register and combinatorial stages |
signal di_reg : std_logic_vector (N-1 downto 0); |
-- internal wren_i stretcher for fsm combinatorial stage |
308,12 → 312,14
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
-- state fsm register (fdr) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
-- rtl core registers (fd) |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
321,7 → 327,15
di_req_reg <= di_req_next; -- input data request |
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization |
end if; |
-- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1) |
-- miso MUX preload control register (fdp) |
if spi_ssel_i = '1' then -- async preset |
preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected |
elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output |
preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK |
end if; |
-- FFD registers clocked on CHANGE edge |
-- tx_bit register (fd) |
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then |
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb |
end if; |
418,16 → 432,16
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output |
|
----------------------------------------------------------------------------------------------- |
-- MISO driver process: copy next tx bit at reset |
-- MISO driver process: preload top bit of parallel data to MOSI at reset |
----------------------------------------------------------------------------------------------- |
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit |
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic. |
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is |
spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is |
begin |
if spi_ssel_i = '1' then |
spi_miso_o <= tx_bit_next; -- copy next => reg at reset |
if preload_miso = '1' then |
spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset |
else |
spi_miso_o <= tx_bit_reg; |
spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation |
end if; |
end process spi_miso_o_proc; |
|
/rtl/spi_master.vhd
166,6 → 166,8
-- circuitry. |
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the |
-- synthesis tool will remove the receive logic from the generated circuitry. |
-- Alternatively, you can remove these ports and related circuitry once the core is verified and |
-- integrated to your circuit. |
--================================================================================================================ |
|
entity spi_master is |
211,7 → 213,7
-- all signals are clocked at the rising edge of the system clock 'sclk_i'. |
--================================================================================================================ |
architecture rtl of spi_master is |
-- core clocks, generated from 'sclk_i': initialized to differential values |
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values |
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic |
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic |
signal core_ce : std_logic := '0'; -- core clock enable, positive logic |
304,7 → 306,7
-- In order to preserve global clocking resources, the core clocking scheme is completely based |
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm, |
-- the spi clock generator and the input sampling clock. |
-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock |
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock |
-- for the core clocking. |
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only |
-- differential interconnect delay skew. |
/syn/spi_master_atlys_top_bitgen.xwbt
1,8 → 1,8
INTSTYLE=ise |
INFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.ncd |
OUTFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.bit |
INFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.ncd |
OUTFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.bit |
FAMILY=Spartan6 |
PART=xc6slx45-2csg324 |
WORKINGDIR=C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn |
WORKINGDIR=C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn |
LICENSE=WebPack |
USER_INFO=205970357_0_0_751 |
/syn/spi_master_atlys_top.twr
36,20 → 36,20
|Max Setup to| Process |Max Hold to | Process | | Clock | |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | |
------------+------------+------------+------------+------------+------------------+--------+ |
btn_i<0> | 3.278(R)| SLOW | -1.955(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<1> | 2.687(R)| SLOW | -1.446(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<2> | 2.472(R)| SLOW | -1.378(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<3> | 2.485(R)| SLOW | -1.363(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<4> | 3.029(R)| SLOW | -1.604(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<5> | 2.674(R)| SLOW | -1.430(R)| SLOW |gclk_i_BUFGP | 0.000| |
sw_i<0> | 4.100(R)| SLOW | -2.174(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<1> | 5.263(R)| SLOW | -2.981(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<2> | 5.340(R)| SLOW | -2.970(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<3> | 4.839(R)| SLOW | -2.685(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<4> | 3.689(R)| SLOW | -2.001(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<5> | 4.210(R)| SLOW | -2.310(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<6> | 4.396(R)| SLOW | -2.450(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<7> | 4.807(R)| SLOW | -2.644(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<0> | 3.220(R)| SLOW | -1.908(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<1> | 2.732(R)| SLOW | -1.473(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<2> | 2.624(R)| SLOW | -1.423(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<3> | 2.466(R)| SLOW | -1.367(R)| SLOW |gclk_i_BUFGP | 0.000| |
btn_i<4> | 2.808(R)| SLOW | -1.482(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<5> | 2.631(R)| SLOW | -1.435(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<0> | 4.138(R)| SLOW | -2.205(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<1> | 5.757(R)| SLOW | -3.265(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<2> | 5.825(R)| SLOW | -3.246(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<3> | 4.946(R)| SLOW | -2.785(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<4> | 3.431(R)| SLOW | -1.904(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<5> | 3.569(R)| SLOW | -2.000(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<6> | 3.411(R)| SLOW | -1.943(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<7> | 5.265(R)| SLOW | -2.971(R)| FAST |gclk_i_BUFGP | 0.000| |
------------+------------+------------+------------+------------+------------------+--------+ |
|
Clock gclk_i to Pad |
57,37 → 57,37
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | |
------------+-----------------+------------+-----------------+------------+------------------+--------+ |
dbg_o<4> | 10.189(R)| SLOW | 4.245(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<5> | 10.661(R)| SLOW | 4.525(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<7> | 10.584(R)| SLOW | 4.515(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<8> | 10.546(R)| SLOW | 4.517(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<9> | 10.444(R)| SLOW | 4.424(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<10> | 11.747(R)| SLOW | 5.263(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<11> | 10.850(R)| SLOW | 4.663(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<0> | 9.978(R)| SLOW | 4.140(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<1> | 9.999(R)| SLOW | 4.146(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<2> | 9.969(R)| SLOW | 4.128(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<3> | 9.554(R)| SLOW | 3.890(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<4> | 10.087(R)| SLOW | 4.246(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<5> | 16.607(R)| SLOW | 8.007(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<6> | 11.948(R)| SLOW | 5.282(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<7> | 11.126(R)| SLOW | 4.792(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<0> | 9.589(R)| SLOW | 3.927(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<1> | 9.834(R)| SLOW | 4.096(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<2> | 9.806(R)| SLOW | 4.063(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<3> | 9.369(R)| SLOW | 3.801(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<4> | 9.464(R)| SLOW | 3.837(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<5> | 9.704(R)| SLOW | 4.008(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<6> | 9.672(R)| SLOW | 3.966(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<7> | 9.539(R)| SLOW | 3.912(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<0>| 11.606(R)| SLOW | 5.188(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<1>| 11.499(R)| SLOW | 5.055(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<2>| 11.467(R)| SLOW | 5.046(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<3>| 11.607(R)| SLOW | 5.144(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_miso_o | 13.517(R)| SLOW | 5.528(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_mosi_o | 13.405(R)| SLOW | 5.552(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_sck_o | 11.665(R)| SLOW | 5.240(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_ssel_o | 12.854(R)| SLOW | 5.876(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<4> | 9.886(R)| SLOW | 4.102(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<5> | 9.856(R)| SLOW | 4.079(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<7> | 10.279(R)| SLOW | 4.343(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<8> | 10.485(R)| SLOW | 4.438(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<9> | 10.661(R)| SLOW | 4.583(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<10> | 10.595(R)| SLOW | 4.516(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<11> | 10.797(R)| SLOW | 4.632(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<0> | 10.127(R)| SLOW | 4.227(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<1> | 9.955(R)| SLOW | 4.135(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<2> | 10.096(R)| SLOW | 4.211(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<3> | 9.531(R)| SLOW | 3.887(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<4> | 10.129(R)| SLOW | 4.244(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<5> | 16.930(R)| SLOW | 8.194(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<6> | 12.027(R)| SLOW | 5.407(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<7> | 11.196(R)| SLOW | 4.818(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<0> | 9.636(R)| SLOW | 3.930(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<1> | 9.683(R)| SLOW | 3.987(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<2> | 9.651(R)| SLOW | 3.945(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<3> | 9.718(R)| SLOW | 4.091(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<4> | 9.623(R)| SLOW | 4.055(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<5> | 9.875(R)| SLOW | 4.135(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<6> | 9.742(R)| SLOW | 4.088(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<7> | 9.568(R)| SLOW | 4.000(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<0>| 11.544(R)| SLOW | 5.167(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<1>| 11.702(R)| SLOW | 5.283(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<2>| 11.667(R)| SLOW | 5.272(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<3>| 11.707(R)| SLOW | 5.314(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_miso_o | 11.814(R)| SLOW | 5.115(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_mosi_o | 13.768(R)| SLOW | 5.317(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_sck_o | 11.645(R)| SLOW | 5.148(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_ssel_o | 12.580(R)| SLOW | 5.649(R)| FAST |gclk_i_BUFGP | 0.000| |
------------+-----------------+------------+-----------------+------------+------------------+--------+ |
|
Clock to Setup on destination clock gclk_i |
95,11 → 95,11
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
---------------+---------+---------+---------+---------+ |
gclk_i | 5.299| | | | |
gclk_i | 4.888| | | | |
---------------+---------+---------+---------+---------+ |
|
|
Analysis completed Wed Aug 10 22:57:08 2011 |
Analysis completed Mon Aug 29 00:08:54 2011 |
-------------------------------------------------------------------------------- |
|
Trace Settings: |
106,7 → 106,7
------------------------- |
Trace Settings |
|
Peak Memory Usage: 180 MB |
Peak Memory Usage: 177 MB |
|
|
|
/syn/spi_master_atlys_top.syr
3,14 → 3,14
--> Parameter TMPDIR set to xst/projnav.tmp |
|
|
Total REAL time to Xst completion: 1.00 secs |
Total CPU time to Xst completion: 0.09 secs |
Total REAL time to Xst completion: 0.00 secs |
Total CPU time to Xst completion: 0.08 secs |
|
--> Parameter xsthdpdir set to xst |
|
|
Total REAL time to Xst completion: 1.00 secs |
Total CPU time to Xst completion: 0.09 secs |
Total REAL time to Xst completion: 0.00 secs |
Total CPU time to Xst completion: 0.08 secs |
|
--> Reading design: spi_master_atlys_top.prj |
|
104,31 → 104,31
========================================================================= |
* HDL Parsing * |
========================================================================= |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work |
Parsing entity <spi_slave>. |
Parsing architecture <rtl> of entity <spi_slave>. |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 347: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 355: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 364: Case choice must be a locally static expression |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" into library work |
Parsing entity <spi_master>. |
Parsing architecture <rtl> of entity <spi_master>. |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 503: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 511: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 519: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 528: Case choice must be a locally static expression |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work |
Parsing entity <grp_debouncer>. |
Parsing architecture <rtl> of entity <grp_debouncer>. |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work |
Parsing entity <spi_master_atlys_top>. |
Parsing architecture <behavioral> of entity <spi_master_atlys_top>. |
Parsing architecture <rtl> of entity <spi_master_atlys_top>. |
|
========================================================================= |
* HDL Elaboration * |
========================================================================= |
|
Elaborating entity <spi_master_atlys_top> (architecture <behavioral>) from library <work>. |
Elaborating entity <spi_master_atlys_top> (architecture <rtl>) with generics from library <work>. |
|
Elaborating entity <spi_master> (architecture <rtl>) with generics from library <work>. |
|
137,10 → 137,9
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>. |
|
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>. |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 456. Case statement is complete. others clause is never selected |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 517. Case statement is complete. others clause is never selected |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 567. Case statement is complete. others clause is never selected |
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 174: Net <dbg[3]> does not have a driver. |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 459. Case statement is complete. others clause is never selected |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 521. Case statement is complete. others clause is never selected |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 571. Case statement is complete. others clause is never selected |
|
========================================================================= |
* HDL Synthesis * |
147,24 → 146,27
========================================================================= |
|
Synthesizing Unit <spi_master_atlys_top>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd". |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sh_reg_dbg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sck_ena_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sck_ena_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <do_transfer_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <wren_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <rx_bit_reg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_n_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_n_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <sh_reg_dbg_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <do_transfer_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <wren_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <rx_bit_next_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 221: Output port <strb_o> of the instance <Inst_sw_debouncer> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 230: Output port <strb_o> of the instance <Inst_btn_debouncer> is unconnected or connected to loadless signal. |
WARNING:Xst:2935 - Signal 'dbg<3:0>', unconnected in block 'spi_master_atlys_top', is tied to its initial value (0000). |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd". |
N = 8 |
CPOL = '0' |
CPHA = '0' |
PREFETCH = 3 |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <sh_reg_dbg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <sck_ena_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <sck_ena_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <do_transfer_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <wren_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <rx_bit_reg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_n_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_n_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <sh_reg_dbg_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <do_transfer_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <wren_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <rx_bit_next_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 224: Output port <strb_o> of the instance <Inst_sw_debouncer> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 233: Output port <strb_o> of the instance <Inst_btn_debouncer> is unconnected or connected to loadless signal. |
Found 1-bit register for signal <samp_ce_gen_proc.clk_cnt>. |
Found 1-bit register for signal <fsm_ce>. |
Found 1-bit register for signal <fsm_ce_gen_proc.clk_cnt>. |
228,10 → 230,10
| Encoding | Gray | |
| Implementation | LUT | |
----------------------------------------------------------------------- |
Found 1-bit adder for signal <samp_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_1_OUT<0>> created at line 273. |
Found 1-bit adder for signal <fsm_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_3_OUT<0>> created at line 287. |
Found 8-bit comparator equal for signal <_n0380> created at line 359 |
Found 6-bit comparator equal for signal <_n0400> created at line 362 |
Found 1-bit adder for signal <samp_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_1_OUT<0>> created at line 276. |
Found 1-bit adder for signal <fsm_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_3_OUT<0>> created at line 290. |
Found 8-bit comparator equal for signal <_n0380> created at line 362 |
Found 6-bit comparator equal for signal <_n0400> created at line 365 |
Summary: |
inferred 2 Adder/Subtractor(s). |
inferred 71 D-type flip-flop(s). |
241,7 → 243,7
Unit <spi_master_atlys_top> synthesized. |
|
Synthesizing Unit <spi_master>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd". |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master.vhd". |
N = 8 |
CPOL = '0' |
CPHA = '0' |
275,12 → 277,12
Found 1-bit register for signal <sck_ena_reg>. |
Found 1-bit register for signal <spi_clk_reg>. |
Found 1-bit register for signal <spi_2x_ce>. |
Found 1-bit adder for signal <spi_2x_ce_gen_proc.clk_cnt[0]_PWR_7_o_add_1_OUT<0>> created at line 328. |
Found 4-bit subtractor for signal <GND_7_o_GND_7_o_sub_12_OUT<3:0>> created at line 526. |
Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_20_o> created at line 519 |
Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_21_o> created at line 519 |
Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_22_o> created at line 528 |
Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_23_o> created at line 528 |
Found 1-bit adder for signal <spi_2x_ce_gen_proc.clk_cnt[0]_PWR_7_o_add_1_OUT<0>> created at line 330. |
Found 4-bit subtractor for signal <GND_7_o_GND_7_o_sub_12_OUT<3:0>> created at line 528. |
Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_20_o> created at line 521 |
Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_21_o> created at line 521 |
Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_22_o> created at line 530 |
Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_23_o> created at line 530 |
Summary: |
inferred 2 Adder/Subtractor(s). |
inferred 52 D-type flip-flop(s). |
289,11 → 291,12
Unit <spi_master> synthesized. |
|
Synthesizing Unit <spi_slave>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd". |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_slave.vhd". |
N = 8 |
CPOL = '0' |
CPHA = '0' |
PREFETCH = 3 |
Found 1-bit register for signal <preload_miso>. |
Found 4-bit register for signal <state_reg>. |
Found 1-bit register for signal <do_valid_B>. |
Found 1-bit register for signal <do_valid_C>. |
313,49 → 316,49
Found 1-bit register for signal <wr_ack_reg>. |
Found 1-bit register for signal <tx_bit_reg>. |
Found 1-bit register for signal <do_valid_A>. |
Found 4-bit subtractor for signal <GND_8_o_GND_8_o_sub_6_OUT<3:0>> created at line 362. |
Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_9_o> created at line 355 |
Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_10_o> created at line 355 |
Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_11_o> created at line 364 |
Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_12_o> created at line 364 |
Found 4-bit subtractor for signal <GND_8_o_GND_8_o_sub_6_OUT<3:0>> created at line 376. |
Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_9_o> created at line 369 |
Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_10_o> created at line 369 |
Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_11_o> created at line 378 |
Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_12_o> created at line 378 |
Summary: |
inferred 1 Adder/Subtractor(s). |
inferred 43 D-type flip-flop(s). |
inferred 44 D-type flip-flop(s). |
inferred 4 Comparator(s). |
inferred 22 Multiplexer(s). |
Unit <spi_slave> synthesized. |
|
Synthesizing Unit <grp_debouncer_1>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd". |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd". |
N = 8 |
CNT_VAL = 200 |
CNT_VAL = 20000 |
Found 8-bit register for signal <reg_A>. |
Found 8-bit register for signal <reg_B>. |
Found 8-bit register for signal <reg_out>. |
Found 8-bit register for signal <cnt_reg>. |
Found 9-bit adder for signal <n0024> created at line 162. |
Found 15-bit register for signal <cnt_reg>. |
Found 16-bit adder for signal <n0024> created at line 162. |
Found 8-bit comparator not equal for signal <n0008> created at line 184 |
Found 8-bit comparator not equal for signal <n0010> created at line 190 |
Summary: |
inferred 1 Adder/Subtractor(s). |
inferred 32 D-type flip-flop(s). |
inferred 39 D-type flip-flop(s). |
inferred 2 Comparator(s). |
Unit <grp_debouncer_1> synthesized. |
|
Synthesizing Unit <grp_debouncer_2>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd". |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd". |
N = 6 |
CNT_VAL = 200 |
CNT_VAL = 20000 |
Found 6-bit register for signal <reg_A>. |
Found 6-bit register for signal <reg_B>. |
Found 6-bit register for signal <reg_out>. |
Found 8-bit register for signal <cnt_reg>. |
Found 9-bit adder for signal <n0024> created at line 162. |
Found 15-bit register for signal <cnt_reg>. |
Found 16-bit adder for signal <n0024> created at line 162. |
Found 6-bit comparator not equal for signal <n0008> created at line 184 |
Found 6-bit comparator not equal for signal <n0010> created at line 190 |
Summary: |
inferred 1 Adder/Subtractor(s). |
inferred 26 D-type flip-flop(s). |
inferred 33 D-type flip-flop(s). |
inferred 2 Comparator(s). |
Unit <grp_debouncer_2> synthesized. |
|
365,13 → 368,14
Macro Statistics |
# Adders/Subtractors : 7 |
1-bit adder : 3 |
16-bit adder : 2 |
4-bit subtractor : 2 |
9-bit adder : 2 |
# Registers : 72 |
1-bit register : 48 |
# Registers : 73 |
1-bit register : 49 |
15-bit register : 2 |
4-bit register : 2 |
6-bit register : 4 |
8-bit register : 18 |
8-bit register : 16 |
# Comparators : 14 |
4-bit comparator greater : 8 |
6-bit comparator equal : 1 |
422,9 → 426,9
4-bit subtractor : 2 |
# Counters : 5 |
1-bit up counter : 3 |
8-bit up counter : 2 |
# Registers : 205 |
Flip-Flops : 205 |
15-bit up counter : 2 |
# Registers : 206 |
Flip-Flops : 206 |
# Comparators : 14 |
4-bit comparator greater : 8 |
6-bit comparator equal : 1 |
431,8 → 435,8
6-bit comparator not equal : 2 |
8-bit comparator equal : 1 |
8-bit comparator not equal : 2 |
# Multiplexers : 46 |
1-bit 2-to-1 multiplexer : 20 |
# Multiplexers : 47 |
1-bit 2-to-1 multiplexer : 21 |
4-bit 2-to-1 multiplexer : 12 |
8-bit 2-to-1 multiplexer : 14 |
# FSMs : 3 |
494,9 → 498,8
You should achieve better results by setting this init to 1. |
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top. |
You should achieve better results by setting this init to 1. |
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_7 hinder the constant cleaning in the block spi_master_atlys_top. |
You should achieve better results by setting this init to 1. |
INFO:Xst:2261 - The FF/Latch <spi_di_reg_s_0> in Unit <spi_master_atlys_top> is equivalent to the following 3 FFs/Latches, which will be removed : <spi_di_reg_s_4> <spi_di_reg_s_6> <spi_di_reg_s_7> |
INFO:Xst:2261 - The FF/Latch <spi_di_reg_s_0> in Unit <spi_master_atlys_top> is equivalent to the following 2 FFs/Latches, which will be removed : <spi_di_reg_s_4> <spi_di_reg_s_6> |
INFO:Xst:2261 - The FF/Latch <spi_di_reg_s_1> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <spi_di_reg_s_7> |
|
Optimizing unit <spi_master_atlys_top> ... |
|
513,7 → 516,8
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <fsm_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/di_reg_7> in Unit <spi_master_atlys_top> is equivalent to the following 3 FFs/Latches, which will be removed : <Inst_spi_slave_port/di_reg_6> <Inst_spi_slave_port/di_reg_4> <Inst_spi_slave_port/di_reg_0> |
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/di_reg_6> in Unit <spi_master_atlys_top> is equivalent to the following 2 FFs/Latches, which will be removed : <Inst_spi_slave_port/di_reg_4> <Inst_spi_slave_port/di_reg_0> |
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/di_reg_7> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <Inst_spi_slave_port/di_reg_1> |
INFO:Xst:2261 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <Inst_spi_master_port/core_ce> |
INFO:Xst:3203 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is the opposite to the following 2 FFs/Latches, which will be removed : <Inst_spi_master_port/core_n_clk> <Inst_spi_master_port/core_n_ce> |
|
530,8 → 534,8
Final Register Report |
|
Macro Statistics |
# Registers : 217 |
Flip-Flops : 217 |
# Registers : 232 |
Flip-Flops : 232 |
|
========================================================================= |
|
554,24 → 558,25
|
Primitive and Black Box Usage: |
------------------------------ |
# BELS : 205 |
# BELS : 259 |
# GND : 1 |
# INV : 4 |
# LUT1 : 14 |
# LUT2 : 4 |
# LUT3 : 28 |
# LUT1 : 28 |
# LUT2 : 3 |
# LUT3 : 26 |
# LUT4 : 17 |
# LUT5 : 55 |
# LUT6 : 47 |
# MUXCY : 14 |
# LUT5 : 62 |
# LUT6 : 55 |
# MUXCY : 28 |
# MUXF7 : 4 |
# VCC : 1 |
# XORCY : 16 |
# FlipFlops/Latches : 217 |
# FD : 83 |
# XORCY : 30 |
# FlipFlops/Latches : 232 |
# FD : 97 |
# FD_1 : 1 |
# FDC : 8 |
# FDE : 111 |
# FDP_1 : 1 |
# FDR : 10 |
# FDRE : 4 |
# Clock Buffers : 2 |
588,15 → 593,15
|
|
Slice Logic Utilization: |
Number of Slice Registers: 217 out of 54576 0% |
Number of Slice LUTs: 169 out of 27288 0% |
Number used as Logic: 169 out of 27288 0% |
Number of Slice Registers: 232 out of 54576 0% |
Number of Slice LUTs: 195 out of 27288 0% |
Number used as Logic: 195 out of 27288 0% |
|
Slice Logic Distribution: |
Number of LUT Flip Flop pairs used: 274 |
Number with an unused Flip Flop: 57 out of 274 20% |
Number with an unused LUT: 105 out of 274 38% |
Number of fully used LUT-FF pairs: 112 out of 274 40% |
Number of LUT Flip Flop pairs used: 301 |
Number with an unused Flip Flop: 69 out of 301 22% |
Number with an unused LUT: 106 out of 301 35% |
Number of fully used LUT-FF pairs: 126 out of 301 41% |
Number of unique control sets: 23 |
|
IO Utilization: |
627,8 → 632,8
-----------------------------------+------------------------+-------+ |
Clock Signal | Clock buffer(FF name) | Load | |
-----------------------------------+------------------------+-------+ |
gclk_i | BUFGP | 189 | |
Inst_spi_master_port/spi_clk_reg | BUFG | 28 | |
gclk_i | BUFGP | 203 | |
Inst_spi_master_port/spi_clk_reg | BUFG | 29 | |
-----------------------------------+------------------------+-------+ |
|
Asynchronous Control Signals Information: |
639,9 → 644,9
--------------- |
Speed Grade: -2 |
|
Minimum period: 5.283ns (Maximum Frequency: 189.286MHz) |
Minimum period: 5.267ns (Maximum Frequency: 189.861MHz) |
Minimum input arrival time before clock: 2.083ns |
Maximum output required time after clock: 7.830ns |
Maximum output required time after clock: 7.216ns |
Maximum combinational path delay: No path found |
|
Timing Details: |
650,28 → 655,28
|
========================================================================= |
Timing constraint: Default period analysis for Clock 'gclk_i' |
Clock period: 5.283ns (frequency: 189.286MHz) |
Total number of paths / destination ports: 1727 / 266 |
Clock period: 5.267ns (frequency: 189.861MHz) |
Total number of paths / destination ports: 2605 / 280 |
------------------------------------------------------------------------- |
Delay: 5.283ns (Levels of Logic = 4) |
Delay: 5.267ns (Levels of Logic = 4) |
Source: sw_reg_5 (FF) |
Destination: btn_reg_0 (FF) |
Destination: m_wr_st_reg_FSM_FFd4 (FF) |
Source Clock: gclk_i rising |
Destination Clock: gclk_i rising |
|
Data Path: sw_reg_5 to btn_reg_0 |
Data Path: sw_reg_5 to m_wr_st_reg_FSM_FFd4 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDE:C->Q 3 0.525 1.196 sw_reg_5 (sw_reg_5) |
LUT6:I1->O 2 0.254 0.834 _n038082 (_n038081) |
LUT6:I4->O 3 0.250 0.766 _n038083 (_n0380) |
LUT5:I4->O 6 0.254 0.876 _n0418_inv1_rstpot (_n0418_inv1_rstpot) |
LUT3:I2->O 1 0.254 0.000 btn_reg_0_dpot (btn_reg_0_dpot) |
FDE:D 0.074 btn_reg_0 |
LUT6:I4->O 8 0.250 0.944 _n038083 (_n0380) |
LUT5:I4->O 1 0.254 0.682 m_wr_st_reg_FSM_FFd2-In1 (m_wr_st_reg_FSM_FFd2-In1) |
LUT6:I5->O 1 0.254 0.000 m_wr_st_reg_FSM_FFd2-In2 (m_wr_st_reg_FSM_FFd2-In) |
FDR:D 0.074 m_wr_st_reg_FSM_FFd2 |
---------------------------------------- |
Total 5.283ns (1.611ns logic, 3.672ns route) |
(30.5% logic, 69.5% route) |
Total 5.267ns (1.611ns logic, 3.656ns route) |
(30.6% logic, 69.4% route) |
|
========================================================================= |
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg' |
689,7 → 694,7
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDC:C->Q 2 0.525 1.156 Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1) |
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N14) |
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N10) |
MUXF7:I0->O 1 0.163 0.000 Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next) |
FD_1:D 0.074 Inst_spi_slave_port/tx_bit_reg |
---------------------------------------- |
717,47 → 722,44
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i' |
Total number of paths / destination ports: 41 / 31 |
Total number of paths / destination ports: 37 / 31 |
------------------------------------------------------------------------- |
Offset: 7.663ns (Levels of Logic = 4) |
Source: Inst_spi_master_port/ssel_ena_reg (FF) |
Destination: spi_miso_o (PAD) |
Offset: 7.216ns (Levels of Logic = 3) |
Source: Inst_spi_master_port/state_reg_2 (FF) |
Destination: spi_mosi_o (PAD) |
Source Clock: gclk_i rising |
|
Data Path: Inst_spi_master_port/ssel_ena_reg to spi_miso_o |
Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDE:C->Q 5 0.525 1.271 Inst_spi_master_port/ssel_ena_reg (Inst_spi_master_port/ssel_ena_reg) |
LUT5:I0->O 1 0.254 0.682 Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1) |
LUT6:I5->O 2 0.254 0.834 Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2) |
LUT3:I1->O 1 0.250 0.681 Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF) |
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o) |
FDRE:C->Q 20 0.525 1.394 Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2) |
LUT2:I0->O 2 0.250 1.156 Inst_spi_master_port/spi_mosi_o_SW0 (N0) |
LUT6:I1->O 2 0.254 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF) |
OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o) |
---------------------------------------- |
Total 7.663ns (4.195ns logic, 3.468ns route) |
(54.7% logic, 45.3% route) |
Total 7.216ns (3.941ns logic, 3.275ns route) |
(54.6% logic, 45.4% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg' |
Total number of paths / destination ports: 25 / 14 |
Total number of paths / destination ports: 19 / 18 |
------------------------------------------------------------------------- |
Offset: 7.830ns (Levels of Logic = 4) |
Source: Inst_spi_slave_port/state_reg_0 (FF) |
Offset: 5.307ns (Levels of Logic = 2) |
Source: Inst_spi_slave_port/preload_miso (FF) |
Destination: spi_miso_o (PAD) |
Source Clock: Inst_spi_master_port/spi_clk_reg rising |
Source Clock: Inst_spi_master_port/spi_clk_reg falling |
|
Data Path: Inst_spi_slave_port/state_reg_0 to spi_miso_o |
Data Path: Inst_spi_slave_port/preload_miso to spi_miso_o |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDC:C->Q 22 0.525 1.442 Inst_spi_slave_port/state_reg_0 (Inst_spi_slave_port/state_reg_0) |
LUT5:I3->O 1 0.250 0.682 Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1) |
LUT6:I5->O 2 0.254 0.834 Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2) |
LUT3:I1->O 1 0.250 0.681 Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF) |
FDP_1:C->Q 2 0.525 0.954 Inst_spi_slave_port/preload_miso (Inst_spi_slave_port/preload_miso) |
LUT3:I0->O 1 0.235 0.681 Inst_spi_slave_port/Mmux_spi_miso_o11 (spi_miso_o_OBUF) |
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o) |
---------------------------------------- |
Total 7.830ns (4.191ns logic, 3.639ns route) |
(53.5% logic, 46.5% route) |
Total 5.307ns (3.672ns logic, 1.635ns route) |
(69.2% logic, 30.8% route) |
|
========================================================================= |
|
769,8 → 771,8
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
--------------------------------+---------+---------+---------+---------+ |
Inst_spi_master_port/spi_clk_reg| 3.706| | 2.262| | |
gclk_i | 4.633| | 2.169| | |
Inst_spi_master_port/spi_clk_reg| 3.682| | 2.224| | |
gclk_i | 4.633| | 3.198| | |
--------------------------------+---------+---------+---------+---------+ |
|
Clock to Setup on destination clock gclk_i |
778,21 → 780,21
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
--------------------------------+---------+---------+---------+---------+ |
Inst_spi_master_port/spi_clk_reg| 4.416| 3.782| | | |
gclk_i | 5.283| | | | |
Inst_spi_master_port/spi_clk_reg| 2.078| 1.855| | | |
gclk_i | 5.267| | | | |
--------------------------------+---------+---------+---------+---------+ |
|
========================================================================= |
|
|
Total REAL time to Xst completion: 8.00 secs |
Total CPU time to Xst completion: 7.33 secs |
Total REAL time to Xst completion: 6.00 secs |
Total CPU time to Xst completion: 6.29 secs |
|
--> |
|
Total memory usage is 178696 kilobytes |
Total memory usage is 188108 kilobytes |
|
Number of errors : 0 ( 0 filtered) |
Number of warnings : 29 ( 0 filtered) |
Number of infos : 22 ( 0 filtered) |
Number of warnings : 26 ( 0 filtered) |
Number of infos : 24 ( 0 filtered) |
|
/syn/spi_master_atlys_top_guide.ncd
1,3 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6 |
###3956:XlxV32DM 3fe8 f5ceNqdWm1v4jgX/SvRaj8ubfyapFlVIpB20FDoAp2n/RTREDpoKbBAZzra/fHPdYghJontVmrA957jY99rJ7ZDf+c+/xe54e+j7Mdit1ivrhx0QZ3fcdjCKA1b2T9vix/TZbbaJ9vsZbHbZ1sovK7B9xy2Xpbr5+kyWW/2QdharPa7/a9lhjA5Gc5ilzmtjfOe8t3ynbJWunshmLaw0/rptJbrl0Uqqjvr+dxprZfO98XLd6f1njkrp7V3EBT3juu0jm3P3jbLRTrdQ08PdbYOdUr9cKbbbOrouu1Azdbr3oEezLL9dLF0WovtQWtTfC/TQmaz/pkVvrWz2yyS12kuNd0vf+2S/XoDjs3FKp3VgherlwZgk84dkaQtfCzTaXhKBDhexcd6ycND82BstoiFtTmAYdp7gEEu1YyfpRLipZ8JINUH8J7Nwsvo4eb27uExecRPRDUpCy/v213kHb5cUhQwlQUmC7woEMkhksM8WfBlISgK3JUF2QTHsiB1uNThUodLHV/W8mUtX9byZS1f9tCXPfSljn/Ukf0JZH8CWSuQtQJZKyhqYRfJApYFIgtUFpgscFnwZOGoU7SOkSsLUhlJZSSVkVRGUhlJZSR1sCwQKcikIJOCTFZnsrocFCzHAnPMD4WipzC0slBwCXUPFEqKbwoTaNzvdeLkEflP2FVMoqIUnUzsKqgwmWrykolUMlLJREX5EyaKSWhaNoMS6D0hXzVVtByQMHFaNstcX1VSc4HVXAizHECg1g3UumBixSRINc9QqpqlhoirNARmWRlMcmaqdWkprQQpnQRTqYue6JlZrouVNBPyhJhqllF6btJyCEyty9RecTVerkrxczJVUVZGYWp4qumrZqCYWK2r5NlTG/LUhtSJJMxAMbFKxkg1sWpS1eSKqQyZOuuEiVTzjExVkysmUeueNcRUlJdQ6irtUnWKUnWKUnUSUqz0Spi+apYySYlKJioKTw1XMamKMhUtR0TVAaW+KuUryaGQHPf0UPEhGSh0UYhIiC5c2EUgfDV8mNw/TK5mzy/J+k+ErtxrEpILJD6ATOHxTSXnNdntp/sMeARoZWSnIM8h+8P9A9aUP2jATwZzXWkEZSQQCMIhv+oNhNjzfpUs/mSiCRT6hXP3E3ye8BHwFc0usxk0mXvpyfuazNY17t3J/RwGecskbzls03nYdtLpdvvLSb9PFysHotnuF6sX5+di/71AXt/end96q90+ER2cZc/rt1WabS/vUijsk/SwuUzSX3+617/R7EOKEJ1BEIdtSFEbw0XgonAxuDhcPRq2YYsFpb/gekRhhMMIyBGQIyBHQI6AHAE56rEw6g87X73D1+MT7Paju9tR0p5MRr3oYRKPQwoeoRf9FYRi/5Zv4gTvodfvJpP26DaGj84XHzzjpDe4GQL3MQ2jbLlz3AsCG/VhlltXomYiPp4Pdqc9Gj3R6cG4uUnGo6L8pT3qwkTOy71hlPSgB1nJHIDI/GTDmIIjODj6DxN2KnLR06KcDEfJXXzH/YMH9hRFP0bxLbRdNDCO+yLeBKZbB4cdSF0HUteB1HUgdR1IXUeIdtrd5Fsv/l/yLR6Ne8MBC/NoAI3h6hG4BlD4Kup9/a/fnnS+iPZvbiDQq/GoN+hNii/3avw06OQpv2qL4n//Qe3+Vxp2oCNQHJIAPu7uepNJ3J1CcTyBvEf9GBgQOjTwlxd2RnEbYDAeedh5EsKzsLN+3RwHYXow81EIijJkLy2K+WOhr1h3igVzCeRhPw5fcEFgXUhIFxLShbnUhZC7PVd8IPGBxQehYTefPF2YjF2YFPHNzXA0SfrxN9FU/DgZtZODbxbe9odRu5/0h7e9jgv3qmInm2n6N4wJq3W7Df4mPm7wkwY/bfCz+m7iejepd9N6d4M2r3d79W6/3h2o2UYwnxX7AjKKKq46H6rx4RofqTZR0yquumoq0qqLzc88+NxBzh303MEqsiw45/AKh7tVVzUyXo2MVyPj1ch4tVe8phNe1eVXXZVwqtW8ajheNRyvGo5XDcerhuNVw/Gq4Xg1/aqG41XCqXL8ajh+NRy/Go5fDcevhuNXw/Gr4fjVcPyarlbCCSqcoBpOUA0nqIYTVMMJquEE1XCCajhBNZygGk4QoLCHw54L18APYaG5FKt4cCiJBXyaFw9rt5eXxSkfSuN4ItbpKB4l+bYkiXqDbm9we1n3uumyB6vhl148EnuQp6Tdvx12hoNxgjENBXTcyST3YqEeT+LBJLkfDe+TMQADsZMRtKKJZPJ0HyM/bBKFxU+Fcj7Pnb3BJB4NIAP3/WTUHtzGsIMR/sGwGx94h8qj+CYexQPYg4v9AyyWNdtI7IWWm0tbJrJmYmsmsWZSayazZvJr7Fswl297kabMmgoD+S1xrbTf11uhbUtF9lRsTyX2VGpPZfZUbk/1rvGzNTXZ7q2G7ciGP5TWVRhlu7elGFstjPQw1sNED1M9zPQw18PeNZzza+AiQyJwLQ4T09XjIrVaCWyQwGYJYpAgZglqkKBmCWaQYGYJbpDg140zVc5pVw8jPYz1MNHDVA8zPcz1sIdqHwACaotnKdah8nilkUBaCXQtT4YaCayVwNfyNKeRIFoJci1PfhoJeGBoUHheTBtRmD0aEOlArAOJDqQ6kDXHEmlHPTqOulYCaSXkqHOdBNZKyFH3dBJEKyFH3ddJ6EY90o56pBv1SDfqkW7UI92oR7pRjxJW/5gU4DrfaulxZMBhxKgelze7VoYYZMjxsaOVoQYZKntjRyN2NEOKmaFTzK5TkobtaNSO1rBSFLSmJVDCSA9jPUz0MNXDDLEDXDqRbtbb/SXm9f673XdRd7aANfCfZJ10TcR18mO6XMySrhzfc2K63mZJuvxbproJl7dAVk/Le5RvEPUEZCJgE4GYCNREYCYCNxFO++R6Asw5PY4MODbgxIBTA84MODfgHpprcDEz20ZGZGR0MTIwoC84MHPk6/0PcJGhd6LlhpsXbrrnt/k8/3cwcUvY8ZAlD1vyiCWPWvKYJY9b8rzrpkeOwktcOxqyo2E7GrGjUTsas6NxO5qnoe2309WuIMo3JAaaXP/njezDCtJuWmpODHnrmKQio1Qkt0omqS4mBkZ+UzfpbN+T50V+oGzq0okhdzhuPXEHYLaa5lqekWJYTnffDc+OI0EeJ/RCyCSEjocKvRA2CcnNcmAQal7GCwI1tUQtY2cmIWYZOzcJccvYm7cPB0Lz9qHAkQHHBpwYcGrAmQHnBtxrutuEjd+TNEvwRZv1HyZmIjkQCTMRX7JVstmu0wuxm01X+4tOXs//aD3YR1xEn62Kit5+oiq+6H62Kvl8rLSI1ftwVfzpmnJIP16TFjn6eE1WpOjjNfmn4wwObTauKGALqmarWaLk/xDVtGHe7bLlcXVq4uT/bFcsO76ZI9dDayqxpzJzJ5FFJ9HxfYM1lZhbxhYtY/v04OPbDmPLxKJlYh/z8f2xPZU3TlZJhQ27kYLMFGymkKZd3c9tIvqq2dWdGHIPETQRs1VTTwQm93GlLfluOf2RFa9xWK27+hZHz6t9iVPind6taHHv+ONfLX56E1YPK/usc/hw5DcQIhOhW051HUFs5bUaZ8/KWsLZq8pz3vnp3YaG7GjYjkbsaNSOxuxo3I4Gx3ZipsFDwIaFrFjYikWsWNSKxaxY3IrlNbOU0/rUhlVzbFTJxUncRIhMhK78BaqJoLsXYZe/yt7zH17mBoKy3NYzkhsLzm3DXX/iyAf9rImnvd3PztvUjsb0rSFDa+ha/6g6o3F9a/hajxNDb06/NmtlqEGG2uWGGWSYXdDcELRnaMY7/vaXamin35jqYUNtrIeJHqZ6mOlhroe9hhVZOSx4Roqcx7ZMbM0k1kxqDAWZQzmdKExi2CyGrfNy/GcRY7PE3CyxTjI5/o/KXM+EG2Ae/h9ATwxm###5648:XlxV32DM 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wXI5L6fXnwj9tLgc/g4/pvDjajEbTupPbLEcLIevr1P4PakH8/rT5ddqPF1QwZLi9XKwrD6r6Rx2+0/wZzHX/8QIfyWf9D9pVNr7p4GGr6/07vghdsRbQch+EMZhyNVSDxgPx5/mA/N3PK2HMOaSyNep/EfyM9n575WS4vXN/JOIjU/4dSr+8e7drwH5AD/oya+BeP/+5J0WjfxuQD8Y3YcBe//+/Stf7QzhH94NhAbsZEDBwg/eZYDgWhQnxtUBZ7/sGGrj7XjT6djR1plJGJ1BV7XOqDb+bcCNHQjvrFvjBuxPDANVfRgQPZSuDg/V+epxEIiYOKQTh32AysCOGUemZRylsyPOBbNz2KZNUH6FgzUYwcwoS7r5YnoOTuz4V5rtDsAFA+GdiUPfn6DvMBtTCFr4EeK3X2ZCqJnCTj/o6TJrT96bGT/BxaThbFAWDPllKuDtgguzjK+wqVsrvZjW5DebJGEtc9Iue0eL06eNd7XcatdeCfIrbUNBps7KVwvuP2Dq7UCzioEoOsts5t90BUwGD3M2Lfjh107OTiv2tNgHPpZpx1fi+s/1PraMjZYjib2Jbgy36VDGUcf25B028gnm5zmGC6kXyqzC5v8BrYHhQg==###4796:XlxV32DM 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upzevqZ1wh10r0/98u2JXISPdz1uMhdqWo2/pkRSg84etaTX0XgRzfbKEAhpf19LjAqEROW7RLoU2K6/N5HQRWpHzfbagUS2H67/4IsbqNOcLcHr8guPE44XKtQjpz7itjvuPKnd+ti4zV6lVc19UtrTt+fhiod6lLULa7v+zsX+DyoD3VI=###6556:XlxV32DM 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12d0eNq1W0mSM6kOvkwfIJkTO/oqFQEJRPSma1HLP+ruj0lDpp22q/x6UWUssJiE9EmC5fKXSvaiwnq9fqpNXZbL9ftLx1wL8s/fpqyXSr3+Lb29CGFrnVxbI9Xq3GXL1/pp2+dHWfsvQ601f+oPzEUsy/zlKDgorL3w0f5Vhm4jhmkZDOvnRwm9u8i6K7O7Umt9ry1joI2nXkzjuTW6Z4NMYvIU9Vex1prF80HC9EbBQWHthcpwzNpBRw46cr2jAitVO5C1g979ukBrO1pn3RcnEZO2mn14apNtTPX3yGgu+YpL7udslGid9G1pnaXU1y/BL/0l1RHXv8bPE3XyM8DPBRiHGcNLnewX1s0yu6kbkdqiyQVmmnPfbyHaAuhtTrX9qE3lI6s+ZMF4icmrbkAa68OG3Daz/rX+NzaRNj3ZB+sYtXEQnYNh1DbGIUor9TqEZe38Uxcl5WmobQZpiFBm8yptXmsnWyK3wQjRV8GxVWijEaKz9oxJG44QjXf7huS2CR+wAZ417+S2LDauJJfazsMzCw4Kay98tH/fX8KsndNHynONVacO/h8lTdGv1O9otLiIS7ioS/zzr0rpYou4/qW27WLj9S9tdZUPc/3c2om7/rO1sXftoNV2rd8LfY/1e1rou2/fBX0P7buk72v73pXLZzKdez3787Ot8zVK077r+rf86UPSKl3rIPUlrm1s4iLrya41bdRpjDZvnI8an6Lz+6xi3XVZNKUVLGecB2MR/eBsoxyc3SIG57oubP4q2N38VTC7+augdvNXQe/mr4Ls2lXOEWlxmKpe5oicPY7ImDkiue/BH3pwtMKoxqVCNW66wNe/StVqnv665OP0m66cPJGncjKgnPqIGyMthhxvkYt3/wlp9KFfkc6UqAGtbIZS0IId6a7HoFbOWlQDpDIMUxlCEhXVgDBhHgo1uXTxb8dLXNaLvHgQfznFfyPx38l9PMj9+kTuy0HuA+wKnaPPZHeCb3SbmLsnDWk9SoNaSRq4fIaDfLqDfK4H+dwO0uN341QhMjQQh1pSfIRijlCJwwhtmZqkmPMz+aUdCGadfDdOfW+6bhy9zToUDgvS2arJZKGk9d+TpFmUi8YEZMhKRVSUISsCawsyZGVibeHs2MgGDrb2O0phumLVlwCSpaZkJaZY584n11cj6/4tr/f04WfFMfN7Ht/lXEuph77so9Z3NqVO6qgvPd+TJ/pSinhkHCfj/Cbj7cC46rbBOL3JOB0Zl8l4e4fxlw1T7bUemnR+1NXvWscQfYBBqXp7gH11qqP9knd4s27aQJd1kWdhg0LaqUqhiRUDtjYWzmoBVguwWoAVamMLELW3bKPKHeAIRWTCqBaQTO+gtU6OK9pGxvNXbVkoVfJFtQr1H8i+nrKfb0EFV47+nnIcpyF5JOtua8MgTyYb1cpWmwZ5nJTSj9c/ZcVGppnnjofrRyDy0siReOX2nfFuWrIk+l61ezRRHJUhqOv1xnhrxYy3PKjjM3Vrwo1BCNCDPvYg0hODMO3AXv07UP83mKFv6L53o6F3c9N7uN/7duidpvkahqFJEJgZC99Ub+QYRBTQ3nXg5IYmz6jgLYqyERU9TJ0So4KPKLpgdGpijssiGRU8MFEyozar0E99YNQ+4LT2xrw78Bh1Koxa25bU57wQtbMornNOtBTo8eksqD90esZ+QluwhDor1hZcIZ34nKfj10Sibn4VifoHJ9zME17YCZ/qs6pRR0csXRuBHUXbCX62ZIcx9Ao6jcZ1Ah1H49vxC/oonoDmXfyxeB7R0l484/Xxqd2LZ9Cwdpq7ejZ7opOrp7xlZHQvbXaMjO6l8oaR0b20mZHJdVWeDQU99e+oWkBhj1Ls2Ee3/EcoRfl0glLsVCZKiN/YfNXN1D2UYvWbjMsJSrHqPcZhOUEpVr7D+EutEzC3HhhKaduNdIZSFISy2lTvoZS2aR2TtEWehTILYefQKc9YMZRiUuGsFmC1AKsFWCFKURBv6S0RpeA5aWRCKQrCP70DRCl4ThqZoxRjjhrMTckXzzSYO2qwFTXYTnOFo46LO801Vdm1j+VEg6V8o8HifQ22HjSYvz62tO6gysKdaMEYWFMbxnANptxCdKbBMEBmDNNgyilGJg22akZGDaacIDLTYCsbCtNgsi77QYOtcx/Vf+Zn5TM/K77ptZQzPyu8x1guZ36Wf5OxOPOz1jf9LPCnpNj7WZ7oOz8LnCO5nPhZGbyqqbh6y1EQez9rJVb3/awMXtVUXIPVAqzIzwroUJWdn+WIzPysgA5V3vlZlshMg7Xmtbd82S5Sg+z7KfuaR6+OsHsEb7syOI/JzgPDvKzp8nTFwlwiC+4Wd84oYKb1FQ8cc8CGZ3XjgA0Ha/h0ZRzDkk5OqdufVq6h/VMNba+vg82mAiRXBdXlC4cIMrl8202ErjCN/cAFehq9rVtuTzSPjDdRt5+cYxO343zQwbyxQHp5OJ/t+hgzhwNm9rvAYnAnKlBub83QBn/UVLB0+Ybxj5IJPf5nOGM5l84vN8mEeD+ZoA/GWh5kgqcKesbQ3vXGy81WbQ+3yh27uSNx64nlkOnN/TjGFM3caLW8tx89+7jbjw32Q97sh7u/H+ZsP1jyh8u02iVzuqGw9+CcF0936AS+ueuLnuhu88KJdZblnc37shKyzzGPtHBMFD0xEWMREMoPGMqHeGgjceOK0YeYKDpD3mzMFMnB6GVTFiyVjrniqsxmtw66xUBIrcNwjFWKUSF0Y0ViVAjzWOkYFTLgVjAOGGDBgGnT15SZ0B7iUtV6zAHCFQrKQ9Q6jN9QHqJRKWeRGBXTIRgualTMWWDWo1JZfqOw/RNz/yDOZZVhtXLWQljKSrh9UQ/a2PvCAxDdUkK1mNUI+q3MrFrOagp2AGBq6mHCux6c8onoIxNZfz8ykdq3Abmx2h2F9X0fBQ+FFQoRCmGXn4y4ZX52EDOkOiOubIF9CyjPEn4XOB4duBMHBcI4Ch4KKxQiFMIuZYWBojpZul9BEaFYmIeEqYnWAbuPIkxkmf+Y4D7AOC3ddRu7MDKi2QxUuV6kBFQZJqo0JzlRf8iJlkNOdL0PNx+kQnm030O0nwNOBkgVANI9DpVPcOiEnxTIHzh0F/8f+YDtkDZgnfRg5pn/KNz8XI/I9FGoID2NeraLWYhE+67fzRW7m7sMyr4WO9iuj3HCSyniXE6wqnoPqnYMfDcX4tKrEz6Ge+NZcvxxNmIPXctyAl31mxN2Z+kXl59OeD/P8FpYezvMc93PU5xAQvPmPNfTOH757TxPgl/bkzj+YWPlWZj2PRSF1j0Idp8AkUAQzGKjzQ+CWXdKEbFbM2TzA8vvKC8YFTNEKxvDsG25IGgCrJYLgzFWYErIUqKI8FGwDAlJZO8YrFOS2jIslVlbBHuC8UWMpteNqGPYZZnDVp5zR6xHqTDLUF0G810WHonJFsiSW3WNFwPDCt1K7FZTHbvAJwwjs6wOJzN4VBiZgSrWmll8KRkZ8QHGvPpWLrA4oyCgIPdIQ8OEBYflul+1RVYLsFqA1QKsEElpvJUVHKyRwDVSVIcpTSs8oyLOzLztHpsCdXoc37GN8xDNjxOz2MfXGMuTa4zrk2uMd24sxLFq92yyXG40tomvmajwxCH019cvFFBqsg0VVQ9uT6ei6smMeqt6OhVUDyqZTgXVYwAkdyqpnkhUzN5/R2VaTrLqxvqRYTe3uZvucVwznl2+22/Seh9oqgPQ1NefRT6PiNMwxHl71USdXTW5uWFyB1nOzAUHkgmBJODHA2y0HDb2K9R3A5j5NoCZHkaRwplx3Qug4zZVWXd2gVCLx7nPM/jgTnFhvrkGoH6ZRHsW23x0XaXO+ebSZIQ5L7+cszmLBebww13czvTJwxn5w4wACgpVfjkjfRY7y/63M3pFHMNxIgUmkn8zkS9lINVu94EBBzDBjUshvcEwj8YkqiMIYYxlZIQQxjJOBCGM3RiZ0qp6ITJBCMrw2xmeaFI6Cx4Ku6iEguG0BjzD78A0OwMz8zAzK6mO7jKZwKhg+I11jIoPdGxkVAg1KlWIivhSGQ0jXBmqGxqiN7YwwBWX3lMd3ddCfO0Y+DSWtUWoq4yETh2/jowpdOeYRTQbo4JFVHg53zFkbfC1i3MwbIfrqhgftMIqERXtuLErawt23BjWJ+JiY9lS0bUvqfvVzur4VJ8MTHOapnk9mmaOmB4gquMF+fggKvQ8G3m8/Hliinm2MRyiQA9s8mmwJ5ru/d81qPHmiqZafhf0356k0nYBGNkl714AJqq3kv4ml7NkYVRPp/rY6rgXrI409iTQEuWbEztNrUXx6h4e31mEJ3Z1NzF3ElmB7n95m0JqULRVSkkhdN2v25scePNo4M2jcVzl6wjqO8+MTm8wVFB/8YNcFuCyABd61anh1rlxu5eZGIPILAshV9Ynvf30nIqPK9GDzInMi8SIRy7sbSRc7+hU0PQ6KqLOGeLzVo1vmvjTTakTdUrPT3UkRvTOUG/AYve8Eh+95MKeVa58hHjPmN50Lux5Iz16XPhTSN4W30thKKVR0Q2Lmqhz5vNVaMsg6nm7agN1n6e69ye5gPBDh3o7c6jhXSC9jto/D7QhnTwPVPLNDLI8ZJDxeaDXr2aQ9VsZ5E2cGROvXs0gh/9LBnk7C+KL92KfGSS0zplinxkOz7aLfcLL7dq2Zxw3HgPtLi/UilmLsVCZWK2ctZhJhVtmTZbYu0fK3ybINkpIBm6ChjiTgRsmAyGKFrZd3ndmTDu7kXzcbh9HYgPgSfpXTMdgvF7c4PWi6TfA8kVeME5S5ukMP4t6sYTP/wCoJ9N0###5060:XlxV32DM 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9o105J9ltXgjwD3eqBeGElurloeK/duw/wPa1sgi###5024:XlxV32DM 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18f4eNq1W8luLTmO/Zn8AI0x2Hi/YkBDCKhN5yKXRv57i+Q5iriu50I3XLmwpaAkTqIoitId+/vff+V6vLm38PlLKrGF9w/vBL4dfsKjwXt4n+Uu5cdo0rp3tPb81p20nlJ+eH/q4O3R7NHspbloc37g9sA9m0dV3O3R6tA6cQ8ZG1q6W9uw1ll+DCPsTJptH2/J5fePvk1wKh1C9m0KGd+13XtruzikKmh22lUTwsqjzdBlBVeKt5tuJlrRTddBR3gIHyC8KNabeOMx2GPwFH7+yeAEikc0ij4EFTs+RjmMmkqZfzLq0apKma2ilPknErYbJyTMkFB4w/SfqpkPaEUxJki+OdOYVYSzWfmQf3//5fegGD56BFdRodGgo2MCDWrSTSINepngv+uWw5t/K2/prXz+T+z9bQ/j/Y/Y2luN73+kLU228/ufXazq/V9Txln8eSX9ug4tvHMotdOf3jV8X/Ydon0HHTZJChapu0+llJJ/n7QnqSEk/dtWg/DQ37ZpWsrEyE86wOeN3pwrKUWW4yviaoiD+yHi8wvinIHY/xBx+Yp4AHH4CeK/Qs0wvElB7GoacxJzzeGGw8ij9qfxT1Gtv7vESJ1IngW+v01q0wanklE5WSlamUM2JeFvVEbCteXuFipHVI6oHFGJM3NOuYpEdRhX16EU3A1WClfS3ku23Xp3dadp3ODlmET31xfLjw6Wn/4py9/iN5Yf4s/saEvfWX76IeL8neXnHyLevrP87YeWT/ObFF4s/7rhL5ZPY5qi/tby56SZnYtJWCWzsr1afr9RvVj+CypHVI6oHFHdll9otGqHt+W3G/yw/LWRbvFp+bne4Kflx3+zfA/Lz/+U5afvLN//0PLTd5bvf2j56TvL9z+0/PSd5fv/luWnV8uP1w3/reWnbyw/0fITLT/R8tOr5cd+o3qx/P2JyhGVIypHVL+x/PRi+bHd4N9Zfnqx/Fhv8NPy079ZfoDlb/9YtPOt5dcfxg7fWn77IeJvLb//EPG3ln/9lyw/v1p+um74by0/f2P5mZafafmZlp9fLT/1G9Xvox1afqblZ1p+/sby84vlp3aDf2f5+cXyU73BD8vPwU/L9+VtBlIXbT/C9vfb9v/VhIk/4lwCKY73uQjc/X3It7+/m3yH+/uU73h/l/d7LZUFTtqtGrjd4E3A/f4O8n3d3/l9rcVx3uBrdhsP7F2+Dfu4seco4Ad24f3bteyPe6AIPc/WN2BXQEHPejd0bXjQFPnhD2rWY+T2XK4Oxn9+3VD2UGD94TkhsbSXCYllf5mQWOrLhMRyvExILFPzf0Zl5F1MYvvGM8Wf7cm55a+iFoq6/79F/c8S7l8kLK8S7t+4yJh+KOH2RcKcKOHxf5Xw/DKZa3W9Sti+SLi/Snh846tj/qGE+1cJL0p4/sMS1lcJz282jfizcEk8ouVfwvncHFLBoVNUoBkr6WC5mXWIkLauKZv23GcUvPJNweUH+M7BxWfvlbkLzt9gySBNL/Tck2S56g4kVo3Kwcr53JNycJTseO5JqbgnKkdUjqgcUa09KZVApjYq41jK6HebKGP054aoUGYtg0sP6Mo3xmfflWd07oau/GL2g0Ltj23Qj6XMeOfdVvwn0JWrCy48oCvvl559mUpM57ihEHxbgj9HTME1w5Y9OQnbIwHqx0KUlcFenuGsQJVBM5j4gAqD7RkAKFQY7M+joEKFiUvny99QsG3JkL/nkI584Sa5UfmKTSOM7gn3AvcL7giXaGV+Ad4G4JLwlC/CL8IvgV8L3gnvAu8L3ghvAm8LXgmvAq+AJ/KfhP+0+E/kPwn/afGfyH8S/tPiP5H/JPynxX8i/0n4T4v/RP6T8J8W/9lZAv9jVqai3UG4z4DPgOqXfBGeCE8CTwseCZcJ83HBA+GSy/ZhwT3hksT2fsEd4bKSvVt8DvIpCWo3Fvwi/BL4mi/mlWdFss/LTnbayS52si872Wknu2arl51stJNN7GRbdrLRTjaxk23R3Wgnm9jJtuxko51sYifbspONdrKJnWy0k82RTyd8usWnI58afbuln0H9DNHPWPoZ1M8Q/YxrwTvhkmIfyx5GI1xy7KMteCW8CrwueCG8CLwsPqkHJ3pwSw+OenCiB7f04KgHJ3pwtx4K4UXgC/9B+CHw44afhJ8CPxf8IPwQ+LHgO+G7wHeul8F1OmSdjrVOB9fpkHU61jqlfpLoJy39JOoniX7S0k8aJ+GnwM8FPwg/BH4s+E74LvCbz43wTeDbgmfCs8DzgifCk8DTgkfCo8DjgtP/DPE/Y62LynmsMo91zWPlvFSZl7rmpW6EbwLfFjwRngS++NEbpOPTUBuNy66fUjvsKinHHXdKJyBh7rZybNbKy73T3Jh24+BXOGd4EAIxVvWOBSdOAUlbGDvG+Siaj+Pzlz+a7FJWXlbK6pFSr6T86ayDlJeV2mGW1uHYgWEHhh0YdnQoIFGMRPR6yWUlvmWAlDog+o4OHR06OnR2SOiQ0CGhQwLJBl4aeKmG0dv92q8wfa20h1Ts+zBKUqrvSF7h2wyz5FtKRbwVo6z6FkC6qrFypLu8OA/ibhLUIFNskGgKCy1YbCcV2dmkZEM/UQIuK0fLjoF+Z2WiDLspQErjc1qPCiClsFOmwLuZTsdlrwqml74azXTeTM191O9zgcW5YSD/cl129Sn6MpaPjnvTqSmDpPFmsalFxmnaeRbXJnbuLwlsN5sQq5wVlSuhMjwqc7IAiYScVpFI0SqhETJQUdZ0FIanjqZ0Ac92oSkeB0ZFxwpJHOhjkunCZmefMfxcEIxSAzES7JPZJw32SRyeKAXFOYmnsnOgFFclQkfmOTwW4iGtkFmhyGKHWvHoHNk5po0VNu3URsE0hbb00wkhz4VEd/CzLbVQ0i2xc6xsIs8NHEa39MPKRmU2iJMpl9qrVjL7ZAoYWUkXR9kMTpNMfLoxKxK8iuZ1yc3gU4P5EGni07JkpWjPC0vrpJSSyhMLmVqRpSIhgNi3+pMGf+JRdisH4OKV1bokuFWHg+9RaXWNC+sA/WHmI2G1lt1KRRngHNQTFYii5zTP45R4MWd2q2eeoK9MvP+0IGVxDk61r5TgWBlTzgs4xsrXAcL5Sc53cl7hPD04ZtnAOXSv38q5nq/07YzxVR98gb6poaxviTqML9BfLhwKvBL4O8hWAVtUJByWYRyGUdjqZEtP/glvSMQmrgPMXEClz176Rqd5PZymJrkDTg/GerBp0LNxDuPRkm39apY4pHRTFN9rXeDe7ITad5IcIHnocyRpwssVORLeTV1PsEJy+zS9wm92Tp/uJbIiBtRQYPcaR2j0w6G7Db0iXSY3A62chCBtIVtHe0rkQPmg67UoRkSqnxYKr9mn0XmUcM6Ej0LuuRoCyspJ3LEq9FzemYCf59ClHEuCxBM8ikSBxnTCw+pspobkh/WBgV1Rw70DwyfEAjQ84tJSMxOdtxHzcLyIm/FHPVVM/WpgXLF5i5lJi6DREp5SN+/pFjUjs53RhuqIge0+o+zwyGL8OqTBo9qaK8WSThp3k2x3HFThqwMJqhLP4yaoEp4qoZWNYw8MOUlQA4xj4ObltOdzWlYrr8ixHKOBRzpp0dL3sD1Cb1/s9ZdqbXuwX2xj6dgqOqJl5URDnWNd0ei9P71N9TZmbiYaJkWU6cLCPJuF7moZARa4/PUJy+MaUA3MndeM4DLbFUus6z5JybebvPgsIS9+RshrmS5Iq3o4Pu1wVuk8dW40YrgsYlC1BnN8Sjfaxr/Ksm7ZlH6/6evuY5vpxc304mZ6rcs8HXY9hikPMkzWhA7TSrqwcOyRRfzEru7uh4ag5tYTIcU9MJszclBnM09PHTGBzkgONiN2hS140wPv2Mm7W5d98RNhw86wwVGu+zGT0JYECWmru5+0dVo2+5bBNh277KPz9CQVU0VpjBoZOQ1WKmIXPQBon8imi9FVQygmRoKoiAFTZ/znGIFVz0pa8c3OLd+yiiBv83Yx9tnNJ2pFD4TTqZl5X+IMvHoDKuHYH6LdJ5mDuJuJ1juPNieONs4E01Wi55EDxh+s1GUjcoqPETnFk6u8FsZU9Ky2HYv81hMrT8TXOCOmN80UB80TSfigOQHjvjy5P8j9aUxbHhGuSpn2KLMxz9iQpa4Fm5PLeGoodZuYpSw5YVHhk8WhhqIZDr9/WlbCODufnJ3krECvuv1Ue0KsZSWrFSwG6NeBxQG1Vqp1h1ob1drAqkNZwXKhek+o14H3QjWfULM+uNW0iQkTKczxFKZSmArePcp1/C2oiPWJMMr8dQtBoUahMAeE6RQGzNuIai5fhKkUpmAiBoSpFKZAmPthpa56f696m11dVo3nkIteQzekhrfhNleJcm3rbaeiDHSQ2ZyXoA7wJFbJgf5RUzFy8Kh4fqB6IdMaMdUEX5VOPLO286bjoVLSWHKg1ofRcsq1h8oXQl+tqKOevTWALXp4kL717iuasiMyMh36broEOyFtemHu+6cerHUFdYshpdTMnhy4xfrkwK0dZikdBKmGJ5eFb0oMcOyViF9KWHkXDQ0k/1KYfznteG2YMjAhzJBjt2KSBI2zbdF2wQGzO2E8uk96lDhpd8CVlrcgX/dLDXr0TYEfJrhdWdjRQQUvFPyEwA4ltKm4rr4UoVxdiLo3POhXgQPKBsErBYeghikDUwamDEwlIdxAZqeSpxOLQgRU3QVLdqnADakGVa63s5ZK3qzU/c8XOwpIz6mJBk0EaKJDE42aqNBAQNmhAYcSmhk0TSVeLehVDXiUSL2NRk1UaMChxPco1MQJTQRo4qQmKjVxQBPUQGWyBRLrUF8QYRdkxTTToytXsOvZr6RHk7qJkhDuX+e9qlSTlx1Kc2F+rlgKT/ruj74eGtrYdxm/JpZ5BS4kNSKRJlv0vBCWJg2UtEnPJ1c2CoYRw27joe7QmdGQ9KGhVSa2ZIoP20myrVUh7Uk6U0cBuZKtuEebu9gmDsXzJyiSa5YDgGZtT2257haN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/syn/spi_master_atlys_top.vhd
37,29 → 37,36
use ieee.std_logic_arith.all; |
|
entity spi_master_atlys_top is |
Generic ( |
N : positive := 8; -- 8bit serial word length is default |
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) |
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase. |
PREFETCH : positive := 3; -- prefetch lookahead cycles |
CLK_PERIOD : time := 10 ns; -- clock period for gclk_i (default 100MHz) |
DEBOUNCE_TIME : time := 200 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation) |
Port ( |
gclk_i : in std_logic := 'X'; -- board clock input 100MHz |
gclk_i : in std_logic := 'X'; -- board clock input 100MHz |
--- SPI interface --- |
spi_ssel_o : out std_logic; -- spi port SSEL |
spi_sck_o : out std_logic; -- spi port SCK |
spi_mosi_o : out std_logic; -- spi port MOSI |
spi_miso_o : out std_logic; -- spi port MISO |
spi_ssel_o : out std_logic; -- spi port SSEL |
spi_sck_o : out std_logic; -- spi port SCK |
spi_mosi_o : out std_logic; -- spi port MOSI |
spi_miso_o : out std_logic; -- spi port MISO |
--- input slide switches --- |
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches |
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches |
--- input buttons --- |
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons |
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons |
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
led_o : out std_logic_vector (7 downto 0); -- output leds |
--- debug outputs --- |
s_do_o : out std_logic_vector (7 downto 0); |
m_do_o : out std_logic_vector (7 downto 0); |
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state |
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state |
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins |
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state |
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state |
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins |
); |
end spi_master_atlys_top; |
|
architecture behavioral of spi_master_atlys_top is |
architecture rtl of spi_master_atlys_top is |
|
--============================================================================================= |
-- Constants |
69,10 → 76,6
constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz |
constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock |
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz |
-- spi port generics |
constant N : integer := 8; -- 8 bits |
constant CPOL : std_logic := '0'; |
constant CPHA : std_logic := '0'; |
|
-- button definitions |
constant btRESET : integer := 0; -- these are constants to use as btn_i(x) |
179,7 → 182,7
--============================================================================================= |
-- spi master port: data and control signals driven by the master fsm |
Inst_spi_master_port: entity work.spi_master(rtl) |
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV) |
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV) |
port map( |
sclk_i => gclk_i, -- system clock is used for serial and parallel ports |
pclk_i => gclk_i, |
200,7 → 203,7
|
-- spi slave port: data and control signals driven by the slave fsm |
Inst_spi_slave_port: entity work.spi_slave(rtl) |
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3) |
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH) |
port map( |
clk_i => gclk_i, |
spi_ssel_i => spi_ssel, -- driven by the spi master |
219,7 → 222,7
|
-- debounce for the input switches, with new data strobe output |
Inst_sw_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 8, CNT_VAL => 200) -- debounce 8 inputs with 200 us settling time |
generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => sw_i, -- noisy input data |
228,7 → 231,7
|
-- debounce for the input pushbuttons, with new data strobe output |
Inst_btn_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 6, CNT_VAL => 200) -- debounce 6 inputs with 200 us settling time |
generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => btn_i, -- noisy input data |
356,12 → 359,12
-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES |
--============================================================================================= |
-- edge detector for new switch data |
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for edge |
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for change edge |
|
-- edge detector for new button data |
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for edge |
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for change edge |
|
-- master port fsm state and combinatorial logic |
-- master port write fsmd logic |
fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, |
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg, |
new_button, clear) is |
459,7 → 462,7
end case; |
end process fsm_m_wr_combi_proc; |
|
-- slave port fsm state and combinatorial logic |
-- slave port write fsmd logic |
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s, |
spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is |
begin |
468,7 → 471,7
s_wr_st_next <= s_wr_st_reg; |
case s_wr_st_reg is |
when st_reset => |
spi_di_next_s <= X"D1"; -- write first data word |
spi_di_next_s <= X"51"; -- write first data word |
spi_wren_next_s <= '1'; -- set write enable |
s_wr_st_next <= st_wait_spi_start; |
|
482,6 → 485,7
if spi_di_req_s = '1' then |
-- spi_di_next_s <= X"D2"; -- do not write on this cycle (cycle miss) |
-- spi_wren_next_s <= '1'; |
-- s_wr_st_next <= st_wait_spi_ack_2; |
s_wr_st_next <= st_wait_spi_do_valid_1; |
end if; |
|
520,7 → 524,7
end case; |
end process fsm_s_wr_combi_proc; |
|
-- slave port fsm state and combinatorial logic |
-- slave port read fsmd logic |
fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is |
begin |
s_do_1_next <= s_do_1_reg; |
607,12 → 611,12
dbg(10) <= spi_wr_ack_m; |
dbg(9) <= spi_di_req_m; |
dbg(8) <= spi_do_valid_m; |
-- dbg(11 downto 8) <= spi_state_s; |
-- slave signals mapped on dbg |
dbg(7) <= spi_wren_reg_s; |
dbg(6) <= spi_wr_ack_s; |
dbg(5) <= spi_di_req_s; |
dbg(4) <= spi_do_valid_s; |
dbg(3 downto 0) <= spi_state_s; |
-- specific ports to test on testbench |
s_do_o <= spi_do_s; |
m_do_o <= spi_do_m; |
619,5 → 623,5
m_state_o <= spi_state_m; -- master spi fsm state |
s_state_o <= spi_state_s; -- slave spi fsm state |
|
end behavioral; |
end rtl; |
|
/syn/fuseRelaunch.cmd
1,5 → 623,5
-intstyle "ise" -incremental -lib "secureip" -o "D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.exe" -prj "D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_translate.prj" "work.testbench" |
-intstyle "ise" -incremental -lib "secureip" -o "C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn/testbench_isim_par.exe" -prj "C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn/testbench_par.prj" "work.testbench" |
/syn/spi_master.vhd
166,6 → 166,8
-- circuitry. |
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the |
-- synthesis tool will remove the receive logic from the generated circuitry. |
-- Alternatively, you can remove these ports and related circuitry once the core is verified and |
-- integrated to your circuit. |
--================================================================================================================ |
|
entity spi_master is |
211,7 → 213,7
-- all signals are clocked at the rising edge of the system clock 'sclk_i'. |
--================================================================================================================ |
architecture rtl of spi_master is |
-- core clocks, generated from 'sclk_i': initialized to differential values |
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values |
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic |
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic |
signal core_ce : std_logic := '0'; -- core clock enable, positive logic |
304,7 → 306,7
-- In order to preserve global clocking resources, the core clocking scheme is completely based |
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm, |
-- the spi clock generator and the input sampling clock. |
-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock |
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock |
-- for the core clocking. |
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only |
-- differential interconnect delay skew. |
/syn/ATLYS_05.SET
0,0 → 1,619
+o²Út‚ÚK_ÌnØÖiÞ£gl‘Ï8ï“ÞIgż2:´«6å„Às3(ˆv âjôð ¸Þk’2p‰Ì¿ùZp/îÄç¬aÕiþ4f6Å“©Íè’| kPÕÆÉxÒî@6¥úùŒÌѼҶðŸè® [ñðá¬õ•° Ñ™šÀÍåÓxœ×¹ƒú—éä¶ÑÍ@Ü꽺‰j‡ŠãMÚ8Ôi›¹—Ø$ö<ÜÚP²ÑŸ¢Oq—Ú¢·‰@´ ¹4?ðÜñP»5zJæÊ&]I6Ti¯ŸZôD·ÑŠx”&b°Ç.d¨y²-#X<κ›®p-ŽºJ×e¥PGÄþ“Þë´Eî£ö‘õ3ÍåÅ
+8x@aHà—1L^oü<:GÙŽÇN’áœ]‰É3aH•.ƒFõEØX ¶Afѳ×X”zÚ ß|)`ãºùâÇ5lÛ SGྨ}¶#'8¶êc†)öðï)OXãóÖüA <·òÈWù'ß|E©`@D ©Lw˜‘„\-\f¨œŸKÕ~¦(š?“^â 守 1…ÖVnÌã£õ@à¨ÙT'®ÂØ@&jM9ýÞ,Mµ÷"´ÆÅÆí9´ "UbœcD
\ No newline at end of file
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:TRIGGER:A:LOGIC:PATTERN:WHEN:LESSLIMIT 8.0000E-9 |
:TRIGGER:A:LOGIC:PATTERN:WHEN:MORELIMIT 8.0000E-9 |
:TRIGGER:A:LOGIC:PATTERN:DELTATIME 8.0000E-9 |
:TRIGGER:A:SETHOLD:CLOCK:SOURCE CH1 |
:TRIGGER:A:SETHOLD:CLOCK:EDGE RISE |
:TRIGGER:A:SETHOLD:CLOCK:THRESHOLD 160.0000E-3 |
:TRIGGER:A:SETHOLD:DATA:SOURCE NONE |
:TRIGGER:A:SETHOLD:DATA:THRESHOLD 9.9100E+37 |
:TRIGGER:A:SETHOLD:HOLDTIME 2.0000E-9 |
:TRIGGER:A:SETHOLD:SETTIME 2.0000E-9 |
:TRIGGER:A:SETHOLD:THRESHOLD:CH1 160.0000E-3 |
:TRIGGER:A:SETHOLD:THRESHOLD:CH2 0.0E+0 |
:TRIGGER:A:SETHOLD:THRESHOLD:CH3 0.0E+0 |
:TRIGGER:A:SETHOLD:THRESHOLD:CH4 0.0E+0 |
:TRIGGER:A:SETHOLD:THRESHOLD:D0 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D1 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D2 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D3 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D4 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D5 1.2600 |
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:TRIGGER:A:SETHOLD:THRESHOLD:D8 1.2600 |
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:TRIGGER:A:SETHOLD:THRESHOLD:D12 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D13 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D14 1.2600 |
:TRIGGER:A:SETHOLD:THRESHOLD:D15 1.2600 |
:TRIGGER:A:PULSE:CLASS WIDTH |
:TRIGGER:A:PULSEWIDTH:POLARITY POSITIVE |
:TRIGGER:A:PULSEWIDTH:WHEN MORETHAN |
:TRIGGER:A:PULSEWIDTH:WIDTH 95.0340E-6 |
:TRIGGER:A:RUNT:POLARITY POSITIVE |
:TRIGGER:A:RUNT:WHEN OCCURS |
:TRIGGER:A:RUNT:WIDTH 95.0340E-6 |
:TRIGGER:A:TRANSITION:POLARITY POSITIVE |
:TRIGGER:A:TRANSITION:WHEN SLOWER |
:TRIGGER:A:TRANSITION:DELTATIME 95.0340E-6 |
:TRIGGER:A:VIDEO:STANDARD NTSC |
:TRIGGER:A:VIDEO:SYNC ALLLINES |
:TRIGGER:A:VIDEO:LINE 1 |
:TRIGGER:A:VIDEO:HOLDOFF:FIELD 0.0E+0 |
:TRIGGER:A:VIDEO:POLARITY POSITIVE |
:TRIGGER:A:BUS:SOURCE B1 |
:TRIGGER:A:BUS:B1:RS232C:CONDITION TXSTART |
:TRIGGER:A:BUS:B2:RS232C:CONDITION TXSTART |
:TRIGGER:A:BUS:B1:RS232C:RX:DATA:SIZE 1 |
:TRIGGER:A:BUS:B2:RS232C:RX:DATA:SIZE 1 |
:TRIGGER:A:BUS:B1:RS232C:RX:DATA:VALUE "XXXXXXXX" |
:TRIGGER:A:BUS:B2:RS232C:RX:DATA:VALUE "XXXXXXXX" |
:TRIGGER:A:BUS:B1:RS232C:TX:DATA:SIZE 1 |
:TRIGGER:A:BUS:B2:RS232C:TX:DATA:SIZE 1 |
:TRIGGER:A:BUS:B1:RS232C:TX:DATA:VALUE "XXXXXXXX" |
:TRIGGER:A:BUS:B2:RS232C:TX:DATA:VALUE "XXXXXXXX" |
:TRIGGER:A:BUS:B1:PARALLEL:VALUE "XXXX" |
:TRIGGER:A:BUS:B2:PARALLEL:VALUE "XXXX" |
:TRIGGER:EXTERNAL:PROBE 10.0000 |
:BUS:B1:RS232C:PARITY NONE |
:BUS:B2:RS232C:PARITY NONE |
:BUS:B1:RS232C:BITRATE 9600 |
:BUS:B2:RS232C:BITRATE 9600 |
:BUS:B1:RS232C:POLARITY NORMAL |
:BUS:B2:RS232C:POLARITY NORMAL |
:BUS:B1:RS232C:DATABITS 8 |
:BUS:B2:RS232C:DATABITS 8 |
:BUS:B1:RS232C:TX:SOURCE CH1 |
:BUS:B2:RS232C:TX:SOURCE CH1 |
:BUS:B1:RS232C:RX:SOURCE D12 |
:BUS:B2:RS232C:RX:SOURCE OFF |
:BUS:B1:RS232C:DISPLAYMODE FRAME |
:BUS:B2:RS232C:DISPLAYMODE FRAME |
:BUS:B1:RS232C:DELIMITER LF |
:BUS:B2:RS232C:DELIMITER LF |
:BUS:B1:STATE 1 |
:BUS:B2:STATE 0 |
:BUS:B1:TYPE PARALLEL |
:BUS:B2:TYPE PARALLEL |
:BUS:B1:POSITION -940.0000E-3 |
:BUS:B2:POSITION 600.0000E-3 |
:BUS:B1:DISPLAY:TYPE BUS |
:BUS:B2:DISPLAY:TYPE BUS |
:BUS:B1:DISPLAY:FORMAT HEXADECIMAL |
:BUS:B2:DISPLAY:FORMAT HEXADECIMAL |
:BUS:B1:LABEL "state_s" |
:BUS:B2:LABEL "ST_S" |
:BUS:B1:PARALLEL:WIDTH 4 |
:BUS:B2:PARALLEL:WIDTH 4 |
:BUS:B1:PARALLEL:CLOCK:ISCLOCKED NO |
:BUS:B2:PARALLEL:CLOCK:ISCLOCKED NO |
:BUS:B1:PARALLEL:CLOCK:SOURCE D15 |
:BUS:B2:PARALLEL:CLOCK:SOURCE D15 |
:BUS:B1:PARALLEL:CLOCK:EDGE RISING |
:BUS:B2:PARALLEL:CLOCK:EDGE RISING |
:BUS:B1:PARALLEL:BIT0:SOURCE D0 |
:BUS:B1:PARALLEL:BIT1:SOURCE D1 |
:BUS:B1:PARALLEL:BIT2:SOURCE D2 |
:BUS:B1:PARALLEL:BIT3:SOURCE D3 |
:BUS:B1:PARALLEL:BIT4:SOURCE D4 |
:BUS:B1:PARALLEL:BIT5:SOURCE D5 |
:BUS:B1:PARALLEL:BIT6:SOURCE D6 |
:BUS:B1:PARALLEL:BIT7:SOURCE D7 |
:BUS:B1:PARALLEL:BIT8:SOURCE D8 |
:BUS:B1:PARALLEL:BIT9:SOURCE D9 |
:BUS:B1:PARALLEL:BIT10:SOURCE D10 |
:BUS:B1:PARALLEL:BIT11:SOURCE D11 |
:BUS:B1:PARALLEL:BIT12:SOURCE D12 |
:BUS:B1:PARALLEL:BIT13:SOURCE D13 |
:BUS:B1:PARALLEL:BIT14:SOURCE D14 |
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:BUS:B1:PARALLEL:BIT16:SOURCE CH1 |
:BUS:B1:PARALLEL:BIT17:SOURCE CH2 |
:BUS:B1:PARALLEL:BIT18:SOURCE CH3 |
:BUS:B1:PARALLEL:BIT19:SOURCE CH4 |
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:BUS:B2:PARALLEL:BIT2:SOURCE D10 |
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:BUS:B2:PARALLEL:BIT6:SOURCE D6 |
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:MEASUREMENT:MEAS3:SOURCE1 CH1 |
:MEASUREMENT:MEAS3:SOURCE2 CH2 |
/syn/spi_master_atlys_top_bit.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/syn/spi_master_atlys_top_map.psr
30,11 → 30,11
========================================================================= |
---- Statistics |
Number of SRLs added by SRL Inferencing | 4 |
Number of LUTs removed by SmartOpt Trimming | 463 |
Number of LUTs removed by SmartOpt Trimming | 511 |
Number of registers removed by SRL Inferencing | 8 |
Number of registers removed by Equivalence Removal | 4 |
|
Overall change in number of design objects | -471 |
Overall change in number of design objects | -519 |
|
|
---- Details |
61,469 → 61,517
Inst_spi_slave_port/state_reg_1_1 | Equivalence Removal |
Inst_spi_slave_port/state_reg_2_1 | Equivalence Removal |
Inst_spi_slave_port/state_reg_2_2 | Equivalence Removal |
][100_9 | SmartOpt Trimming |
][104_10 | SmartOpt Trimming |
][111_11 | SmartOpt Trimming |
][118_12 | SmartOpt Trimming |
][125_13 | SmartOpt Trimming |
][132_14 | SmartOpt Trimming |
][139_15 | SmartOpt Trimming |
][148_16 | SmartOpt Trimming |
][152_17 | SmartOpt Trimming |
][156_18 | SmartOpt Trimming |
][163_19 | SmartOpt Trimming |
][170_20 | SmartOpt Trimming |
][177_21 | SmartOpt Trimming |
][184_22 | SmartOpt Trimming |
][191_23 | SmartOpt Trimming |
][205_26 | SmartOpt Trimming |
][214_42 | SmartOpt Trimming |
][218_47 | SmartOpt Trimming |
][222_52 | SmartOpt Trimming |
][226_57 | SmartOpt Trimming |
][230_62 | SmartOpt Trimming |
][234_67 | SmartOpt Trimming |
][238_72 | SmartOpt Trimming |
][246_85 | SmartOpt Trimming |
][250_90 | SmartOpt Trimming |
][254_95 | SmartOpt Trimming |
][258_100 | SmartOpt Trimming |
][262_105 | SmartOpt Trimming |
][406_203 | SmartOpt Trimming |
][410_208 | SmartOpt Trimming |
][414_213 | SmartOpt Trimming |
][418_218 | SmartOpt Trimming |
][422_223 | SmartOpt Trimming |
][426_228 | SmartOpt Trimming |
][430_233 | SmartOpt Trimming |
][450_251 | SmartOpt Trimming |
][454_255 | SmartOpt Trimming |
][458_258 | SmartOpt Trimming |
][462_262 | SmartOpt Trimming |
][466_266 | SmartOpt Trimming |
][470_270 | SmartOpt Trimming |
][696_424 | SmartOpt Trimming |
][701_427 | SmartOpt Trimming |
][706_430 | SmartOpt Trimming |
][722_442 | SmartOpt Trimming |
][726_446 | SmartOpt Trimming |
][730_451 | SmartOpt Trimming |
][734_455 | SmartOpt Trimming |
][737_456 | SmartOpt Trimming |
][814_514 | SmartOpt Trimming |
][820_519 | SmartOpt Trimming |
][823_522 | SmartOpt Trimming |
][826_525 | SmartOpt Trimming |
][832_530 | SmartOpt Trimming |
][96_8 | SmartOpt Trimming |
][const_100_156 | SmartOpt Trimming |
][const_101_157 | SmartOpt Trimming |
][const_102_158 | SmartOpt Trimming |
][const_103_159 | SmartOpt Trimming |
][const_104_160 | SmartOpt Trimming |
][const_105_161 | SmartOpt Trimming |
][const_106_162 | SmartOpt Trimming |
][const_107_163 | SmartOpt Trimming |
][const_108_166 | SmartOpt Trimming |
][const_109_167 | SmartOpt Trimming |
][const_110_171 | SmartOpt Trimming |
][const_111_172 | SmartOpt Trimming |
][const_112_174 | SmartOpt Trimming |
][const_113_175 | SmartOpt Trimming |
][const_114_177 | SmartOpt Trimming |
][const_115_178 | SmartOpt Trimming |
][const_116_180 | SmartOpt Trimming |
][const_117_181 | SmartOpt Trimming |
][const_118_184 | SmartOpt Trimming |
][const_119_185 | SmartOpt Trimming |
][const_120_187 | SmartOpt Trimming |
][const_121_188 | SmartOpt Trimming |
][const_122_191 | SmartOpt Trimming |
][const_123_192 | SmartOpt Trimming |
][const_124_195 | SmartOpt Trimming |
][const_125_196 | SmartOpt Trimming |
][const_126_201 | SmartOpt Trimming |
][const_127_202 | SmartOpt Trimming |
][const_128_206 | SmartOpt Trimming |
][const_129_207 | SmartOpt Trimming |
][const_130_211 | SmartOpt Trimming |
][const_131_212 | SmartOpt Trimming |
][const_132_216 | SmartOpt Trimming |
][const_133_217 | SmartOpt Trimming |
][const_134_221 | SmartOpt Trimming |
][const_135_222 | SmartOpt Trimming |
][const_136_226 | SmartOpt Trimming |
][const_137_227 | SmartOpt Trimming |
][const_138_231 | SmartOpt Trimming |
][const_139_232 | SmartOpt Trimming |
][const_140_238 | SmartOpt Trimming |
][const_142_240 | SmartOpt Trimming |
][const_144_244 | SmartOpt Trimming |
][const_146_249 | SmartOpt Trimming |
][const_148_252 | SmartOpt Trimming |
][const_150_256 | SmartOpt Trimming |
][const_152_259 | SmartOpt Trimming |
][const_154_263 | SmartOpt Trimming |
][const_156_267 | SmartOpt Trimming |
][const_158_271 | SmartOpt Trimming |
][const_160_272 | SmartOpt Trimming |
][const_161_273 | SmartOpt Trimming |
][const_162_276 | SmartOpt Trimming |
][const_163_277 | SmartOpt Trimming |
][const_164_278 | SmartOpt Trimming |
][const_165_279 | SmartOpt Trimming |
][const_166_280 | SmartOpt Trimming |
][const_167_281 | SmartOpt Trimming |
][const_168_282 | SmartOpt Trimming |
][const_169_283 | SmartOpt Trimming |
][const_170_284 | SmartOpt Trimming |
][const_171_285 | SmartOpt Trimming |
][const_172_286 | SmartOpt Trimming |
][const_173_287 | SmartOpt Trimming |
][const_174_288 | SmartOpt Trimming |
][const_175_289 | SmartOpt Trimming |
][const_176_290 | SmartOpt Trimming |
][const_177_291 | SmartOpt Trimming |
][const_179_292 | SmartOpt Trimming |
][const_180_293 | SmartOpt Trimming |
][const_182_294 | SmartOpt Trimming |
][const_183_295 | SmartOpt Trimming |
][const_185_296 | SmartOpt Trimming |
][const_186_297 | SmartOpt Trimming |
][const_188_298 | SmartOpt Trimming |
][const_189_299 | SmartOpt Trimming |
][const_191_300 | SmartOpt Trimming |
][const_192_301 | SmartOpt Trimming |
][const_194_302 | SmartOpt Trimming |
][const_195_303 | SmartOpt Trimming |
][const_197_304 | SmartOpt Trimming |
][const_198_305 | SmartOpt Trimming |
][const_200_306 | SmartOpt Trimming |
][const_201_307 | SmartOpt Trimming |
][const_203_308 | SmartOpt Trimming |
][const_204_309 | SmartOpt Trimming |
][const_206_310 | SmartOpt Trimming |
][const_207_311 | SmartOpt Trimming |
][const_209_312 | SmartOpt Trimming |
][const_210_313 | SmartOpt Trimming |
][const_212_314 | SmartOpt Trimming |
][const_213_315 | SmartOpt Trimming |
][const_215_316 | SmartOpt Trimming |
][const_216_317 | SmartOpt Trimming |
][const_218_318 | SmartOpt Trimming |
][const_219_319 | SmartOpt Trimming |
][const_221_320 | SmartOpt Trimming |
][const_222_321 | SmartOpt Trimming |
][const_224_322 | SmartOpt Trimming |
][const_225_323 | SmartOpt Trimming |
][const_226_326 | SmartOpt Trimming |
][const_227_327 | SmartOpt Trimming |
][const_228_328 | SmartOpt Trimming |
][const_229_329 | SmartOpt Trimming |
][const_230_330 | SmartOpt Trimming |
][const_231_331 | SmartOpt Trimming |
][const_232_332 | SmartOpt Trimming |
][const_233_333 | SmartOpt Trimming |
][const_234_334 | SmartOpt Trimming |
][const_235_335 | SmartOpt Trimming |
][const_236_336 | SmartOpt Trimming |
][const_237_337 | SmartOpt Trimming |
][const_239_338 | SmartOpt Trimming |
][const_240_339 | SmartOpt Trimming |
][const_242_340 | SmartOpt Trimming |
][const_243_341 | SmartOpt Trimming |
][const_245_342 | SmartOpt Trimming |
][const_246_343 | SmartOpt Trimming |
][const_248_344 | SmartOpt Trimming |
][const_249_345 | SmartOpt Trimming |
][const_24_24 | SmartOpt Trimming |
][const_251_346 | SmartOpt Trimming |
][const_252_347 | SmartOpt Trimming |
][const_254_348 | SmartOpt Trimming |
][const_255_349 | SmartOpt Trimming |
][const_257_350 | SmartOpt Trimming |
][const_258_351 | SmartOpt Trimming |
][const_25_25 | SmartOpt Trimming |
][const_260_352 | SmartOpt Trimming |
][const_261_353 | SmartOpt Trimming |
][const_263_354 | SmartOpt Trimming |
][const_264_355 | SmartOpt Trimming |
][const_266_356 | SmartOpt Trimming |
][const_267_357 | SmartOpt Trimming |
][const_269_358 | SmartOpt Trimming |
][const_26_27 | SmartOpt Trimming |
][const_270_359 | SmartOpt Trimming |
][const_272_360 | SmartOpt Trimming |
][const_273_361 | SmartOpt Trimming |
][const_274_363 | SmartOpt Trimming |
][const_275_364 | SmartOpt Trimming |
][const_276_365 | SmartOpt Trimming |
][const_277_366 | SmartOpt Trimming |
][const_278_367 | SmartOpt Trimming |
][const_279_368 | SmartOpt Trimming |
][const_27_28 | SmartOpt Trimming |
][const_280_369 | SmartOpt Trimming |
][const_281_370 | SmartOpt Trimming |
][const_282_371 | SmartOpt Trimming |
][const_283_372 | SmartOpt Trimming |
][const_284_373 | SmartOpt Trimming |
][const_285_374 | SmartOpt Trimming |
][const_286_375 | SmartOpt Trimming |
][const_287_376 | SmartOpt Trimming |
][const_288_379 | SmartOpt Trimming |
][const_289_380 | SmartOpt Trimming |
][const_28_32 | SmartOpt Trimming |
][const_290_384 | SmartOpt Trimming |
][const_291_385 | SmartOpt Trimming |
][const_292_388 | SmartOpt Trimming |
][const_293_389 | SmartOpt Trimming |
][const_294_392 | SmartOpt Trimming |
][const_295_393 | SmartOpt Trimming |
][const_296_396 | SmartOpt Trimming |
][const_297_397 | SmartOpt Trimming |
][const_298_400 | SmartOpt Trimming |
][const_299_401 | SmartOpt Trimming |
][const_29_33 | SmartOpt Trimming |
][const_300_404 | SmartOpt Trimming |
][const_301_405 | SmartOpt Trimming |
][const_302_408 | SmartOpt Trimming |
][const_303_409 | SmartOpt Trimming |
][const_304_410 | SmartOpt Trimming |
][const_305_411 | SmartOpt Trimming |
][const_307_412 | SmartOpt Trimming |
][const_308_413 | SmartOpt Trimming |
][const_30_40 | SmartOpt Trimming |
][const_310_414 | SmartOpt Trimming |
][const_311_415 | SmartOpt Trimming |
][const_313_416 | SmartOpt Trimming |
][const_314_417 | SmartOpt Trimming |
][const_316_419 | SmartOpt Trimming |
][const_317_423 | SmartOpt Trimming |
][const_318_426 | SmartOpt Trimming |
][const_319_429 | SmartOpt Trimming |
][const_31_41 | SmartOpt Trimming |
][const_320_431 | SmartOpt Trimming |
][const_321_432 | SmartOpt Trimming |
][const_323_433 | SmartOpt Trimming |
][const_324_434 | SmartOpt Trimming |
][const_326_435 | SmartOpt Trimming |
][const_327_436 | SmartOpt Trimming |
][const_329_437 | SmartOpt Trimming |
][const_32_45 | SmartOpt Trimming |
][const_330_438 | SmartOpt Trimming |
][const_332_440 | SmartOpt Trimming |
][const_333_441 | SmartOpt Trimming |
][const_334_444 | SmartOpt Trimming |
][const_335_445 | SmartOpt Trimming |
][const_336_449 | SmartOpt Trimming |
][const_337_450 | SmartOpt Trimming |
][const_338_453 | SmartOpt Trimming |
][const_339_454 | SmartOpt Trimming |
][const_33_46 | SmartOpt Trimming |
][const_340_457 | SmartOpt Trimming |
][const_341_458 | SmartOpt Trimming |
][const_342_460 | SmartOpt Trimming |
][const_343_461 | SmartOpt Trimming |
][const_345_463 | SmartOpt Trimming |
][const_346_464 | SmartOpt Trimming |
][const_348_465 | SmartOpt Trimming |
][const_349_466 | SmartOpt Trimming |
][const_34_50 | SmartOpt Trimming |
][const_350_467 | SmartOpt Trimming |
][const_351_468 | SmartOpt Trimming |
][const_352_469 | SmartOpt Trimming |
][const_353_470 | SmartOpt Trimming |
][const_354_471 | SmartOpt Trimming |
][const_355_472 | SmartOpt Trimming |
][const_356_473 | SmartOpt Trimming |
][const_357_474 | SmartOpt Trimming |
][const_358_475 | SmartOpt Trimming |
][const_359_476 | SmartOpt Trimming |
][const_35_51 | SmartOpt Trimming |
][const_360_477 | SmartOpt Trimming |
][const_361_478 | SmartOpt Trimming |
][const_362_479 | SmartOpt Trimming |
][const_363_480 | SmartOpt Trimming |
][const_364_483 | SmartOpt Trimming |
][const_365_484 | SmartOpt Trimming |
][const_366_488 | SmartOpt Trimming |
][const_367_489 | SmartOpt Trimming |
][const_368_491 | SmartOpt Trimming |
][const_369_492 | SmartOpt Trimming |
][const_36_55 | SmartOpt Trimming |
][const_370_495 | SmartOpt Trimming |
][const_371_496 | SmartOpt Trimming |
][const_372_499 | SmartOpt Trimming |
][const_373_500 | SmartOpt Trimming |
][const_374_504 | SmartOpt Trimming |
][const_375_505 | SmartOpt Trimming |
][const_376_506 | SmartOpt Trimming |
][const_377_507 | SmartOpt Trimming |
][const_378_510 | SmartOpt Trimming |
][const_379_511 | SmartOpt Trimming |
][const_37_56 | SmartOpt Trimming |
][const_380_512 | SmartOpt Trimming |
][const_381_513 | SmartOpt Trimming |
][const_383_515 | SmartOpt Trimming |
][const_384_516 | SmartOpt Trimming |
][const_386_517 | SmartOpt Trimming |
][const_387_518 | SmartOpt Trimming |
][const_389_520 | SmartOpt Trimming |
][const_38_60 | SmartOpt Trimming |
][const_390_521 | SmartOpt Trimming |
][const_392_523 | SmartOpt Trimming |
][const_393_524 | SmartOpt Trimming |
][const_395_526 | SmartOpt Trimming |
][const_396_527 | SmartOpt Trimming |
][const_398_528 | SmartOpt Trimming |
][const_399_529 | SmartOpt Trimming |
][const_39_61 | SmartOpt Trimming |
][const_401_531 | SmartOpt Trimming |
][const_402_532 | SmartOpt Trimming |
][const_405_534 | SmartOpt Trimming |
][const_407_537 | SmartOpt Trimming |
][const_409_540 | SmartOpt Trimming |
][const_40_65 | SmartOpt Trimming |
][const_411_542 | SmartOpt Trimming |
][const_412_543 | SmartOpt Trimming |
][const_413_544 | SmartOpt Trimming |
][const_415_545 | SmartOpt Trimming |
][const_416_546 | SmartOpt Trimming |
][const_418_547 | SmartOpt Trimming |
][const_419_548 | SmartOpt Trimming |
][const_41_66 | SmartOpt Trimming |
][const_421_549 | SmartOpt Trimming |
][const_422_550 | SmartOpt Trimming |
][const_424_551 | SmartOpt Trimming |
][const_425_552 | SmartOpt Trimming |
][const_427_553 | SmartOpt Trimming |
][const_428_554 | SmartOpt Trimming |
][const_42_70 | SmartOpt Trimming |
][const_430_555 | SmartOpt Trimming |
][const_431_556 | SmartOpt Trimming |
][const_433_557 | SmartOpt Trimming |
][const_434_558 | SmartOpt Trimming |
][const_436_560 | SmartOpt Trimming |
][const_437_561 | SmartOpt Trimming |
][const_439_564 | SmartOpt Trimming |
][const_43_71 | SmartOpt Trimming |
][const_440_565 | SmartOpt Trimming |
][const_442_566 | SmartOpt Trimming |
][const_443_567 | SmartOpt Trimming |
][const_445_570 | SmartOpt Trimming |
][const_446_571 | SmartOpt Trimming |
][const_448_573 | SmartOpt Trimming |
][const_449_574 | SmartOpt Trimming |
][const_44_75 | SmartOpt Trimming |
][const_451_576 | SmartOpt Trimming |
][const_452_577 | SmartOpt Trimming |
][const_454_578 | SmartOpt Trimming |
][const_455_579 | SmartOpt Trimming |
][const_456_580 | SmartOpt Trimming |
][const_457_581 | SmartOpt Trimming |
][const_458_582 | SmartOpt Trimming |
][const_459_583 | SmartOpt Trimming |
][const_45_76 | SmartOpt Trimming |
][const_461_584 | SmartOpt Trimming |
][const_462_585 | SmartOpt Trimming |
][const_464_587 | SmartOpt Trimming |
][const_465_588 | SmartOpt Trimming |
][const_467_590 | SmartOpt Trimming |
][const_468_591 | SmartOpt Trimming |
][const_46_83 | SmartOpt Trimming |
][const_470_593 | SmartOpt Trimming |
][const_471_594 | SmartOpt Trimming |
][const_473_596 | SmartOpt Trimming |
][const_474_597 | SmartOpt Trimming |
][const_476_600 | SmartOpt Trimming |
][const_477_601 | SmartOpt Trimming |
][const_479_604 | SmartOpt Trimming |
][const_47_84 | SmartOpt Trimming |
][const_480_605 | SmartOpt Trimming |
][const_482_610 | SmartOpt Trimming |
][const_483_611 | SmartOpt Trimming |
][const_485_613 | SmartOpt Trimming |
][const_486_614 | SmartOpt Trimming |
][const_488_616 | SmartOpt Trimming |
][const_489_617 | SmartOpt Trimming |
][const_48_88 | SmartOpt Trimming |
][const_491_619 | SmartOpt Trimming |
][const_492_620 | SmartOpt Trimming |
][const_494_622 | SmartOpt Trimming |
][const_495_623 | SmartOpt Trimming |
][const_497_625 | SmartOpt Trimming |
][const_498_626 | SmartOpt Trimming |
][const_49_89 | SmartOpt Trimming |
][const_500_628 | SmartOpt Trimming |
][const_501_629 | SmartOpt Trimming |
][const_503_631 | SmartOpt Trimming |
][const_504_632 | SmartOpt Trimming |
][const_506_637 | SmartOpt Trimming |
][const_507_638 | SmartOpt Trimming |
][const_509_640 | SmartOpt Trimming |
][const_50_93 | SmartOpt Trimming |
][const_510_641 | SmartOpt Trimming |
][const_512_643 | SmartOpt Trimming |
][const_513_644 | SmartOpt Trimming |
][const_515_646 | SmartOpt Trimming |
][const_516_647 | SmartOpt Trimming |
][const_518_649 | SmartOpt Trimming |
][const_519_650 | SmartOpt Trimming |
][const_51_94 | SmartOpt Trimming |
][const_521_652 | SmartOpt Trimming |
][const_522_653 | SmartOpt Trimming |
][const_524_655 | SmartOpt Trimming |
][const_525_656 | SmartOpt Trimming |
][const_527_658 | SmartOpt Trimming |
][const_528_659 | SmartOpt Trimming |
][const_52_98 | SmartOpt Trimming |
][const_53_99 | SmartOpt Trimming |
][const_54_103 | SmartOpt Trimming |
][const_55_104 | SmartOpt Trimming |
][const_56_106 | SmartOpt Trimming |
][const_57_107 | SmartOpt Trimming |
][const_58_111 | SmartOpt Trimming |
][const_59_112 | SmartOpt Trimming |
][const_60_113 | SmartOpt Trimming |
][const_61_114 | SmartOpt Trimming |
][const_62_116 | SmartOpt Trimming |
][const_63_117 | SmartOpt Trimming |
][const_64_118 | SmartOpt Trimming |
][const_65_119 | SmartOpt Trimming |
][const_66_120 | SmartOpt Trimming |
][const_67_121 | SmartOpt Trimming |
][const_68_122 | SmartOpt Trimming |
][const_69_123 | SmartOpt Trimming |
][const_70_124 | SmartOpt Trimming |
][const_71_125 | SmartOpt Trimming |
][const_72_126 | SmartOpt Trimming |
][const_73_127 | SmartOpt Trimming |
][const_74_128 | SmartOpt Trimming |
][const_75_129 | SmartOpt Trimming |
][const_76_130 | SmartOpt Trimming |
][const_77_131 | SmartOpt Trimming |
][const_78_133 | SmartOpt Trimming |
][const_79_134 | SmartOpt Trimming |
][const_80_135 | SmartOpt Trimming |
][const_81_136 | SmartOpt Trimming |
][const_82_137 | SmartOpt Trimming |
][const_83_138 | SmartOpt Trimming |
][const_84_139 | SmartOpt Trimming |
][const_85_140 | SmartOpt Trimming |
][const_86_141 | SmartOpt Trimming |
][const_87_142 | SmartOpt Trimming |
][const_88_143 | SmartOpt Trimming |
][const_89_144 | SmartOpt Trimming |
][const_90_145 | SmartOpt Trimming |
][const_91_146 | SmartOpt Trimming |
][const_92_147 | SmartOpt Trimming |
][const_93_148 | SmartOpt Trimming |
][const_94_150 | SmartOpt Trimming |
][const_95_151 | SmartOpt Trimming |
][const_96_152 | SmartOpt Trimming |
][const_97_153 | SmartOpt Trimming |
][const_98_154 | SmartOpt Trimming |
][const_99_155 | SmartOpt Trimming |
][1017_599 | SmartOpt Trimming |
][124_6 | SmartOpt Trimming |
][128_7 | SmartOpt Trimming |
][132_8 | SmartOpt Trimming |
][139_9 | SmartOpt Trimming |
][146_10 | SmartOpt Trimming |
][153_11 | SmartOpt Trimming |
][160_12 | SmartOpt Trimming |
][167_13 | SmartOpt Trimming |
][174_14 | SmartOpt Trimming |
][181_15 | SmartOpt Trimming |
][188_16 | SmartOpt Trimming |
][195_17 | SmartOpt Trimming |
][202_18 | SmartOpt Trimming |
][209_19 | SmartOpt Trimming |
][216_20 | SmartOpt Trimming |
][225_21 | SmartOpt Trimming |
][229_22 | SmartOpt Trimming |
][233_23 | SmartOpt Trimming |
][240_24 | SmartOpt Trimming |
][247_25 | SmartOpt Trimming |
][254_26 | SmartOpt Trimming |
][261_27 | SmartOpt Trimming |
][268_28 | SmartOpt Trimming |
][275_29 | SmartOpt Trimming |
][282_30 | SmartOpt Trimming |
][289_31 | SmartOpt Trimming |
][296_32 | SmartOpt Trimming |
][303_33 | SmartOpt Trimming |
][310_34 | SmartOpt Trimming |
][317_35 | SmartOpt Trimming |
][331_38 | SmartOpt Trimming |
][340_53 | SmartOpt Trimming |
][344_58 | SmartOpt Trimming |
][348_63 | SmartOpt Trimming |
][352_68 | SmartOpt Trimming |
][356_73 | SmartOpt Trimming |
][360_78 | SmartOpt Trimming |
][364_83 | SmartOpt Trimming |
][500_179 | SmartOpt Trimming |
][504_183 | SmartOpt Trimming |
][508_187 | SmartOpt Trimming |
][512_191 | SmartOpt Trimming |
][516_196 | SmartOpt Trimming |
][520_200 | SmartOpt Trimming |
][524_205 | SmartOpt Trimming |
][532_216 | SmartOpt Trimming |
][536_221 | SmartOpt Trimming |
][540_226 | SmartOpt Trimming |
][544_231 | SmartOpt Trimming |
][548_236 | SmartOpt Trimming |
][552_241 | SmartOpt Trimming |
][556_246 | SmartOpt Trimming |
][576_265 | SmartOpt Trimming |
][580_269 | SmartOpt Trimming |
][584_273 | SmartOpt Trimming |
][588_277 | SmartOpt Trimming |
][592_281 | SmartOpt Trimming |
][596_285 | SmartOpt Trimming |
][822_441 | SmartOpt Trimming |
][827_445 | SmartOpt Trimming |
][832_448 | SmartOpt Trimming |
][848_460 | SmartOpt Trimming |
][852_464 | SmartOpt Trimming |
][856_469 | SmartOpt Trimming |
][860_474 | SmartOpt Trimming |
][863_475 | SmartOpt Trimming |
][937_536 | SmartOpt Trimming |
][940_539 | SmartOpt Trimming |
][943_542 | SmartOpt Trimming |
][946_545 | SmartOpt Trimming |
][949_548 | SmartOpt Trimming |
][952_551 | SmartOpt Trimming |
][958_556 | SmartOpt Trimming |
][const_100_161 | SmartOpt Trimming |
][const_101_162 | SmartOpt Trimming |
][const_102_163 | SmartOpt Trimming |
][const_103_164 | SmartOpt Trimming |
][const_104_165 | SmartOpt Trimming |
][const_105_166 | SmartOpt Trimming |
][const_106_167 | SmartOpt Trimming |
][const_107_168 | SmartOpt Trimming |
][const_108_171 | SmartOpt Trimming |
][const_109_172 | SmartOpt Trimming |
][const_110_177 | SmartOpt Trimming |
][const_111_178 | SmartOpt Trimming |
][const_112_181 | SmartOpt Trimming |
][const_113_182 | SmartOpt Trimming |
][const_114_185 | SmartOpt Trimming |
][const_115_186 | SmartOpt Trimming |
][const_116_189 | SmartOpt Trimming |
][const_117_190 | SmartOpt Trimming |
][const_118_194 | SmartOpt Trimming |
][const_119_195 | SmartOpt Trimming |
][const_120_198 | SmartOpt Trimming |
][const_121_199 | SmartOpt Trimming |
][const_122_203 | SmartOpt Trimming |
][const_123_204 | SmartOpt Trimming |
][const_124_208 | SmartOpt Trimming |
][const_125_209 | SmartOpt Trimming |
][const_126_214 | SmartOpt Trimming |
][const_127_215 | SmartOpt Trimming |
][const_128_219 | SmartOpt Trimming |
][const_129_220 | SmartOpt Trimming |
][const_130_224 | SmartOpt Trimming |
][const_131_225 | SmartOpt Trimming |
][const_132_229 | SmartOpt Trimming |
][const_133_230 | SmartOpt Trimming |
][const_134_234 | SmartOpt Trimming |
][const_135_235 | SmartOpt Trimming |
][const_136_239 | SmartOpt Trimming |
][const_137_240 | SmartOpt Trimming |
][const_138_244 | SmartOpt Trimming |
][const_139_245 | SmartOpt Trimming |
][const_140_251 | SmartOpt Trimming |
][const_142_254 | SmartOpt Trimming |
][const_144_258 | SmartOpt Trimming |
][const_146_262 | SmartOpt Trimming |
][const_148_266 | SmartOpt Trimming |
][const_150_270 | SmartOpt Trimming |
][const_152_274 | SmartOpt Trimming |
][const_154_278 | SmartOpt Trimming |
][const_156_282 | SmartOpt Trimming |
][const_158_286 | SmartOpt Trimming |
][const_160_287 | SmartOpt Trimming |
][const_161_288 | SmartOpt Trimming |
][const_162_292 | SmartOpt Trimming |
][const_163_293 | SmartOpt Trimming |
][const_164_294 | SmartOpt Trimming |
][const_165_295 | SmartOpt Trimming |
][const_166_296 | SmartOpt Trimming |
][const_167_297 | SmartOpt Trimming |
][const_168_298 | SmartOpt Trimming |
][const_169_299 | SmartOpt Trimming |
][const_170_300 | SmartOpt Trimming |
][const_171_301 | SmartOpt Trimming |
][const_172_302 | SmartOpt Trimming |
][const_173_303 | SmartOpt Trimming |
][const_174_304 | SmartOpt Trimming |
][const_175_305 | SmartOpt Trimming |
][const_176_306 | SmartOpt Trimming |
][const_177_307 | SmartOpt Trimming |
][const_179_308 | SmartOpt Trimming |
][const_180_309 | SmartOpt Trimming |
][const_182_310 | SmartOpt Trimming |
][const_183_311 | SmartOpt Trimming |
][const_185_312 | SmartOpt Trimming |
][const_186_313 | SmartOpt Trimming |
][const_188_314 | SmartOpt Trimming |
][const_189_315 | SmartOpt Trimming |
][const_191_316 | SmartOpt Trimming |
][const_192_317 | SmartOpt Trimming |
][const_194_318 | SmartOpt Trimming |
][const_195_319 | SmartOpt Trimming |
][const_197_320 | SmartOpt Trimming |
][const_198_321 | SmartOpt Trimming |
][const_200_322 | SmartOpt Trimming |
][const_201_323 | SmartOpt Trimming |
][const_203_324 | SmartOpt Trimming |
][const_204_325 | SmartOpt Trimming |
][const_206_326 | SmartOpt Trimming |
][const_207_327 | SmartOpt Trimming |
][const_209_328 | SmartOpt Trimming |
][const_210_329 | SmartOpt Trimming |
][const_212_330 | SmartOpt Trimming |
][const_213_331 | SmartOpt Trimming |
][const_215_332 | SmartOpt Trimming |
][const_216_333 | SmartOpt Trimming |
][const_218_334 | SmartOpt Trimming |
][const_219_335 | SmartOpt Trimming |
][const_221_336 | SmartOpt Trimming |
][const_222_337 | SmartOpt Trimming |
][const_224_338 | SmartOpt Trimming |
][const_225_339 | SmartOpt Trimming |
][const_226_343 | SmartOpt Trimming |
][const_227_344 | SmartOpt Trimming |
][const_228_345 | SmartOpt Trimming |
][const_229_346 | SmartOpt Trimming |
][const_230_347 | SmartOpt Trimming |
][const_231_348 | SmartOpt Trimming |
][const_232_349 | SmartOpt Trimming |
][const_233_350 | SmartOpt Trimming |
][const_234_351 | SmartOpt Trimming |
][const_235_352 | SmartOpt Trimming |
][const_236_353 | SmartOpt Trimming |
][const_237_354 | SmartOpt Trimming |
][const_239_355 | SmartOpt Trimming |
][const_240_356 | SmartOpt Trimming |
][const_242_357 | SmartOpt Trimming |
][const_243_358 | SmartOpt Trimming |
][const_245_359 | SmartOpt Trimming |
][const_246_360 | SmartOpt Trimming |
][const_248_361 | SmartOpt Trimming |
][const_249_362 | SmartOpt Trimming |
][const_24_36 | SmartOpt Trimming |
][const_251_363 | SmartOpt Trimming |
][const_252_364 | SmartOpt Trimming |
][const_254_365 | SmartOpt Trimming |
][const_255_366 | SmartOpt Trimming |
][const_257_367 | SmartOpt Trimming |
][const_258_368 | SmartOpt Trimming |
][const_25_37 | SmartOpt Trimming |
][const_260_369 | SmartOpt Trimming |
][const_261_370 | SmartOpt Trimming |
][const_263_371 | SmartOpt Trimming |
][const_264_372 | SmartOpt Trimming |
][const_266_373 | SmartOpt Trimming |
][const_267_374 | SmartOpt Trimming |
][const_269_375 | SmartOpt Trimming |
][const_26_39 | SmartOpt Trimming |
][const_270_376 | SmartOpt Trimming |
][const_272_377 | SmartOpt Trimming |
][const_273_378 | SmartOpt Trimming |
][const_274_380 | SmartOpt Trimming |
][const_275_381 | SmartOpt Trimming |
][const_276_382 | SmartOpt Trimming |
][const_277_383 | SmartOpt Trimming |
][const_278_384 | SmartOpt Trimming |
][const_279_385 | SmartOpt Trimming |
][const_27_40 | SmartOpt Trimming |
][const_280_386 | SmartOpt Trimming |
][const_281_387 | SmartOpt Trimming |
][const_282_388 | SmartOpt Trimming |
][const_283_389 | SmartOpt Trimming |
][const_284_390 | SmartOpt Trimming |
][const_285_391 | SmartOpt Trimming |
][const_286_392 | SmartOpt Trimming |
][const_287_393 | SmartOpt Trimming |
][const_288_396 | SmartOpt Trimming |
][const_289_397 | SmartOpt Trimming |
][const_28_43 | SmartOpt Trimming |
][const_290_401 | SmartOpt Trimming |
][const_291_402 | SmartOpt Trimming |
][const_292_405 | SmartOpt Trimming |
][const_293_406 | SmartOpt Trimming |
][const_294_409 | SmartOpt Trimming |
][const_295_410 | SmartOpt Trimming |
][const_296_413 | SmartOpt Trimming |
][const_297_414 | SmartOpt Trimming |
][const_298_417 | SmartOpt Trimming |
][const_299_418 | SmartOpt Trimming |
][const_29_44 | SmartOpt Trimming |
][const_300_421 | SmartOpt Trimming |
][const_301_422 | SmartOpt Trimming |
][const_302_425 | SmartOpt Trimming |
][const_303_426 | SmartOpt Trimming |
][const_304_427 | SmartOpt Trimming |
][const_305_428 | SmartOpt Trimming |
][const_307_429 | SmartOpt Trimming |
][const_308_430 | SmartOpt Trimming |
][const_30_51 | SmartOpt Trimming |
][const_310_431 | SmartOpt Trimming |
][const_311_432 | SmartOpt Trimming |
][const_313_433 | SmartOpt Trimming |
][const_314_434 | SmartOpt Trimming |
][const_316_436 | SmartOpt Trimming |
][const_317_440 | SmartOpt Trimming |
][const_318_444 | SmartOpt Trimming |
][const_319_447 | SmartOpt Trimming |
][const_31_52 | SmartOpt Trimming |
][const_320_449 | SmartOpt Trimming |
][const_321_450 | SmartOpt Trimming |
][const_323_451 | SmartOpt Trimming |
][const_324_452 | SmartOpt Trimming |
][const_326_453 | SmartOpt Trimming |
][const_327_454 | SmartOpt Trimming |
][const_329_455 | SmartOpt Trimming |
][const_32_56 | SmartOpt Trimming |
][const_330_456 | SmartOpt Trimming |
][const_332_458 | SmartOpt Trimming |
][const_333_459 | SmartOpt Trimming |
][const_334_462 | SmartOpt Trimming |
][const_335_463 | SmartOpt Trimming |
][const_336_467 | SmartOpt Trimming |
][const_337_468 | SmartOpt Trimming |
][const_338_472 | SmartOpt Trimming |
][const_339_473 | SmartOpt Trimming |
][const_33_57 | SmartOpt Trimming |
][const_340_476 | SmartOpt Trimming |
][const_341_477 | SmartOpt Trimming |
][const_342_479 | SmartOpt Trimming |
][const_343_480 | SmartOpt Trimming |
][const_345_482 | SmartOpt Trimming |
][const_346_483 | SmartOpt Trimming |
][const_348_484 | SmartOpt Trimming |
][const_349_485 | SmartOpt Trimming |
][const_34_61 | SmartOpt Trimming |
][const_350_486 | SmartOpt Trimming |
][const_351_487 | SmartOpt Trimming |
][const_352_488 | SmartOpt Trimming |
][const_353_489 | SmartOpt Trimming |
][const_354_490 | SmartOpt Trimming |
][const_355_491 | SmartOpt Trimming |
][const_356_492 | SmartOpt Trimming |
][const_357_493 | SmartOpt Trimming |
][const_358_494 | SmartOpt Trimming |
][const_359_495 | SmartOpt Trimming |
][const_35_62 | SmartOpt Trimming |
][const_360_496 | SmartOpt Trimming |
][const_361_497 | SmartOpt Trimming |
][const_362_498 | SmartOpt Trimming |
][const_363_499 | SmartOpt Trimming |
][const_364_504 | SmartOpt Trimming |
][const_365_505 | SmartOpt Trimming |
][const_366_509 | SmartOpt Trimming |
][const_367_510 | SmartOpt Trimming |
][const_368_514 | SmartOpt Trimming |
][const_369_515 | SmartOpt Trimming |
][const_36_66 | SmartOpt Trimming |
][const_370_518 | SmartOpt Trimming |
][const_371_519 | SmartOpt Trimming |
][const_372_522 | SmartOpt Trimming |
][const_373_523 | SmartOpt Trimming |
][const_374_528 | SmartOpt Trimming |
][const_375_529 | SmartOpt Trimming |
][const_376_530 | SmartOpt Trimming |
][const_377_531 | SmartOpt Trimming |
][const_378_534 | SmartOpt Trimming |
][const_379_535 | SmartOpt Trimming |
][const_37_67 | SmartOpt Trimming |
][const_380_537 | SmartOpt Trimming |
][const_381_538 | SmartOpt Trimming |
][const_383_540 | SmartOpt Trimming |
][const_384_541 | SmartOpt Trimming |
][const_386_543 | SmartOpt Trimming |
][const_387_544 | SmartOpt Trimming |
][const_389_546 | SmartOpt Trimming |
][const_38_71 | SmartOpt Trimming |
][const_390_547 | SmartOpt Trimming |
][const_392_549 | SmartOpt Trimming |
][const_393_550 | SmartOpt Trimming |
][const_395_552 | SmartOpt Trimming |
][const_396_553 | SmartOpt Trimming |
][const_398_554 | SmartOpt Trimming |
][const_399_555 | SmartOpt Trimming |
][const_39_72 | SmartOpt Trimming |
][const_401_557 | SmartOpt Trimming |
][const_402_558 | SmartOpt Trimming |
][const_405_560 | SmartOpt Trimming |
][const_407_563 | SmartOpt Trimming |
][const_409_566 | SmartOpt Trimming |
][const_40_76 | SmartOpt Trimming |
][const_411_568 | SmartOpt Trimming |
][const_412_569 | SmartOpt Trimming |
][const_413_570 | SmartOpt Trimming |
][const_415_571 | SmartOpt Trimming |
][const_416_572 | SmartOpt Trimming |
][const_418_573 | SmartOpt Trimming |
][const_419_574 | SmartOpt Trimming |
][const_41_77 | SmartOpt Trimming |
][const_421_575 | SmartOpt Trimming |
][const_422_576 | SmartOpt Trimming |
][const_424_577 | SmartOpt Trimming |
][const_425_578 | SmartOpt Trimming |
][const_427_579 | SmartOpt Trimming |
][const_428_580 | SmartOpt Trimming |
][const_42_81 | SmartOpt Trimming |
][const_430_581 | SmartOpt Trimming |
][const_431_582 | SmartOpt Trimming |
][const_433_583 | SmartOpt Trimming |
][const_434_584 | SmartOpt Trimming |
][const_436_585 | SmartOpt Trimming |
][const_437_586 | SmartOpt Trimming |
][const_439_589 | SmartOpt Trimming |
][const_43_82 | SmartOpt Trimming |
][const_440_590 | SmartOpt Trimming |
][const_442_593 | SmartOpt Trimming |
][const_443_594 | SmartOpt Trimming |
][const_445_597 | SmartOpt Trimming |
][const_446_598 | SmartOpt Trimming |
][const_449_600 | SmartOpt Trimming |
][const_44_89 | SmartOpt Trimming |
][const_450_602 | SmartOpt Trimming |
][const_451_603 | SmartOpt Trimming |
][const_453_605 | SmartOpt Trimming |
][const_454_606 | SmartOpt Trimming |
][const_456_607 | SmartOpt Trimming |
][const_457_608 | SmartOpt Trimming |
][const_458_609 | SmartOpt Trimming |
][const_459_610 | SmartOpt Trimming |
][const_45_90 | SmartOpt Trimming |
][const_460_611 | SmartOpt Trimming |
][const_461_612 | SmartOpt Trimming |
][const_463_613 | SmartOpt Trimming |
][const_464_614 | SmartOpt Trimming |
][const_466_617 | SmartOpt Trimming |
][const_467_618 | SmartOpt Trimming |
][const_469_620 | SmartOpt Trimming |
][const_46_93 | SmartOpt Trimming |
][const_470_621 | SmartOpt Trimming |
][const_472_625 | SmartOpt Trimming |
][const_473_626 | SmartOpt Trimming |
][const_475_629 | SmartOpt Trimming |
][const_476_630 | SmartOpt Trimming |
][const_478_633 | SmartOpt Trimming |
][const_479_634 | SmartOpt Trimming |
][const_47_94 | SmartOpt Trimming |
][const_481_637 | SmartOpt Trimming |
][const_482_638 | SmartOpt Trimming |
][const_484_644 | SmartOpt Trimming |
][const_485_645 | SmartOpt Trimming |
][const_487_647 | SmartOpt Trimming |
][const_488_648 | SmartOpt Trimming |
][const_48_97 | SmartOpt Trimming |
][const_490_650 | SmartOpt Trimming |
][const_491_651 | SmartOpt Trimming |
][const_493_653 | SmartOpt Trimming |
][const_494_654 | SmartOpt Trimming |
][const_496_656 | SmartOpt Trimming |
][const_497_657 | SmartOpt Trimming |
][const_499_659 | SmartOpt Trimming |
][const_49_98 | SmartOpt Trimming |
][const_500_660 | SmartOpt Trimming |
][const_502_662 | SmartOpt Trimming |
][const_503_663 | SmartOpt Trimming |
][const_505_665 | SmartOpt Trimming |
][const_506_666 | SmartOpt Trimming |
][const_508_668 | SmartOpt Trimming |
][const_509_669 | SmartOpt Trimming |
][const_50_101 | SmartOpt Trimming |
][const_511_671 | SmartOpt Trimming |
][const_512_672 | SmartOpt Trimming |
][const_514_674 | SmartOpt Trimming |
][const_515_675 | SmartOpt Trimming |
][const_517_677 | SmartOpt Trimming |
][const_518_678 | SmartOpt Trimming |
][const_51_102 | SmartOpt Trimming |
][const_520_680 | SmartOpt Trimming |
][const_521_681 | SmartOpt Trimming |
][const_523_683 | SmartOpt Trimming |
][const_524_684 | SmartOpt Trimming |
][const_526_686 | SmartOpt Trimming |
][const_527_687 | SmartOpt Trimming |
][const_529_692 | SmartOpt Trimming |
][const_52_105 | SmartOpt Trimming |
][const_530_693 | SmartOpt Trimming |
][const_532_695 | SmartOpt Trimming |
][const_533_696 | SmartOpt Trimming |
][const_535_698 | SmartOpt Trimming |
][const_536_699 | SmartOpt Trimming |
][const_538_701 | SmartOpt Trimming |
][const_539_702 | SmartOpt Trimming |
][const_53_106 | SmartOpt Trimming |
][const_541_704 | SmartOpt Trimming |
][const_542_705 | SmartOpt Trimming |
][const_544_707 | SmartOpt Trimming |
][const_545_708 | SmartOpt Trimming |
][const_547_710 | SmartOpt Trimming |
][const_548_711 | SmartOpt Trimming |
][const_54_109 | SmartOpt Trimming |
][const_550_713 | SmartOpt Trimming |
][const_551_714 | SmartOpt Trimming |
][const_553_716 | SmartOpt Trimming |
][const_554_717 | SmartOpt Trimming |
][const_556_719 | SmartOpt Trimming |
][const_557_720 | SmartOpt Trimming |
][const_559_722 | SmartOpt Trimming |
][const_55_110 | SmartOpt Trimming |
][const_560_723 | SmartOpt Trimming |
][const_562_725 | SmartOpt Trimming |
][const_563_726 | SmartOpt Trimming |
][const_565_728 | SmartOpt Trimming |
][const_566_729 | SmartOpt Trimming |
][const_568_731 | SmartOpt Trimming |
][const_569_732 | SmartOpt Trimming |
][const_56_111 | SmartOpt Trimming |
][const_571_734 | SmartOpt Trimming |
][const_572_735 | SmartOpt Trimming |
][const_57_112 | SmartOpt Trimming |
][const_58_116 | SmartOpt Trimming |
][const_59_117 | SmartOpt Trimming |
][const_60_118 | SmartOpt Trimming |
][const_61_119 | SmartOpt Trimming |
][const_62_121 | SmartOpt Trimming |
][const_63_122 | SmartOpt Trimming |
][const_64_123 | SmartOpt Trimming |
][const_65_124 | SmartOpt Trimming |
][const_66_125 | SmartOpt Trimming |
][const_67_126 | SmartOpt Trimming |
][const_68_127 | SmartOpt Trimming |
][const_69_128 | SmartOpt Trimming |
][const_70_129 | SmartOpt Trimming |
][const_71_130 | SmartOpt Trimming |
][const_72_131 | SmartOpt Trimming |
][const_73_132 | SmartOpt Trimming |
][const_74_133 | SmartOpt Trimming |
][const_75_134 | SmartOpt Trimming |
][const_76_135 | SmartOpt Trimming |
][const_77_136 | SmartOpt Trimming |
][const_78_138 | SmartOpt Trimming |
][const_79_139 | SmartOpt Trimming |
][const_80_140 | SmartOpt Trimming |
][const_81_141 | SmartOpt Trimming |
][const_82_142 | SmartOpt Trimming |
][const_83_143 | SmartOpt Trimming |
][const_84_144 | SmartOpt Trimming |
][const_85_145 | SmartOpt Trimming |
][const_86_146 | SmartOpt Trimming |
][const_87_147 | SmartOpt Trimming |
][const_88_148 | SmartOpt Trimming |
][const_89_149 | SmartOpt Trimming |
][const_90_150 | SmartOpt Trimming |
][const_91_151 | SmartOpt Trimming |
][const_92_152 | SmartOpt Trimming |
][const_93_153 | SmartOpt Trimming |
][const_94_155 | SmartOpt Trimming |
][const_95_156 | SmartOpt Trimming |
][const_96_157 | SmartOpt Trimming |
][const_97_158 | SmartOpt Trimming |
][const_98_159 | SmartOpt Trimming |
][const_99_160 | SmartOpt Trimming |
|
|
Flops added for Enable Generation |
/syn/spi_slave.vhd
127,8 → 127,9
-- data, the last data word is repeated. |
-- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word, |
-- the slave will send (others => '0') instead. |
-- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'. |
-- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
-- ==== |
174,6 → 175,8
-- circuitry. |
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the |
-- synthesis tool will remove the receive logic from the generated circuitry. |
-- Alternatively, you can remove these ports and related circuitry once the core is verified and |
-- integrated to your circuit. |
--================================================================================================================ |
|
architecture rtl of spi_slave is |
188,7 → 191,7
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can |
-- reduce the usability of the slice registers, due to the need to share the control |
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. |
-- By using GSR for the initialization, and reducing RESET local init to the bare |
-- By using GSR for the initialization, and reducing RESET local init to the really |
-- essential, the model achieves better LUT/FF packing and CLB usability. |
------------------------------------------------------------------------------------------ |
-- internal state signals for register and combinatorial stages |
198,9 → 201,10
signal sh_next : std_logic_vector (N-1 downto 0); |
signal sh_reg : std_logic_vector (N-1 downto 0); |
-- mosi and miso connections |
signal rx_bit_next : std_logic; |
signal rx_bit_next : std_logic; -- sample of MOSI input |
signal tx_bit_next : std_logic; |
signal tx_bit_reg : std_logic; |
signal tx_bit_reg : std_logic; -- drives MISO during sequential logic |
signal preload_miso : std_logic; -- controls the MISO MUX |
-- buffered di_i data signals for register and combinatorial stages |
signal di_reg : std_logic_vector (N-1 downto 0); |
-- internal wren_i stretcher for fsm combinatorial stage |
308,12 → 312,14
core_reg_proc : process (spi_sck_i, spi_ssel_i) is |
begin |
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) |
-- state fsm register (fdr) |
if spi_ssel_i = '1' then -- async clr |
state_reg <= 0; -- state falls back to idle when slave not selected |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register |
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock |
end if; |
-- FFD registers clocked on SHIFT edge |
-- rtl core registers (fd) |
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers |
sh_reg <= sh_next; -- core shift register |
do_buffer_reg <= do_buffer_next; -- registered data output |
321,7 → 327,15
di_req_reg <= di_req_next; -- input data request |
wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization |
end if; |
-- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1) |
-- miso MUX preload control register (fdp) |
if spi_ssel_i = '1' then -- async preset |
preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected |
elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output |
preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK |
end if; |
-- FFD registers clocked on CHANGE edge |
-- tx_bit register (fd) |
if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then |
tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb |
end if; |
418,16 → 432,16
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output |
|
----------------------------------------------------------------------------------------------- |
-- MISO driver process: copy next tx bit at reset |
-- MISO driver process: preload top bit of parallel data to MOSI at reset |
----------------------------------------------------------------------------------------------- |
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit |
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic. |
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is |
spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is |
begin |
if spi_ssel_i = '1' then |
spi_miso_o <= tx_bit_next; -- copy next => reg at reset |
if preload_miso = '1' then |
spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset |
else |
spi_miso_o <= tx_bit_reg; |
spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation |
end if; |
end process spi_miso_o_proc; |
|
/syn/spi_master_atlys_top.pcf
1,14 → 1,8
//! ************************************************************************** |
// Written by: Map O.40d on Wed Aug 10 22:56:48 2011 |
// Written by: Map O.40d on Mon Aug 29 00:08:35 2011 |
//! ************************************************************************** |
|
SCHEMATIC START; |
COMP "dbg_o<10>" LOCATE = SITE "V13" LEVEL 1; |
COMP "dbg_o<11>" LOCATE = SITE "U13" LEVEL 1; |
COMP "spi_miso_o" LOCATE = SITE "V15" LEVEL 1; |
COMP "spi_mosi_o" LOCATE = SITE "U15" LEVEL 1; |
COMP "sw_i<0>" LOCATE = SITE "A10" LEVEL 1; |
COMP "sw_i<1>" LOCATE = SITE "D14" LEVEL 1; |
COMP "sw_i<2>" LOCATE = SITE "C14" LEVEL 1; |
COMP "sw_i<3>" LOCATE = SITE "P15" LEVEL 1; |
COMP "sw_i<4>" LOCATE = SITE "P12" LEVEL 1; |
46,5 → 40,15
COMP "led_o<7>" LOCATE = SITE "N12" LEVEL 1; |
COMP "gclk_i" LOCATE = SITE "L15" LEVEL 1; |
COMP "spi_sck_o" LOCATE = SITE "V16" LEVEL 1; |
COMP "s_state_o<0>" LOCATE = SITE "V9" LEVEL 1; |
COMP "s_state_o<1>" LOCATE = SITE "T9" LEVEL 1; |
COMP "s_state_o<2>" LOCATE = SITE "V4" LEVEL 1; |
COMP "s_state_o<3>" LOCATE = SITE "T4" LEVEL 1; |
COMP "dbg_o<10>" LOCATE = SITE "V13" LEVEL 1; |
COMP "dbg_o<11>" LOCATE = SITE "U13" LEVEL 1; |
COMP "spi_miso_o" LOCATE = SITE "V15" LEVEL 1; |
COMP "spi_mosi_o" LOCATE = SITE "U15" LEVEL 1; |
COMP "sw_i<0>" LOCATE = SITE "A10" LEVEL 1; |
COMP "sw_i<1>" LOCATE = SITE "D14" LEVEL 1; |
SCHEMATIC END; |
|
/syn/spi_ms_atlys.xise
16,6 → 16,7
|
<files> |
<file xil_pn:name="spi_master_atlys_top.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="spi_master.vhd" xil_pn:type="FILE_VHDL"> |
31,7 → 32,7
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="spi_master_atlys_test.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="67"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> |
154,7 → 155,7
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="inst_spi_master_atlys_top" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="Inst_spi_master_atlys_top" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spi_master_atlys_top|behavioral" xil_pn:valueState="non-default"/> |
289,7 → 290,7
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="inst_spi_master_atlys_top" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="Inst_spi_master_atlys_top" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
/syn/par_usage_statistics.html
1,32 → 1,32
<TABLE BORDER CELLSPACING=0 WIDTH='100%'> |
<xtag-section name="ParStatistics"> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>302</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>829</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>829</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>710</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.2 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.6 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.9 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>335</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1055</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1055</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>941</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.3 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>9.3 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>7.8</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.6</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>2.7</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>26.3</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>8.8</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>2.9</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>2.5</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>28.8</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0172</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0238</xtag-par-property-value></TD></TR> |
</xtag-section> |
</TABLE> |
/syn/spi_master_atlys_top_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status</B></TD></TR> |
<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status (08/28/2011 - 23:35:14)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>spi_ms_atlys.xise</TD> |
19,12 → 19,13
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6slx45-2csg324</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> </TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD> </TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/*.xmsgs?&DataKey=Warning'>28 Warnings (0 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
31,20 → 32,22
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
All Signals Completely Routed</TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> |
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> </TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD>0 </TD> |
<TD> </TD> |
</TR> |
</TABLE> |
|
51,387 → 54,66
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
</TR> |
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>209</TD> |
<TD ALIGN=RIGHT>54,576</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
<TD ALIGN=RIGHT>218</TD> |
<TD ALIGN=RIGHT>54576</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> |
<TD ALIGN=RIGHT>209</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>145</TD> |
<TD ALIGN=RIGHT>27,288</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
<TD ALIGN=RIGHT>166</TD> |
<TD ALIGN=RIGHT>27288</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> |
<TD ALIGN=RIGHT>127</TD> |
<TD ALIGN=RIGHT>27,288</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>112</TD> |
<TD ALIGN=RIGHT>272</TD> |
<TD ALIGN=RIGHT COLSPAN='2'>41%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
<TD ALIGN=RIGHT>75</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
<TD ALIGN=RIGHT>13</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
<TD ALIGN=RIGHT>39</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>6,408</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD> |
<TD ALIGN=RIGHT>14</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD> |
<TD ALIGN=RIGHT>12</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
<TD ALIGN=RIGHT>91</TD> |
<TD ALIGN=RIGHT>6,822</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD> |
<TD ALIGN=RIGHT>49</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD ALIGN=RIGHT>21%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD> |
<TD ALIGN=RIGHT>80</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD ALIGN=RIGHT>35%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>96</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD ALIGN=RIGHT>42%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD> |
<TD ALIGN=RIGHT>25</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD> |
<TD ALIGN=RIGHT>59</TD> |
<TD ALIGN=RIGHT>54,576</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD> |
<TD ALIGN=RIGHT>63</TD> |
<TD ALIGN=RIGHT>218</TD> |
<TD ALIGN=RIGHT>28%</TD> |
<TD COLSPAN='2'> </TD> |
<TD ALIGN=RIGHT COLSPAN='2'>28%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD> |
<TD ALIGN=RIGHT>43</TD> |
<TD ALIGN=RIGHT>63</TD> |
<TD ALIGN=RIGHT>68%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>116</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>232</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>32</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>32</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>16</TD> |
<TD ALIGN=RIGHT>12%</TD> |
<TD COLSPAN='2'> </TD> |
<TD ALIGN=RIGHT COLSPAN='2'>12%</TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>8</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>376</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>376</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>376</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>256</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>8</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>58</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
<TD ALIGN=RIGHT>2.81</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> |
<TD>0 (Setup: 0, Hold: 0)</TD> |
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
All Signals Completely Routed</TD> |
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> |
<TD> |
<A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
<TD BGCOLOR='#FFFF99'><B> </B></TD> |
<TD COLSPAN='2'> </TD> |
</TABLE> |
|
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:56:21 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:56:49 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:57:01 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Aug 28 23:35:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Warning'>28 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Info'>24 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:23:42 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.mrp'>Map Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/map.xmsgs?&DataKey=Info'>13 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>qua 10. ago 22:57:08 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Sun Aug 28 23:24:19 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qua 10. ago 22:56:49 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>qua 10. ago 22:59:16 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:30:20 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/synthesis/spi_master_atlys_top_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:19:42 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/translate/spi_master_atlys_top_translate.nlf'>Post-Translate Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:19:45 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/map/spi_master_atlys_top_map.nlf'>Post-Map Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:20:15 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:24:01 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\netgen/par/spi_master_atlys_top_timesim.nlf'>Post-Place and Route Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sun Aug 28 23:24:26 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed Aug 10 23:31:06 2011</TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 08/11/2011 - 18:45:24</center> |
<br><center><b>Date Generated:</b> 08/28/2011 - 23:44:54</center> |
</BODY></HTML> |
/syn/spi_master_atlys_top.par
1,7 → 1,7
Release 13.1 par O.40d (nt) |
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
|
DEVELOP-W7:: Wed Aug 10 22:56:51 2011 |
DEVELOP-W7:: Mon Aug 29 00:08:38 2011 |
|
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd |
spi_master_atlys_top.ncd spi_master_atlys_top.pcf |
27,16 → 27,16
Device Utilization Summary: |
|
Slice Logic Utilization: |
Number of Slice Registers: 209 out of 54,576 1% |
Number used as Flip Flops: 209 |
Number of Slice Registers: 224 out of 54,576 1% |
Number used as Flip Flops: 224 |
Number used as Latches: 0 |
Number used as Latch-thrus: 0 |
Number used as AND/OR logics: 0 |
Number of Slice LUTs: 145 out of 27,288 1% |
Number used as logic: 127 out of 27,288 1% |
Number using O6 output only: 75 |
Number using O5 output only: 13 |
Number using O5 and O6: 39 |
Number of Slice LUTs: 177 out of 27,288 1% |
Number used as logic: 167 out of 27,288 1% |
Number using O6 output only: 112 |
Number using O5 output only: 28 |
Number using O5 and O6: 27 |
Number used as ROM: 0 |
Number used as Memory: 4 out of 6,408 1% |
Number used as Dual Port RAM: 0 |
45,17 → 45,17
Number using O6 output only: 4 |
Number using O5 output only: 0 |
Number using O5 and O6: 0 |
Number used exclusively as route-thrus: 14 |
Number with same-slice register load: 12 |
Number used exclusively as route-thrus: 6 |
Number with same-slice register load: 4 |
Number with same-slice carry load: 2 |
Number with other load: 0 |
|
Slice Logic Distribution: |
Number of occupied Slices: 91 out of 6,822 1% |
Number of LUT Flip Flop pairs used: 225 |
Number with an unused Flip Flop: 49 out of 225 21% |
Number with an unused LUT: 80 out of 225 35% |
Number of fully used LUT-FF pairs: 96 out of 225 42% |
Number of occupied Slices: 102 out of 6,822 1% |
Number of LUT Flip Flop pairs used: 272 |
Number with an unused Flip Flop: 64 out of 272 23% |
Number with an unused LUT: 95 out of 272 34% |
Number of fully used LUT-FF pairs: 113 out of 272 41% |
Number of slice register sites lost |
to control set restrictions: 0 out of 54,576 0% |
|
67,7 → 67,7
|
IO Utilization: |
Number of bonded IOBs: 63 out of 218 28% |
Number of LOCed IOBs: 43 out of 63 68% |
Number of LOCed IOBs: 47 out of 63 74% |
|
Specific Feature Utilization: |
Number of RAMB16BWERs: 0 out of 116 0% |
106,13 → 106,13
Starting Router |
|
|
Phase 1 : 910 unrouted; REAL time: 5 secs |
Phase 1 : 1133 unrouted; REAL time: 5 secs |
|
Phase 2 : 760 unrouted; REAL time: 6 secs |
Phase 2 : 972 unrouted; REAL time: 6 secs |
|
Phase 3 : 207 unrouted; REAL time: 7 secs |
Phase 3 : 282 unrouted; REAL time: 7 secs |
|
Phase 4 : 207 unrouted; (Par is working to improve performance) REAL time: 9 secs |
Phase 4 : 282 unrouted; (Par is working to improve performance) REAL time: 9 secs |
|
Updating file: spi_master_atlys_top.ncd with current fully routed design. |
|
148,11 → 148,11
Constraint | Check | Worst Case | Best Case | Timing | Timing |
| | Slack | Achievable | Errors | Score |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net gcl | SETUP | N/A| 5.299ns| N/A| 0 |
k_i_BUFGP | HOLD | 0.388ns| | 0| 0 |
Autotimespec constraint for clock net gcl | SETUP | N/A| 4.888ns| N/A| 0 |
k_i_BUFGP | HOLD | 0.378ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net Ins | SETUP | N/A| 5.052ns| N/A| 0 |
t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.497ns| | 0| 0 |
Autotimespec constraint for clock net Ins | SETUP | N/A| 3.948ns| N/A| 0 |
t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.459ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
|
|
171,7 → 171,7
Total REAL time to PAR completion: 10 secs |
Total CPU time to PAR completion: 10 secs |
|
Peak Memory Usage: 269 MB |
Peak Memory Usage: 264 MB |
|
Placer: Placement generated during map. |
Routing: Completed - No errors found. |
/syn/usage_statistics_webtalk.html
17,7 → 17,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD> |
<TD><xtag-property name="RandomID">d557c6c4bb5b4e4fa669c510e7b04848</xtag-property>.<xtag-property name="ProjectID">2C5BE631B69F48AB8C2F24035AF7A13B</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD> |
<TD><xtag-property name="RandomID">d557c6c4bb5b4e4fa669c510e7b04848</xtag-property>.<xtag-property name="ProjectID">2C5BE631B69F48AB8C2F24035AF7A13B</xtag-property>.<xtag-property name="ProjectIteration">5</xtag-property></TD> |
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD> |
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD> |
</TR> |
29,7 → 29,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD> |
<TD><xtag-property name="Date Generated">2011-08-10T22:59:16</xtag-property></TD> |
<TD><xtag-property name="Date Generated">2011-08-29T00:11:27</xtag-property></TD> |
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD> |
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD> |
</TR> |
84,21 → 84,21
<xtag-group><xtag-group-name name="Counters=5">Counters=5</xtag-group-name> |
<UL> |
<LI><xtag-item1>1-bit up counter=3</xtag-item1></LI> |
<LI><xtag-item1>8-bit up counter=2</xtag-item1></LI> |
<LI><xtag-item1>15-bit up counter=2</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="FSMs=3">FSMs=3</xtag-group-name> |
</xtag-group> |
<xtag-group><xtag-group-name name="Multiplexers=46">Multiplexers=46</xtag-group-name> |
<xtag-group><xtag-group-name name="Multiplexers=47">Multiplexers=47</xtag-group-name> |
<UL> |
<LI><xtag-item1>1-bit 2-to-1 multiplexer=20</xtag-item1></LI> |
<LI><xtag-item1>1-bit 2-to-1 multiplexer=21</xtag-item1></LI> |
<LI><xtag-item1>4-bit 2-to-1 multiplexer=12</xtag-item1></LI> |
<LI><xtag-item1>8-bit 2-to-1 multiplexer=14</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="Registers=205">Registers=205</xtag-group-name> |
<xtag-group><xtag-group-name name="Registers=206">Registers=206</xtag-group-name> |
<UL> |
<LI><xtag-item1>Flip-Flops=205</xtag-item1></LI> |
<LI><xtag-item1>Flip-Flops=206</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
109,34 → 109,34
<UL> |
<LI><xtag-item1>AGG_BONDED_IO=63</xtag-item1></LI> |
<LI><xtag-item1>AGG_IO=63</xtag-item1></LI> |
<LI><xtag-item1>AGG_LOCED_IO=43</xtag-item1></LI> |
<LI><xtag-item1>AGG_SLICE=91</xtag-item1></LI> |
<LI><xtag-item1>AGG_LOCED_IO=47</xtag-item1></LI> |
<LI><xtag-item1>AGG_SLICE=102</xtag-item1></LI> |
<LI><xtag-item1>NUM_BONDED_IOB=63</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSFULL=96</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSLUTONLY=49</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSREGONLY=80</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSUSED=225</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSFULL=113</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSLUTONLY=64</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSREGONLY=95</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSUSED=272</xtag-item1></LI> |
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOCED_IOB=43</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=39</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ONLY=13</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O6ONLY=75</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOCED_IOB=47</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=27</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ONLY=28</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O6ONLY=112</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO5=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO5=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_O6=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEL=8</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_O6=26</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEL=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEM=1</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEX=82</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CARRY4=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CONTROLSET=25</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CYINIT=198</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEX=89</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CARRY4=8</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CONTROLSET=26</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CYINIT=232</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_F7MUX=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_FF=209</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=15</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_FF=224</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=17</xtag-item1></LI> |
<LI><xtag-item1>NUM_SRL_O6ONLY=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=59</xtag-item1></LI> |
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=68</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
143,38 → 143,38
<TD> |
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name> |
<UL> |
<LI><xtag-item1>NumNets_Active=365</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Active=398</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=38</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=9</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=49</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=9</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=76</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=13</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=39</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=326</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=73</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=75</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_INPUT=8</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=58</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=58</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=561</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=313</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=298</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=44</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=8</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=85</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=12</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=43</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=338</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=77</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=66</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_INPUT=12</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=62</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=62</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=758</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=344</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=335</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=48</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=15</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=210</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=694</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_QUAD=616</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=101</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=431</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=248</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=903</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_QUAD=603</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=109</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=504</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=25</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=24</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=59</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=61</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=59</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=61</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=1</xtag-item1></LI> |
</UL> |
</xtag-group> |
183,9 → 183,9
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBM=33</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBS=30</xtag-item1></LI> |
<LI><xtag-item1>SLICEL-SLICEM=2</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEL=18</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEM=20</xtag-item1></LI> |
<LI><xtag-item1>SLICEL-SLICEM=7</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEL=12</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEM=30</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
196,22 → 196,22
<UL> |
<LI><xtag-item2>BUFG=2</xtag-item2></LI> |
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI> |
<LI><xtag-item2>CARRY4=4</xtag-item2></LI> |
<LI><xtag-item2>FF_SR=42</xtag-item2></LI> |
<LI><xtag-item2>CARRY4=8</xtag-item2></LI> |
<LI><xtag-item2>FF_SR=22</xtag-item2></LI> |
<LI><xtag-item2>HARD0=2</xtag-item2></LI> |
<LI><xtag-item2>IOB=63</xtag-item2></LI> |
<LI><xtag-item2>IOB_IMUX=15</xtag-item2></LI> |
<LI><xtag-item2>IOB_INBUF=15</xtag-item2></LI> |
<LI><xtag-item2>IOB_OUTBUF=48</xtag-item2></LI> |
<LI><xtag-item2>LUT5=64</xtag-item2></LI> |
<LI><xtag-item2>LUT6=128</xtag-item2></LI> |
<LI><xtag-item2>LUT5=59</xtag-item2></LI> |
<LI><xtag-item2>LUT6=167</xtag-item2></LI> |
<LI><xtag-item2>LUT_OR_MEM6=4</xtag-item2></LI> |
<LI><xtag-item2>PAD=63</xtag-item2></LI> |
<LI><xtag-item2>REG_SR=167</xtag-item2></LI> |
<LI><xtag-item2>REG_SR=202</xtag-item2></LI> |
<LI><xtag-item2>SELMUX2_1=4</xtag-item2></LI> |
<LI><xtag-item2>SLICEL=8</xtag-item2></LI> |
<LI><xtag-item2>SLICEL=12</xtag-item2></LI> |
<LI><xtag-item2>SLICEM=1</xtag-item2></LI> |
<LI><xtag-item2>SLICEX=82</xtag-item2></LI> |
<LI><xtag-item2>SLICEX=89</xtag-item2></LI> |
</UL> |
</xtag-group> |
</TD> |
223,9 → 223,9
<TD> |
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK=[CK:42] [CK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:42]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:36] [SYNC:6]</xtag-item3></LI> |
<LI><xtag-item3>CK=[CK:22] [CK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:22]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:17] [SYNC:5]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name> |
246,10 → 246,10
</xtag-group> |
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK=[CK:166] [CK_INV:1]</xtag-item3></LI> |
<LI><xtag-item3>LATCH_OR_FF=[FF:167]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:164] [SRINIT1:3]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:159] [SYNC:8]</xtag-item3></LI> |
<LI><xtag-item3>CK=[CK:200] [CK_INV:2]</xtag-item3></LI> |
<LI><xtag-item3>LATCH_OR_FF=[FF:202]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:198] [SRINIT1:4]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:193] [SYNC:9]</xtag-item3></LI> |
</UL> |
</TD> |
<TD> |
256,7 → 256,7
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:3] [CLK_INV:1]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:4] [CLK_INV:1]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> |
266,7 → 266,7
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:71] [CLK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:78] [CLK_INV:1]</xtag-item3></LI> |
</UL> |
</xtag-group> |
</TD> |
290,29 → 290,29
</xtag-group> |
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name> |
<UL> |
<LI><xtag-item1>CIN=2</xtag-item1></LI> |
<LI><xtag-item1>CO3=2</xtag-item1></LI> |
<LI><xtag-item1>CIN=6</xtag-item1></LI> |
<LI><xtag-item1>CO3=6</xtag-item1></LI> |
<LI><xtag-item1>CYINIT=2</xtag-item1></LI> |
<LI><xtag-item1>DI0=4</xtag-item1></LI> |
<LI><xtag-item1>DI1=4</xtag-item1></LI> |
<LI><xtag-item1>DI2=4</xtag-item1></LI> |
<LI><xtag-item1>DI3=2</xtag-item1></LI> |
<LI><xtag-item1>O0=4</xtag-item1></LI> |
<LI><xtag-item1>O1=4</xtag-item1></LI> |
<LI><xtag-item1>O2=4</xtag-item1></LI> |
<LI><xtag-item1>O3=4</xtag-item1></LI> |
<LI><xtag-item1>S0=4</xtag-item1></LI> |
<LI><xtag-item1>S1=4</xtag-item1></LI> |
<LI><xtag-item1>S2=4</xtag-item1></LI> |
<LI><xtag-item1>S3=4</xtag-item1></LI> |
<LI><xtag-item1>DI0=8</xtag-item1></LI> |
<LI><xtag-item1>DI1=8</xtag-item1></LI> |
<LI><xtag-item1>DI2=6</xtag-item1></LI> |
<LI><xtag-item1>DI3=6</xtag-item1></LI> |
<LI><xtag-item1>O0=8</xtag-item1></LI> |
<LI><xtag-item1>O1=8</xtag-item1></LI> |
<LI><xtag-item1>O2=8</xtag-item1></LI> |
<LI><xtag-item1>O3=6</xtag-item1></LI> |
<LI><xtag-item1>S0=8</xtag-item1></LI> |
<LI><xtag-item1>S1=8</xtag-item1></LI> |
<LI><xtag-item1>S2=8</xtag-item1></LI> |
<LI><xtag-item1>S3=6</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> |
<UL> |
<LI><xtag-item1>CE=20</xtag-item1></LI> |
<LI><xtag-item1>CK=42</xtag-item1></LI> |
<LI><xtag-item1>D=42</xtag-item1></LI> |
<LI><xtag-item1>Q=42</xtag-item1></LI> |
<LI><xtag-item1>CE=6</xtag-item1></LI> |
<LI><xtag-item1>CK=22</xtag-item1></LI> |
<LI><xtag-item1>D=22</xtag-item1></LI> |
<LI><xtag-item1>Q=22</xtag-item1></LI> |
<LI><xtag-item1>SR=7</xtag-item1></LI> |
</UL> |
</xtag-group> |
348,23 → 348,23
</xtag-group> |
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=17</xtag-item1></LI> |
<LI><xtag-item1>A2=29</xtag-item1></LI> |
<LI><xtag-item1>A3=31</xtag-item1></LI> |
<LI><xtag-item1>A4=30</xtag-item1></LI> |
<LI><xtag-item1>A5=35</xtag-item1></LI> |
<LI><xtag-item1>O5=64</xtag-item1></LI> |
<LI><xtag-item1>A1=16</xtag-item1></LI> |
<LI><xtag-item1>A2=18</xtag-item1></LI> |
<LI><xtag-item1>A3=22</xtag-item1></LI> |
<LI><xtag-item1>A4=25</xtag-item1></LI> |
<LI><xtag-item1>A5=26</xtag-item1></LI> |
<LI><xtag-item1>O5=59</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=34</xtag-item1></LI> |
<LI><xtag-item1>A2=66</xtag-item1></LI> |
<LI><xtag-item1>A3=97</xtag-item1></LI> |
<LI><xtag-item1>A4=108</xtag-item1></LI> |
<LI><xtag-item1>A5=126</xtag-item1></LI> |
<LI><xtag-item1>A6=128</xtag-item1></LI> |
<LI><xtag-item1>O6=128</xtag-item1></LI> |
<LI><xtag-item1>A1=63</xtag-item1></LI> |
<LI><xtag-item1>A2=123</xtag-item1></LI> |
<LI><xtag-item1>A3=127</xtag-item1></LI> |
<LI><xtag-item1>A4=134</xtag-item1></LI> |
<LI><xtag-item1>A5=165</xtag-item1></LI> |
<LI><xtag-item1>A6=167</xtag-item1></LI> |
<LI><xtag-item1>O6=167</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
390,11 → 390,11
</xtag-group> |
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> |
<UL> |
<LI><xtag-item1>CE=92</xtag-item1></LI> |
<LI><xtag-item1>CK=167</xtag-item1></LI> |
<LI><xtag-item1>D=167</xtag-item1></LI> |
<LI><xtag-item1>Q=167</xtag-item1></LI> |
<LI><xtag-item1>SR=11</xtag-item1></LI> |
<LI><xtag-item1>CE=106</xtag-item1></LI> |
<LI><xtag-item1>CK=202</xtag-item1></LI> |
<LI><xtag-item1>D=202</xtag-item1></LI> |
<LI><xtag-item1>Q=202</xtag-item1></LI> |
<LI><xtag-item1>SR=12</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name> |
407,41 → 407,47
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> |
<UL> |
<LI><xtag-item1>A=1</xtag-item1></LI> |
<LI><xtag-item1>A1=1</xtag-item1></LI> |
<LI><xtag-item1>A2=1</xtag-item1></LI> |
<LI><xtag-item1>A3=1</xtag-item1></LI> |
<LI><xtag-item1>A4=1</xtag-item1></LI> |
<LI><xtag-item1>A5=5</xtag-item1></LI> |
<LI><xtag-item1>A6=5</xtag-item1></LI> |
<LI><xtag-item1>AMUX=4</xtag-item1></LI> |
<LI><xtag-item1>A5=9</xtag-item1></LI> |
<LI><xtag-item1>A6=9</xtag-item1></LI> |
<LI><xtag-item1>AMUX=8</xtag-item1></LI> |
<LI><xtag-item1>AQ=2</xtag-item1></LI> |
<LI><xtag-item1>AX=1</xtag-item1></LI> |
<LI><xtag-item1>B5=4</xtag-item1></LI> |
<LI><xtag-item1>B6=4</xtag-item1></LI> |
<LI><xtag-item1>BMUX=4</xtag-item1></LI> |
<LI><xtag-item1>BQ=1</xtag-item1></LI> |
<LI><xtag-item1>BX=1</xtag-item1></LI> |
<LI><xtag-item1>B=1</xtag-item1></LI> |
<LI><xtag-item1>B1=1</xtag-item1></LI> |
<LI><xtag-item1>B2=1</xtag-item1></LI> |
<LI><xtag-item1>B3=1</xtag-item1></LI> |
<LI><xtag-item1>B4=1</xtag-item1></LI> |
<LI><xtag-item1>B5=9</xtag-item1></LI> |
<LI><xtag-item1>B6=9</xtag-item1></LI> |
<LI><xtag-item1>BMUX=8</xtag-item1></LI> |
<LI><xtag-item1>BQ=2</xtag-item1></LI> |
<LI><xtag-item1>BX=2</xtag-item1></LI> |
<LI><xtag-item1>C1=1</xtag-item1></LI> |
<LI><xtag-item1>C2=4</xtag-item1></LI> |
<LI><xtag-item1>C3=4</xtag-item1></LI> |
<LI><xtag-item1>C4=4</xtag-item1></LI> |
<LI><xtag-item1>C5=8</xtag-item1></LI> |
<LI><xtag-item1>C6=8</xtag-item1></LI> |
<LI><xtag-item1>CIN=2</xtag-item1></LI> |
<LI><xtag-item1>CLK=4</xtag-item1></LI> |
<LI><xtag-item1>CMUX=5</xtag-item1></LI> |
<LI><xtag-item1>COUT=2</xtag-item1></LI> |
<LI><xtag-item1>CQ=3</xtag-item1></LI> |
<LI><xtag-item1>CX=4</xtag-item1></LI> |
<LI><xtag-item1>C5=10</xtag-item1></LI> |
<LI><xtag-item1>C6=12</xtag-item1></LI> |
<LI><xtag-item1>CIN=6</xtag-item1></LI> |
<LI><xtag-item1>CLK=5</xtag-item1></LI> |
<LI><xtag-item1>CMUX=9</xtag-item1></LI> |
<LI><xtag-item1>COUT=6</xtag-item1></LI> |
<LI><xtag-item1>CQ=4</xtag-item1></LI> |
<LI><xtag-item1>CX=5</xtag-item1></LI> |
<LI><xtag-item1>D1=3</xtag-item1></LI> |
<LI><xtag-item1>D2=3</xtag-item1></LI> |
<LI><xtag-item1>D3=4</xtag-item1></LI> |
<LI><xtag-item1>D4=4</xtag-item1></LI> |
<LI><xtag-item1>D5=6</xtag-item1></LI> |
<LI><xtag-item1>D6=8</xtag-item1></LI> |
<LI><xtag-item1>DMUX=4</xtag-item1></LI> |
<LI><xtag-item1>DQ=1</xtag-item1></LI> |
<LI><xtag-item1>DX=1</xtag-item1></LI> |
<LI><xtag-item1>D5=10</xtag-item1></LI> |
<LI><xtag-item1>D6=10</xtag-item1></LI> |
<LI><xtag-item1>DMUX=6</xtag-item1></LI> |
<LI><xtag-item1>DQ=2</xtag-item1></LI> |
<LI><xtag-item1>DX=2</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
486,49 → 492,49
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> |
<UL> |
<LI><xtag-item1>A=16</xtag-item1></LI> |
<LI><xtag-item1>A1=16</xtag-item1></LI> |
<LI><xtag-item1>A2=26</xtag-item1></LI> |
<LI><xtag-item1>A3=32</xtag-item1></LI> |
<LI><xtag-item1>A4=34</xtag-item1></LI> |
<LI><xtag-item1>A5=35</xtag-item1></LI> |
<LI><xtag-item1>A6=32</xtag-item1></LI> |
<LI><xtag-item1>AMUX=13</xtag-item1></LI> |
<LI><xtag-item1>AQ=46</xtag-item1></LI> |
<LI><xtag-item1>AX=28</xtag-item1></LI> |
<LI><xtag-item1>A=12</xtag-item1></LI> |
<LI><xtag-item1>A1=25</xtag-item1></LI> |
<LI><xtag-item1>A2=38</xtag-item1></LI> |
<LI><xtag-item1>A3=38</xtag-item1></LI> |
<LI><xtag-item1>A4=42</xtag-item1></LI> |
<LI><xtag-item1>A5=44</xtag-item1></LI> |
<LI><xtag-item1>A6=43</xtag-item1></LI> |
<LI><xtag-item1>AMUX=10</xtag-item1></LI> |
<LI><xtag-item1>AQ=64</xtag-item1></LI> |
<LI><xtag-item1>AX=30</xtag-item1></LI> |
<LI><xtag-item1>B=10</xtag-item1></LI> |
<LI><xtag-item1>B1=8</xtag-item1></LI> |
<LI><xtag-item1>B2=14</xtag-item1></LI> |
<LI><xtag-item1>B3=19</xtag-item1></LI> |
<LI><xtag-item1>B4=23</xtag-item1></LI> |
<LI><xtag-item1>B5=24</xtag-item1></LI> |
<LI><xtag-item1>B6=22</xtag-item1></LI> |
<LI><xtag-item1>BMUX=8</xtag-item1></LI> |
<LI><xtag-item1>BQ=36</xtag-item1></LI> |
<LI><xtag-item1>B1=15</xtag-item1></LI> |
<LI><xtag-item1>B2=27</xtag-item1></LI> |
<LI><xtag-item1>B3=28</xtag-item1></LI> |
<LI><xtag-item1>B4=28</xtag-item1></LI> |
<LI><xtag-item1>B5=29</xtag-item1></LI> |
<LI><xtag-item1>B6=28</xtag-item1></LI> |
<LI><xtag-item1>BMUX=5</xtag-item1></LI> |
<LI><xtag-item1>BQ=43</xtag-item1></LI> |
<LI><xtag-item1>BX=24</xtag-item1></LI> |
<LI><xtag-item1>C=9</xtag-item1></LI> |
<LI><xtag-item1>C1=9</xtag-item1></LI> |
<LI><xtag-item1>C2=12</xtag-item1></LI> |
<LI><xtag-item1>C3=18</xtag-item1></LI> |
<LI><xtag-item1>C4=20</xtag-item1></LI> |
<LI><xtag-item1>C5=23</xtag-item1></LI> |
<LI><xtag-item1>C6=21</xtag-item1></LI> |
<LI><xtag-item1>CE=29</xtag-item1></LI> |
<LI><xtag-item1>CLK=71</xtag-item1></LI> |
<LI><xtag-item1>CMUX=8</xtag-item1></LI> |
<LI><xtag-item1>CQ=35</xtag-item1></LI> |
<LI><xtag-item1>CX=19</xtag-item1></LI> |
<LI><xtag-item1>D=14</xtag-item1></LI> |
<LI><xtag-item1>D1=13</xtag-item1></LI> |
<LI><xtag-item1>D2=21</xtag-item1></LI> |
<LI><xtag-item1>D3=25</xtag-item1></LI> |
<LI><xtag-item1>D4=28</xtag-item1></LI> |
<LI><xtag-item1>D5=30</xtag-item1></LI> |
<LI><xtag-item1>D6=28</xtag-item1></LI> |
<LI><xtag-item1>DMUX=21</xtag-item1></LI> |
<LI><xtag-item1>DQ=39</xtag-item1></LI> |
<LI><xtag-item1>DX=24</xtag-item1></LI> |
<LI><xtag-item1>SR=10</xtag-item1></LI> |
<LI><xtag-item1>C1=14</xtag-item1></LI> |
<LI><xtag-item1>C2=25</xtag-item1></LI> |
<LI><xtag-item1>C3=25</xtag-item1></LI> |
<LI><xtag-item1>C4=25</xtag-item1></LI> |
<LI><xtag-item1>C5=26</xtag-item1></LI> |
<LI><xtag-item1>C6=25</xtag-item1></LI> |
<LI><xtag-item1>CE=34</xtag-item1></LI> |
<LI><xtag-item1>CLK=79</xtag-item1></LI> |
<LI><xtag-item1>CMUX=6</xtag-item1></LI> |
<LI><xtag-item1>CQ=38</xtag-item1></LI> |
<LI><xtag-item1>CX=20</xtag-item1></LI> |
<LI><xtag-item1>D=15</xtag-item1></LI> |
<LI><xtag-item1>D1=16</xtag-item1></LI> |
<LI><xtag-item1>D2=30</xtag-item1></LI> |
<LI><xtag-item1>D3=30</xtag-item1></LI> |
<LI><xtag-item1>D4=32</xtag-item1></LI> |
<LI><xtag-item1>D5=34</xtag-item1></LI> |
<LI><xtag-item1>D6=31</xtag-item1></LI> |
<LI><xtag-item1>DMUX=10</xtag-item1></LI> |
<LI><xtag-item1>DQ=43</xtag-item1></LI> |
<LI><xtag-item1>DX=26</xtag-item1></LI> |
<LI><xtag-item1>SR=9</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
540,11 → 546,72
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD><B>Tool Usage</B></TD></TR> |
<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>fuse</xtag-cmdline></LI> |
</xtag-section></UL></TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR> |
570,8 → 637,8
</tr> |
<tr> |
<td><xtag-program-name>bitgen</xtag-program-name></td> |
<td><xtag-total-run-started>178</xtag-total-run-started></td> |
<td><xtag-total-run-finished>178</xtag-total-run-finished></td> |
<td><xtag-total-run-started>184</xtag-total-run-started></td> |
<td><xtag-total-run-finished>184</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
630,8 → 697,8
</tr> |
<tr> |
<td><xtag-program-name>map</xtag-program-name></td> |
<td><xtag-total-run-started>506</xtag-total-run-started></td> |
<td><xtag-total-run-finished>490</xtag-total-run-finished></td> |
<td><xtag-total-run-started>515</xtag-total-run-started></td> |
<td><xtag-total-run-finished>499</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
640,8 → 707,8
</tr> |
<tr> |
<td><xtag-program-name>netgen</xtag-program-name></td> |
<td><xtag-total-run-started>489</xtag-total-run-started></td> |
<td><xtag-total-run-finished>481</xtag-total-run-finished></td> |
<td><xtag-total-run-started>504</xtag-total-run-started></td> |
<td><xtag-total-run-finished>496</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
660,8 → 727,8
</tr> |
<tr> |
<td><xtag-program-name>ngdbuild</xtag-program-name></td> |
<td><xtag-total-run-started>550</xtag-total-run-started></td> |
<td><xtag-total-run-finished>550</xtag-total-run-finished></td> |
<td><xtag-total-run-started>561</xtag-total-run-started></td> |
<td><xtag-total-run-finished>561</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
670,8 → 737,8
</tr> |
<tr> |
<td><xtag-program-name>par</xtag-program-name></td> |
<td><xtag-total-run-started>522</xtag-total-run-started></td> |
<td><xtag-total-run-finished>464</xtag-total-run-finished></td> |
<td><xtag-total-run-started>531</xtag-total-run-started></td> |
<td><xtag-total-run-finished>473</xtag-total-run-finished></td> |
<td><xtag-total-error>14</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
690,8 → 757,8
</tr> |
<tr> |
<td><xtag-program-name>trce</xtag-program-name></td> |
<td><xtag-total-run-started>491</xtag-total-run-started></td> |
<td><xtag-total-run-finished>491</xtag-total-run-finished></td> |
<td><xtag-total-run-started>500</xtag-total-run-started></td> |
<td><xtag-total-run-finished>500</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
720,8 → 787,8
</tr> |
<tr> |
<td><xtag-program-name>xst</xtag-program-name></td> |
<td><xtag-total-run-started>848</xtag-total-run-started></td> |
<td><xtag-total-run-finished>843</xtag-total-run-finished></td> |
<td><xtag-total-run-started>878</xtag-total-run-started></td> |
<td><xtag-total-run-finished>873</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
795,7 → 862,7
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2011-07-07T09:55:20</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>2C5BE631B69F48AB8C2F24035AF7A13B</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>1</xtag-process-property-value></TD> |
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>5</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD> |
804,7 → 871,7
</TR><TR><TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_par</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_translate</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_selectedSimSourceNode</xtag-process-property-name>=<xtag-process-property-value>inst_spi_master_atlys_top</xtag-process-property-value></TD> |
</TR><TR><TD><xtag-process-property-name>PROP_selectedSimSourceNode</xtag-process-property-name>=<xtag-process-property-value>Inst_spi_master_atlys_top</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_xilxBitgStart_Clk_DriveDone</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_xilxMapReportDetail</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD> |
845,68 → 912,70
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>83</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>97</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>111</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDP_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>10</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>26</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>17</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>55</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>47</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>62</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>55</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>48</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>48</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>16</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>30</xtag-preunisim-param-value></TD> |
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>83</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>97</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>111</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDP_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>10</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>26</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>17</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>55</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>47</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>62</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>55</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>48</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>48</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>16</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>30</xtag-postunisim-param-value></TD> |
</xtag-section></TABLE> |
<BR></BODY></HTML> |
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="ISimStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR><TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>simprim</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>2183 ms, 136068 KB</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>10373</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>7082</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>2081</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>6468</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>21100 ns</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>4.55523 sec, 480030 KB</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR><TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR></xtag-section></TABLE></BODY></HTML> |
/syn/spi_ms_atlys.gise
29,6 → 29,28
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> |
<file xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"> |
<branch xil_pn:name="BehavioralSim"/> |
<branch xil_pn:name="PostTranslateSimulation"/> |
<branch xil_pn:name="PostRouteSimulation"/> |
</file> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"> |
<branch xil_pn:name="PostTranslateSimulation"/> |
<branch xil_pn:name="PostRouteSimulation"/> |
</file> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="netgen"/> |
<file xil_pn:branch="PostMapSimulation" xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/map/spi_master_atlys_top_map.nlf"/> |
<file xil_pn:branch="PostMapSimulation" xil_pn:fileType="FILE_SDF" xil_pn:name="netgen/map/spi_master_atlys_top_map.sdf"/> |
<file xil_pn:branch="PostMapSimulation" xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/map/spi_master_atlys_top_map.vhd"/> |
<file xil_pn:branch="PostRouteSimulation" xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/par/spi_master_atlys_top_timesim.nlf"/> |
<file xil_pn:branch="PostRouteSimulation" xil_pn:fileType="FILE_SDF" xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/> |
<file xil_pn:branch="PostRouteSimulation" xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/> |
<file xil_pn:branch="PostSynthSim" xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.nlf"/> |
<file xil_pn:branch="PostSynthSim" xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.vhd"/> |
<file xil_pn:branch="PostTranslateSimulation" xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/translate/spi_master_atlys_top_translate.nlf"/> |
<file xil_pn:branch="PostTranslateSimulation" xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spi_master_atlys_top.bgn" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="spi_master_atlys_top.bit" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="spi_master_atlys_top.bld"/> |
52,7 → 74,9
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spi_master_atlys_top.ut" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:fileType="FILE_XPI" xil_pn:name="spi_master_atlys_top.xpi"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spi_master_atlys_top.xst"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_master_atlys_top_envsettings.html"/> |
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spi_master_atlys_top_guide.ncd" xil_pn:origination="imported"/> |
<file xil_pn:branch="PostTranslateSimulation" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_master_atlys_top_isim_translate.exe"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spi_master_atlys_top_map.map" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spi_master_atlys_top_map.mrp" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="spi_master_atlys_top_map.ncd" xil_pn:subbranch="Map"/> |
63,107 → 87,318
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="spi_master_atlys_top_pad.csv" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="spi_master_atlys_top_pad.txt" xil_pn:subbranch="Par"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_master_atlys_top_par.xrpt"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_master_atlys_top_stx_beh.prj"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_master_atlys_top_stx_translate.prj"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_master_atlys_top_summary.html"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="spi_master_atlys_top_summary.xml"/> |
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="spi_master_atlys_top_usage.xml"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_master_atlys_top_xst.xrpt"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_beh.wdb"/> |
<file xil_pn:branch="PostRouteSimulation" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_par.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_par.wdb"/> |
<file xil_pn:branch="PostTranslateSimulation" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testbench_isim_translate.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testbench_isim_translate.wdb"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_par.prj"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_beh.prj"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_par.prj"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_translate.prj"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_translate.prj"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
<file xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"> |
<branch xil_pn:name="BehavioralSim"/> |
<branch xil_pn:name="PostTranslateSimulation"/> |
<branch xil_pn:name="PostRouteSimulation"/> |
</file> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> |
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314545579" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1314545579"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3566399560241464054" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314583834" xil_pn:in_ck="4343194839995565815" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1314583834"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="spi_master_atlys_test.vhd"/> |
<outfile xil_pn:name="spi_master_atlys_top.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2102355656976309210" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314545589" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="4434870115928851094" xil_pn:start_ts="1314545589"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314545589" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1902104842233773292" xil_pn:start_ts="1314545589"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1280022453574249608" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314545589" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2102355656976309210" xil_pn:start_ts="1314545589"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314545589" xil_pn:in_ck="5277757373456505906" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1314545589"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="spi_master_atlys_test.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1313027771" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-8317595265581962832" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314545598" xil_pn:in_ck="5277757373456505906" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="1459423336703152140" xil_pn:start_ts="1314545589"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="testbench_beh.prj"/> |
<outfile xil_pn:name="testbench_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1313027782" xil_pn:in_ck="-8247761554522826671" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8195216592062898977" xil_pn:start_ts="1313027771"> |
<transform xil_pn:end_ts="1314545598" xil_pn:in_ck="7130759491340027311" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5414671575160791934" xil_pn:start_ts="1314545598"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="testbench_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1314586086" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1314586086"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1314586086" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3566399560241464054" xil_pn:start_ts="1314586086"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1314586086" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2102355656976309210" xil_pn:start_ts="1314586086"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1314586086" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1314586086"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1314586086" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1280022453574249608" xil_pn:start_ts="1314586086"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1314586086" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1314586086"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1314586086" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-8317595265581962832" xil_pn:start_ts="1314586086"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1314587294" xil_pn:in_ck="-8247761554522826671" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8195216592062898977" xil_pn:start_ts="1314587285"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<status xil_pn:value="OutputRemoved"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="spi_master_atlys_top.lso"/> |
<outfile xil_pn:name="spi_master_atlys_top.ngc"/> |
<outfile xil_pn:name="spi_master_atlys_top.ngr"/> |
<outfile xil_pn:name="spi_master_atlys_top.prj"/> |
<outfile xil_pn:name="spi_master_atlys_top.stx"/> |
<outfile xil_pn:name="spi_master_atlys_top.syr"/> |
<outfile xil_pn:name="spi_master_atlys_top.xst"/> |
<outfile xil_pn:name="spi_master_atlys_top_stx_beh.prj"/> |
<outfile xil_pn:name="spi_master_atlys_top_stx_translate.prj"/> |
<outfile xil_pn:name="spi_master_atlys_top_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1313027782" xil_pn:in_ck="-6344801126424831697" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4068456177828066131" xil_pn:start_ts="1313027782"> |
<transform xil_pn:end_ts="1314587294" xil_pn:in_ck="-6344801126424831697" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4068456177828066131" xil_pn:start_ts="1314587294"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1313027787" xil_pn:in_ck="-2449764723691034422" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-177710677611610831" xil_pn:start_ts="1313027782"> |
<transform xil_pn:end_ts="1314587297" xil_pn:in_ck="-2449764723691034422" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-177710677611610831" xil_pn:start_ts="1314587294"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
<outfile xil_pn:name="spi_master_atlys_top.bld"/> |
<outfile xil_pn:name="spi_master_atlys_top.ngd"/> |
<outfile xil_pn:name="spi_master_atlys_top_ngdbuild.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1314587317" xil_pn:in_ck="-2449764723691034421" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1314587297"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
<outfile xil_pn:name="spi_master_atlys_top.pcf"/> |
<outfile xil_pn:name="spi_master_atlys_top_map.map"/> |
<outfile xil_pn:name="spi_master_atlys_top_map.mrp"/> |
<outfile xil_pn:name="spi_master_atlys_top_map.ncd"/> |
<outfile xil_pn:name="spi_master_atlys_top_map.ngm"/> |
<outfile xil_pn:name="spi_master_atlys_top_map.psr"/> |
<outfile xil_pn:name="spi_master_atlys_top_map.xrpt"/> |
<outfile xil_pn:name="spi_master_atlys_top_summary.xml"/> |
<outfile xil_pn:name="spi_master_atlys_top_usage.xml"/> |
</transform> |
<transform xil_pn:end_ts="1314587335" xil_pn:in_ck="5633518429974504804" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1314587317"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
<outfile xil_pn:name="spi_master_atlys_top.ncd"/> |
<outfile xil_pn:name="spi_master_atlys_top.pad"/> |
<outfile xil_pn:name="spi_master_atlys_top.par"/> |
<outfile xil_pn:name="spi_master_atlys_top.ptwx"/> |
<outfile xil_pn:name="spi_master_atlys_top.unroutes"/> |
<outfile xil_pn:name="spi_master_atlys_top.xpi"/> |
<outfile xil_pn:name="spi_master_atlys_top_pad.csv"/> |
<outfile xil_pn:name="spi_master_atlys_top_pad.txt"/> |
<outfile xil_pn:name="spi_master_atlys_top_par.xrpt"/> |
</transform> |
<transform xil_pn:end_ts="1314587493" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1314587477"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
<outfile xil_pn:name="spi_master_atlys_top.bgn"/> |
<outfile xil_pn:name="spi_master_atlys_top.bit"/> |
<outfile xil_pn:name="spi_master_atlys_top.drc"/> |
<outfile xil_pn:name="spi_master_atlys_top.ut"/> |
<outfile xil_pn:name="usage_statistics_webtalk.html"/> |
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1314586528" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRAN_postParSimModel" xil_pn:prop_ck="5598892574118791338" xil_pn:start_ts="1314586521"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputChanged"/> |
<outfile xil_pn:name="netgen"/> |
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.nlf"/> |
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/> |
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1314584667" xil_pn:in_ck="-7029858421675272663" xil_pn:name="TRAN_copyPost-ParAbstractToPreSimulation" xil_pn:start_ts="1314584667"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/> |
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/> |
<outfile xil_pn:name="spi_master_atlys_test.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1313027810" xil_pn:in_ck="-2449764723691034421" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1313027787"> |
<transform xil_pn:end_ts="1314584674" xil_pn:in_ck="9156795390127265392" xil_pn:name="TRAN_ISimulatePostPlace&RouteModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314584667"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<status xil_pn:value="OutputRemoved"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testbench_isim_par.exe"/> |
<outfile xil_pn:name="testbench_par.prj"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1313027829" xil_pn:in_ck="5633518429974504804" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1313027810"> |
<transform xil_pn:end_ts="1314584674" xil_pn:in_ck="7130759509275896515" xil_pn:name="TRAN_ISimulatePostPlace&RouteModel" xil_pn:prop_ck="-3956543683666394319" xil_pn:start_ts="1314584674"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testbench_isim_par.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1314587335" xil_pn:in_ck="-2449764723691034553" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1314587329"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
<outfile xil_pn:name="spi_master_atlys_top.twr"/> |
<outfile xil_pn:name="spi_master_atlys_top.twx"/> |
</transform> |
<transform xil_pn:end_ts="1314586520" xil_pn:in_ck="-2655376893977800779" xil_pn:name="TRAN_postMapSimModel" xil_pn:prop_ck="-119654110892640368" xil_pn:start_ts="1314586513"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputChanged"/> |
<outfile xil_pn:name="netgen"/> |
<outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.nlf"/> |
<outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.sdf"/> |
<outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1314586512" xil_pn:in_ck="-5988982649231273316" xil_pn:name="TRAN_postXlateSimModel" xil_pn:prop_ck="4032524037721565697" xil_pn:start_ts="1314586510"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputChanged"/> |
<outfile xil_pn:name="netgen"/> |
<outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.nlf"/> |
<outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1314584431" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_copyPost-TranslateAbstractToPreSimulation" xil_pn:start_ts="1314584431"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/> |
<outfile xil_pn:name="spi_master_atlys_test.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1313027964" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1313027946"> |
<transform xil_pn:end_ts="1314584434" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_ISimulatePostTranslateModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314584431"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testbench_isim_translate.exe"/> |
<outfile xil_pn:name="testbench_translate.prj"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1313027829" xil_pn:in_ck="-2449764723691034553" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1313027823"> |
<transform xil_pn:end_ts="1314584435" xil_pn:in_ck="-2373432107787769551" xil_pn:name="TRAN_ISimulatePostTranslateModel" xil_pn:prop_ck="-8441040086216995160" xil_pn:start_ts="1314584434"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testbench_isim_translate.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1314586509" xil_pn:in_ck="-5988982649231273317" xil_pn:name="TRAN_postSynthesisSimModel" xil_pn:prop_ck="367852130939253958" xil_pn:start_ts="1314586508"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputChanged"/> |
<outfile xil_pn:name="netgen"/> |
<outfile xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.nlf"/> |
<outfile xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.vhd"/> |
</transform> |
</transforms> |
|
</generated_project> |
/syn/spi_master_atlys.ucf
210,10 → 210,10
NET "m_state_o<1>" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, PMOD JB<2>, Sch name = JA-D0_P |
NET "m_state_o<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, PMOD JB<3>, Sch name = JA-D2_N |
NET "m_state_o<3>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, PMOD JB<4>, Sch name = JA-D2_P |
# NET "s_state_o<0>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, PMOD JB<7>, Sch name = JA-CLK_N |
# NET "s_state_o<1>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, PMOD JB<8>, Sch name = JA-CLK_P |
# NET "s_state_o<2>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, PMOD JB<9>, Sch name = JA-D1_N |
# NET "s_state_o<3>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P |
NET "s_state_o<0>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, PMOD JB<7>, Sch name = JA-CLK_N |
NET "s_state_o<1>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, PMOD JB<8>, Sch name = JA-CLK_P |
NET "s_state_o<2>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, PMOD JB<9>, Sch name = JA-D1_N |
NET "s_state_o<3>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P |
|
# onboard VHDCI |
# Channnel 1 connects to P signals, Channel 2 to N signals |
/syn/spi_master_atlys_top_map.mrp
12,7 → 12,7
Target Package : csg324 |
Target Speed : -2 |
Mapper Version : spartan6 -- $Revision: 1.55 $ |
Mapped Date : Wed Aug 10 22:56:29 2011 |
Mapped Date : Mon Aug 29 00:08:18 2011 |
|
Design Summary |
-------------- |
19,16 → 19,16
Number of errors: 0 |
Number of warnings: 0 |
Slice Logic Utilization: |
Number of Slice Registers: 209 out of 54,576 1% |
Number used as Flip Flops: 209 |
Number of Slice Registers: 224 out of 54,576 1% |
Number used as Flip Flops: 224 |
Number used as Latches: 0 |
Number used as Latch-thrus: 0 |
Number used as AND/OR logics: 0 |
Number of Slice LUTs: 145 out of 27,288 1% |
Number used as logic: 127 out of 27,288 1% |
Number using O6 output only: 75 |
Number using O5 output only: 13 |
Number using O5 and O6: 39 |
Number of Slice LUTs: 177 out of 27,288 1% |
Number used as logic: 167 out of 27,288 1% |
Number using O6 output only: 112 |
Number using O5 output only: 28 |
Number using O5 and O6: 27 |
Number used as ROM: 0 |
Number used as Memory: 4 out of 6,408 1% |
Number used as Dual Port RAM: 0 |
37,20 → 37,20
Number using O6 output only: 4 |
Number using O5 output only: 0 |
Number using O5 and O6: 0 |
Number used exclusively as route-thrus: 14 |
Number with same-slice register load: 12 |
Number used exclusively as route-thrus: 6 |
Number with same-slice register load: 4 |
Number with same-slice carry load: 2 |
Number with other load: 0 |
|
Slice Logic Distribution: |
Number of occupied Slices: 91 out of 6,822 1% |
Number of LUT Flip Flop pairs used: 225 |
Number with an unused Flip Flop: 49 out of 225 21% |
Number with an unused LUT: 80 out of 225 35% |
Number of fully used LUT-FF pairs: 96 out of 225 42% |
Number of unique control sets: 25 |
Number of occupied Slices: 102 out of 6,822 1% |
Number of LUT Flip Flop pairs used: 272 |
Number with an unused Flip Flop: 64 out of 272 23% |
Number with an unused LUT: 95 out of 272 34% |
Number of fully used LUT-FF pairs: 113 out of 272 41% |
Number of unique control sets: 26 |
Number of slice register sites lost |
to control set restrictions: 59 out of 54,576 1% |
to control set restrictions: 68 out of 54,576 1% |
|
A LUT Flip Flop pair for this architecture represents one LUT paired with |
one Flip Flop within a slice. A control set is a unique combination of |
60,7 → 60,7
|
IO Utilization: |
Number of bonded IOBs: 63 out of 218 28% |
Number of LOCed IOBs: 43 out of 63 68% |
Number of LOCed IOBs: 47 out of 63 74% |
|
Specific Feature Utilization: |
Number of RAMB16BWERs: 0 out of 116 0% |
87,10 → 87,10
Number of STARTUPs: 0 out of 1 0% |
Number of SUSPEND_SYNCs: 0 out of 1 0% |
|
Average Fanout of Non-Clock Nets: 2.81 |
Average Fanout of Non-Clock Nets: 3.18 |
|
Peak Memory Usage: 303 MB |
Total REAL time to MAP completion: 19 secs |
Peak Memory Usage: 298 MB |
Total REAL time to MAP completion: 17 secs |
Total CPU time to MAP completion (all processors): 17 secs |
|
Table of Contents |
142,8 → 142,8
1.260 Volts) |
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report |
(.mrp). |
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 43 are locked |
and 20 are not locked. If you would like to print the names of these IOs, |
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked |
and 16 are not locked. If you would like to print the names of these IOs, |
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. |
INFO:Pack:1650 - Map created a placed design. |
|
152,7 → 152,7
2 block(s) removed |
2 block(s) optimized away |
2 signal(s) removed |
55 Block(s) redundant |
87 Block(s) redundant |
|
Section 5 - Removed Logic |
------------------------- |
179,6 → 179,13
|
Redundant Block(s): |
TYPE BLOCK |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<13>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<12>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<11>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<10>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<9>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<8>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<7>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt |
185,6 → 192,13
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<13>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<12>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<11>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<10>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<9>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<8>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<7>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt |
191,49 → 205,67
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<7>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_xor<7>_rt |
INV ][1034_3_INV_0 |
INV ][269_110_INV_0 |
INV ][369_165_INV_0 |
INV ][373_170_INV_0 |
INV ][389_183_INV_0 |
INV ][397_190_INV_0 |
INV ][401_194_INV_0 |
INV ][402_198_INV_0 |
INV ][405_200_INV_0 |
INV ][409_205_INV_0 |
INV ][413_210_INV_0 |
INV ][417_215_INV_0 |
INV ][421_220_INV_0 |
INV ][425_225_INV_0 |
INV ][429_230_INV_0 |
INV ][441_243_INV_0 |
INV ][453_254_INV_0 |
INV ][461_261_INV_0 |
INV ][465_265_INV_0 |
INV ][469_269_INV_0 |
INV ][645_378_INV_0 |
INV ][649_383_INV_0 |
INV ][653_387_INV_0 |
INV ][657_391_INV_0 |
INV ][661_395_INV_0 |
INV ][665_399_INV_0 |
INV ][669_403_INV_0 |
INV ][673_407_INV_0 |
INV ][694_422_INV_0 |
INV ][729_448_INV_0 |
INV ][783_487_INV_0 |
INV ][791_494_INV_0 |
INV ][795_498_INV_0 |
INV ][799_503_INV_0 |
INV ][807_509_INV_0 |
INV ][840_536_INV_0 |
INV ][845_539_INV_0 |
INV ][882_563_INV_0 |
INV ][888_569_INV_0 |
INV ][923_599_INV_0 |
INV ][926_603_INV_0 |
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<14>_rt |
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_xor<14>_rt |
INV ][1211_3_INV_0 |
INV ][1212_5_INV_0 |
INV ][335_42_INV_0 |
INV ][339_50_INV_0 |
INV ][343_55_INV_0 |
INV ][347_60_INV_0 |
INV ][351_65_INV_0 |
INV ][355_70_INV_0 |
INV ][359_75_INV_0 |
INV ][363_80_INV_0 |
INV ][395_115_INV_0 |
INV ][495_170_INV_0 |
INV ][496_174_INV_0 |
INV ][499_176_INV_0 |
INV ][515_193_INV_0 |
INV ][523_202_INV_0 |
INV ][527_207_INV_0 |
INV ][528_211_INV_0 |
INV ][531_213_INV_0 |
INV ][535_218_INV_0 |
INV ][539_223_INV_0 |
INV ][543_228_INV_0 |
INV ][547_233_INV_0 |
INV ][551_238_INV_0 |
INV ][555_243_INV_0 |
INV ][563_253_INV_0 |
INV ][567_257_INV_0 |
INV ][575_264_INV_0 |
INV ][579_268_INV_0 |
INV ][583_272_INV_0 |
INV ][587_276_INV_0 |
INV ][591_280_INV_0 |
INV ][595_284_INV_0 |
INV ][771_395_INV_0 |
INV ][775_400_INV_0 |
INV ][779_404_INV_0 |
INV ][783_408_INV_0 |
INV ][787_412_INV_0 |
INV ][791_416_INV_0 |
INV ][795_420_INV_0 |
INV ][799_424_INV_0 |
INV ][820_439_INV_0 |
INV ][825_443_INV_0 |
INV ][855_466_INV_0 |
INV ][859_471_INV_0 |
INV ][909_508_INV_0 |
INV ][917_517_INV_0 |
INV ][921_521_INV_0 |
INV ][925_527_INV_0 |
INV ][933_533_INV_0 |
INV ][966_562_INV_0 |
INV ][971_565_INV_0 |
INV ][1008_588_INV_0 |
INV ][1011_592_INV_0 |
INV ][1014_596_INV_0 |
INV ][1042_616_INV_0 |
INV ][1051_628_INV_0 |
INV ][1054_632_INV_0 |
INV ][1057_636_INV_0 |
|
Section 6 - IOB Properties |
-------------------------- |
352,32 → 384,33
| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count | |
+-----------------------------------------------------------------------------------------------------------------------------------+ |
| Inst_spi_master_port/spi_clk_reg_BUFG | | | | 6 | 11 | |
| Inst_spi_master_port/spi_clk_reg_BUFG | | | lut1153_485 | 3 | 8 | |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][1032_0 | | | 2 | 3 | |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][IN_virtPIBox_530_660 | | | 1 | 1 | |
| Inst_spi_master_port/spi_clk_reg_BUFG | | | lut1117_506 | 3 | 8 | |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0 | | | 2 | 2 | |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][IN_virtPIBox_574_736 | | | 1 | 2 | |
+-----------------------------------------------------------------------------------------------------------------------------------+ |
| gclk_i_BUFGP | | | | 31 | 71 | |
| gclk_i_BUFGP | | | | 36 | 85 | |
| gclk_i_BUFGP | | | GLOBAL_LOGIC1 | 1 | 4 | |
| gclk_i_BUFGP | | | ][210_37 | 1 | 8 | |
| gclk_i_BUFGP | | | ][242_80 | 2 | 6 | |
| gclk_i_BUFGP | | | ][402_198 | 2 | 8 | |
| gclk_i_BUFGP | | | ][691_420 | 2 | 4 | |
| gclk_i_BUFGP | | | lut403_108 | 1 | 2 | |
| gclk_i_BUFGP | | | lut415_115 | 2 | 8 | |
| gclk_i_BUFGP | | | lut456_132 | 2 | 8 | |
| gclk_i_BUFGP | | | lut497_149 | 2 | 8 | |
| gclk_i_BUFGP | | | lut539_168 | 2 | 8 | |
| gclk_i_BUFGP | | | lut703_275 | 1 | 8 | |
| gclk_i_BUFGP | | | lut825_325 | 2 | 6 | |
| gclk_i_BUFGP | | | lut916_362 | 2 | 8 | |
| gclk_i_BUFGP | | | lut958_381 | 2 | 8 | |
| gclk_i_BUFGP | | | spi_wren_reg_m | 1 | 8 | |
| gclk_i_BUFGP | | | ][336_48 | 2 | 8 | |
| gclk_i_BUFGP | | | ][496_174 | 2 | 8 | |
| gclk_i_BUFGP | | | ][528_211 | 2 | 8 | |
| gclk_i_BUFGP | | | ][817_437 | 3 | 4 | |
| gclk_i_BUFGP | | | lut263_47 | 2 | 6 | |
| gclk_i_BUFGP | | | lut350_113 | 1 | 2 | |
| gclk_i_BUFGP | | | lut362_120 | 2 | 8 | |
| gclk_i_BUFGP | | | lut403_137 | 2 | 8 | |
| gclk_i_BUFGP | | | lut444_154 | 2 | 8 | |
| gclk_i_BUFGP | | | lut649_291 | 2 | 8 | |
| gclk_i_BUFGP | | | lut772_342 | 2 | 6 | |
| gclk_i_BUFGP | | | lut863_379 | 2 | 8 | |
| gclk_i_BUFGP | | | lut905_398 | 3 | 8 | |
| gclk_i_BUFGP | | | spi_wren_reg_m | 2 | 8 | |
| gclk_i_BUFGP | | | spi_wren_reg_s | 1 | 2 | |
| gclk_i_BUFGP | ][1032_0 | | | 4 | 6 | |
| gclk_i_BUFGP | ][1209_0 | | | 2 | 6 | |
| gclk_i_BUFGP | clear | | | 2 | 4 | |
| gclk_i_BUFGP | spi_rst_reg | | ][691_420 | 1 | 4 | |
| gclk_i_BUFGP | spi_rst_reg | | ][817_437 | 1 | 4 | |
+-----------------------------------------------------------------------------------------------------------------------------------+ |
| ~Inst_spi_master_port/spi_clk_reg_BUFG | | | | 1 | 1 | |
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0 | | | 1 | 1 | |
+-----------------------------------------------------------------------------------------------------------------------------------+ |
|
Section 13 - Utilization by Hierarchy |
385,11 → 418,11
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name | |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
| spi_master_atlys_top/ | | 64/121 | 71/209 | 109/119 | 0/4 | 0/0 | 0/0 | 1/2 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top | |
| +Inst_btn_debouncer | | 10/10 | 26/26 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_btn_debouncer | |
| +Inst_spi_master_port | | 18/18 | 45/45 | 2/2 | 2/2 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_master_port | |
| +Inst_spi_slave_port | | 21/21 | 35/35 | 6/6 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_slave_port | |
| +Inst_sw_debouncer | | 8/8 | 32/32 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_sw_debouncer | |
| spi_master_atlys_top/ | | 68/139 | 71/224 | 135/145 | 0/4 | 0/0 | 0/0 | 1/2 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top | |
| +Inst_btn_debouncer | | 14/14 | 33/33 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_btn_debouncer | |
| +Inst_spi_master_port | | 21/21 | 45/45 | 2/2 | 2/2 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_master_port | |
| +Inst_spi_slave_port | | 23/23 | 36/36 | 6/6 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_slave_port | |
| +Inst_sw_debouncer | | 13/13 | 39/39 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_sw_debouncer | |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
* Slices can be packed with basic elements from multiple hierarchies. |
/syn/spi_master_atlys_top_envsettings.html
16,44 → 16,44
<tr> |
<td>PATHEXT</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
</tr> |
<tr> |
<td>Path</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</font></td> |
</tr> |
<tr> |
<td>XILINX</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
</tr> |
<tr> |
<td>XILINX_DSP</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
</tr> |
<tr> |
<td>XILINX_EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
</tr> |
<tr> |
<td>XILINX_PLANAHEAD</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
</tr> |
</TABLE> |
<A NAME="Synthesis Property Settings"></A> |
350,28 → 350,28
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-dd</td> |
<td> </td> |
<td>_ngo</td> |
<td>None</td> |
<td><font color=gray>-dd</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>_ngo</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
<td><font color=gray>-p</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>xc6slx45-csg324-2</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-uc</td> |
<td> </td> |
<td>spi_master_atlys.ucf</td> |
<td>None</td> |
<td><font color=gray>-uc</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>spi_master_atlys.ucf</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
</TABLE> |
<A NAME="Map Property Settings"></A> |
386,100 → 386,100
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-detail</td> |
<td>Generate Detailed MAP Report</td> |
<td>TRUE</td> |
<td>TRUE</td> |
<td><font color=gray>-detail</font></td> |
<td><font color=gray>Generate Detailed MAP Report</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>TRUE</font></td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>high</td> |
<td><font color=gray>-ol</font></td> |
<td><font color=gray>Place & Route Effort Level (Overall)</font></td> |
<td><font color=gray>high</font></td> |
<td><font color=gray>high</font></td> |
</tr> |
<tr> |
<td>-xe</td> |
<td>Placer Extra Effort Map</td> |
<td>NORMAL</td> |
<td> </td> |
<td><font color=gray>-xe</font></td> |
<td><font color=gray>Placer Extra Effort Map</font></td> |
<td><font color=gray>NORMAL</font></td> |
<td><font color=gray> </font></td> |
</tr> |
<tr> |
<td>-xt</td> |
<td>Extra Cost Tables</td> |
<td>0</td> |
<td>0</td> |
<td><font color=gray>-xt</font></td> |
<td><font color=gray>Extra Cost Tables</font></td> |
<td><font color=gray>0</font></td> |
<td><font color=gray>0</font></td> |
</tr> |
<tr> |
<td>-global_opt</td> |
<td>Global Optimization map</td> |
<td>TRUE</td> |
<td>FALSE</td> |
<td><font color=gray>-global_opt</font></td> |
<td><font color=gray>Global Optimization map</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>FALSE</font></td> |
</tr> |
<tr> |
<td>-ir</td> |
<td>Use RLOC Constraints</td> |
<td>OFF</td> |
<td>OFF</td> |
<td><font color=gray>-ir</font></td> |
<td><font color=gray>Use RLOC Constraints</font></td> |
<td><font color=gray>OFF</font></td> |
<td><font color=gray>OFF</font></td> |
</tr> |
<tr> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>2</td> |
<td>0</td> |
<td><font color=gray>-mt</font></td> |
<td><font color=gray>Enable Multi-Threading</font></td> |
<td><font color=gray>2</font></td> |
<td><font color=gray>0</font></td> |
</tr> |
<tr> |
<td>-t</td> |
<td>Starting Placer Cost Table (1-100) Map</td> |
<td>1</td> |
<td>0</td> |
<td><font color=gray>-t</font></td> |
<td><font color=gray>Starting Placer Cost Table (1-100) Map</font></td> |
<td><font color=gray>1</font></td> |
<td><font color=gray>0</font></td> |
</tr> |
<tr> |
<td>-r</td> |
<td>Register Ordering</td> |
<td>4</td> |
<td>4</td> |
<td><font color=gray>-r</font></td> |
<td><font color=gray>Register Ordering</font></td> |
<td><font color=gray>4</font></td> |
<td><font color=gray>4</font></td> |
</tr> |
<tr> |
<td>-equivalent_register_removal</td> |
<td>Equivalent Register Removal</td> |
<td>TRUE</td> |
<td>TRUE</td> |
<td><font color=gray>-equivalent_register_removal</font></td> |
<td><font color=gray>Equivalent Register Removal</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>TRUE</font></td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-lc</td> |
<td>LUT Combining</td> |
<td>area</td> |
<td>off</td> |
<td><font color=gray>-lc</font></td> |
<td><font color=gray>LUT Combining</font></td> |
<td><font color=gray>area</font></td> |
<td><font color=gray>off</font></td> |
</tr> |
<tr> |
<td>-o</td> |
<td> </td> |
<td>spi_master_atlys_top_map.ncd</td> |
<td>None</td> |
<td><font color=gray>-o</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>spi_master_atlys_top_map.ncd</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
<td><font color=gray>-w</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>true</font></td> |
<td><font color=gray>false</font></td> |
</tr> |
<tr> |
<td>-pr</td> |
<td>Pack I/O Registers/Latches into IOBs</td> |
<td>off</td> |
<td>off</td> |
<td><font color=gray>-pr</font></td> |
<td><font color=gray>Pack I/O Registers/Latches into IOBs</font></td> |
<td><font color=gray>off</font></td> |
<td><font color=gray>off</font></td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
<td><font color=gray>-p</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>xc6slx45-csg324-2</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
</TABLE> |
<A NAME="Place and Route Property Settings"></A> |
494,34 → 494,34
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-xe</td> |
<td> </td> |
<td>n</td> |
<td>None</td> |
<td><font color=gray>-xe</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>n</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td> </td> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray> </font></td> |
</tr> |
<tr> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>4</td> |
<td>off</td> |
<td><font color=gray>-mt</font></td> |
<td><font color=gray>Enable Multi-Threading</font></td> |
<td><font color=gray>4</font></td> |
<td><font color=gray>off</font></td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>std</td> |
<td><font color=gray>-ol</font></td> |
<td><font color=gray>Place & Route Effort Level (Overall)</font></td> |
<td><font color=gray>high</font></td> |
<td><font color=gray>std</font></td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
<td><font color=gray>-w</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>true</font></td> |
<td><font color=gray>false</font></td> |
</tr> |
|