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URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

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/spi_master_slave/trunk/bench/spi_master_atlys_test.vhd
0,0 → 1,149
-- TestBench Template
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity testbench is
end testbench;
 
architecture behavior of testbench is
 
--=============================================================================================
-- Constants
--=============================================================================================
-- clock period
constant CLK_PERIOD : time := 10 ns;
 
-- button definitions
constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
constant btUP : integer := 1;
constant btLEFT : integer := 2;
constant btDOWN : integer := 3;
constant btRIGHT : integer := 4;
constant btCENTER : integer := 5;
 
--=============================================================================================
-- COMPONENT DECLARATIONS
--=============================================================================================
component spi_master_atlys_top
port(
gclk_i : in std_logic;
sw_i : in std_logic_vector(7 downto 0);
btn_i : in std_logic_vector(5 downto 0);
spi_ssel_o : out std_logic;
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_o : out std_logic;
led_o : out std_logic_vector(7 downto 0);
s_do_o : out std_logic_vector (7 downto 0);
m_do_o : out std_logic_vector (7 downto 0);
m_state_o : out std_logic_vector (3 downto 0);
s_state_o : out std_logic_vector (3 downto 0);
dbg_o : out std_logic_vector(11 downto 0)
);
end component;
 
--=============================================================================================
-- Signals for state machine control
--=============================================================================================
 
--=============================================================================================
-- Signals for internal operation
--=============================================================================================
--- clock signals ---
signal sysclk : std_logic := '0'; -- 100MHz clock
--- switch debouncer signals ---
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
--- pushbutton debouncer signals ---
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons
--- spi port signals ---
signal spi_ssel : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
-- debug output signals
signal leds : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
-- debug ports --
signal s_do_reg : std_logic_vector (7 downto 0);
signal m_do_reg : std_logic_vector (7 downto 0);
-- master signals mapped on dbg
signal wren_m : std_logic;
signal wr_ack_m : std_logic;
signal di_req_m : std_logic;
signal do_valid_m : std_logic;
signal master_state : std_logic_vector (3 downto 0);
-- slave signals mapped on dbg
signal wren_s : std_logic;
signal wr_ack_s : std_logic;
signal di_req_s : std_logic;
signal do_valid_s : std_logic;
signal slave_state : std_logic_vector (3 downto 0);
begin
 
--=============================================================================================
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
--=============================================================================================
-- spi_master_atlys_top:
-- receives the 100 MHz clock from the board clock oscillator
-- receives the 8 slide switches and 5 pushbuttons as test stimuli
-- connects to 4 spi signals
-- connects to 8 board LEDs
-- connects to 12 debug pins
inst_spi_master_atlys_top: spi_master_atlys_top
port map(
gclk_i => sysclk,
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
spi_miso_o => spi_miso,
sw_i => sw_data,
btn_i => btn_data,
led_o => leds,
m_state_o => master_state,
s_state_o => slave_state,
dbg_o => dbg
);
 
-- master signals mapped on dbg
wren_m <= dbg(11);
wr_ack_m <= dbg(10);
di_req_m <= dbg(9);
do_valid_m <= dbg(8);
-- slave signals mapped on dbg
wren_s <= dbg(7);
wr_ack_s <= dbg(6);
di_req_s <= dbg(5);
do_valid_s <= dbg(4);
 
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
gclk_proc: process is
begin
loop
sysclk <= not sysclk;
wait for CLK_PERIOD / 2;
end loop;
end process gclk_proc;
 
--=============================================================================================
-- TEST BENCH STIMULI
--=============================================================================================
tb : process
begin
wait for 100 ns; -- wait until global set/reset completes
 
btn_data(btRESET) <= '1';
wait for 1 us;
btn_data(btRESET) <= '0';
wait for 900 ns;
sw_data <= X"5A";
wait; -- will wait forever
end process tb;
-- End Test Bench
END;
/spi_master_slave/trunk/bench/spi_test_ct.wcfg
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/dropbox/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="testbench" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpackage" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="22" />
<wvobject fp_name="/testbench/dbg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dbg[11:0]</obj_property>
<obj_property name="ObjectShortName">dbg[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/sysclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sysclk</obj_property>
<obj_property name="ObjectShortName">sysclk</obj_property>
</wvobject>
<wvobject fp_name="/testbench/sw_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sw_data[7:0]</obj_property>
<obj_property name="ObjectShortName">sw_data[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/btn_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">btn_data[5:0]</obj_property>
<obj_property name="ObjectShortName">btn_data[5:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_ssel" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_ssel</obj_property>
<obj_property name="ObjectShortName">spi_ssel</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_sck" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_sck</obj_property>
<obj_property name="ObjectShortName">spi_sck</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_mosi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_mosi</obj_property>
<obj_property name="ObjectShortName">spi_mosi</obj_property>
</wvobject>
<wvobject fp_name="/testbench/dbg[3]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">dbg[3]</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_miso" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_miso</obj_property>
<obj_property name="ObjectShortName">spi_miso</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wren_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wren_m</obj_property>
<obj_property name="ObjectShortName">wren_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wr_ack_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wr_ack_m</obj_property>
<obj_property name="ObjectShortName">wr_ack_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/di_req_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">di_req_m</obj_property>
<obj_property name="ObjectShortName">di_req_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/do_valid_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">do_valid_m</obj_property>
<obj_property name="ObjectShortName">do_valid_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/m_do_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_do_reg[7:0]</obj_property>
<obj_property name="ObjectShortName">m_do_reg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/master_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">master_state[3:0]</obj_property>
<obj_property name="ObjectShortName">master_state[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wren_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wren_s</obj_property>
<obj_property name="ObjectShortName">wren_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wr_ack_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wr_ack_s</obj_property>
<obj_property name="ObjectShortName">wr_ack_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/di_req_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">di_req_s</obj_property>
<obj_property name="ObjectShortName">di_req_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/do_valid_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">do_valid_s</obj_property>
<obj_property name="ObjectShortName">do_valid_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/s_do_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_do_reg[7:0]</obj_property>
<obj_property name="ObjectShortName">s_do_reg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/leds" type="array" db_ref_id="1">
<obj_property name="ElementShortName">leds[7:0]</obj_property>
<obj_property name="ObjectShortName">leds[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/slave_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">slave_state[3:0]</obj_property>
<obj_property name="ObjectShortName">slave_state[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>
/spi_master_slave/trunk/rtl/spi_slave.vhd
115,6 → 115,10
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
-- Simulated in iSim with the master core for continuous transmission mode.
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
--
-----------------------------------------------------------------------------------------------------------------------
121,12 → 125,11
-- TODO
-- ====
--
--
-----------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
entity spi_slave is
Generic (
150,7 → 153,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
165,7 → 168,7
-- synthesis tool will remove the receive logic from the generated circuitry.
--================================================================================================================
 
architecture RTL of spi_slave is
architecture rtl of spi_slave is
-- constants to control FlipFlop synthesis
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge
180,25 → 183,25
-- By using GSR for the initialization, and reducing RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
------------------------------------------------------------------------------------------
-- internal state signals for register and combinational stages
-- internal state signals for register and combinatorial stages
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
-- shifter signals for register and combinational stages
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- mosi and miso connections
signal rx_bit_next : std_logic := '0';
signal tx_bit_next : std_logic := '0';
signal tx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinational stages
signal rx_bit_next : std_logic;
signal tx_bit_next : std_logic;
signal tx_bit_reg : std_logic;
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinational stage
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinational stages
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
291,7 → 294,7
end process in_transfer_proc;
 
--=============================================================================================
-- RTL CORE REGISTER PROCESSES
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT_EDGE
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
317,9 → 320,9
end process core_reg_proc;
 
--=============================================================================================
-- RTL COMBINATIONAL LOGIC PROCESSES
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinational logic
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
begin
332,15 → 335,16
di_req_next <= di_req_reg; -- data input request
state_next <= state_reg; -- fsm control state
case state_reg is
when (N) =>
-- acknowledge write enable
wr_ack_next <= '1'; -- acknowledge data in transfer
do_transfer_next <= '0'; -- reset transfer signal
-- stretch do_valid
wr_ack_next <= '0'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) =>
-- send bit out and shif bit in
do_transfer_next <= '0'; -- reset transfer signal
350,6 → 354,7
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 3 =>
-- raise data prefetch request
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
358,6 → 363,7
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when 2 =>
-- transfer parallel data on next state
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
368,6 → 374,7
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
do_buffer_next <= sh_next; -- get next data directly into rx buffer
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 =>
-- restart from state 'N' if more sck pulses come
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
374,7 → 381,6
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_reg
wr_ack_next <= '1'; -- acknowledge data in transfer
state_next <= N; -- next state is top bit of new data
383,44 → 389,53
sh_next <= (others => '0'); -- load null data (output '0' if no load)
state_next <= 0; -- next state is idle state
end if;
when 0 =>
-- idle state: start and end of transmission
if CPHA = '1' then
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
else
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= not wr_ack_reg; -- will request data if shifter empty
sh_next <= di_reg; -- load parallel data from di_reg into shifter
end if;
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
state_next <= N; -- next state is top bit of new data
when others =>
state_next <= 0; -- safe state
end case;
end process core_combi_proc;
 
--=============================================================================================
-- RTL OUTPUT LOGIC PROCESSES
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
 
-----------------------------------------------------------------------------------------------
-- MISO driver process: copy next tx bit at reset
-----------------------------------------------------------------------------------------------
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is
begin
if spi_ssel_i = '1' then
spi_miso_o <= tx_bit_next; -- copy next => reg at reset
else
spi_miso_o <= tx_bit_reg;
end if;
end process spi_miso_o_proc;
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted or commented-out after debug.
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next;
wren_o_proc: wren_o <= wren;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture RTL;
end architecture rtl;
 
/spi_master_slave/trunk/rtl/spi_master.vhd
13,6 → 13,7
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
143,6 → 144,8
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
193,7 → 196,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
206,7 → 209,7
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture RTL of spi_master is
architecture rtl of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
234,14 → 237,14
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic := '0';
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
251,8 → 254,8
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
309,7 → 312,7
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources.
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
357,7 → 360,6
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
381,7 → 383,8
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
 
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
388,10 → 391,6
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
--
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
-- REDUCED DEMAND ON MISO SETUP TIME.
--
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
450,7 → 449,7
end process in_transfer_proc;
 
--=============================================================================================
-- RTL REGISTER PROCESSES
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
483,7 → 482,7
end process core_reg_proc;
 
--=============================================================================================
-- RTL combinatorial LOGIC PROCESSES
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
496,10 → 495,12
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
-- slave select
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
506,6 → 507,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy'
-- stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
512,6 → 515,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
-- send bit out and shif bit in
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
519,6 → 524,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
-- raise data prefetch request
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
525,6 → 532,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if wren
-- load next word or end transmission
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
540,15 → 549,17
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 =>
-- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
588,9 → 599,9
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted or commented-out after debug.
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6));
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
601,5 → 612,5
sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
 
end architecture RTL;
end architecture rtl;
 
/spi_master_slave/trunk/rtl/grp_debouncer.vhd
0,0 → 1,195
-----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
--
-- Create Date: 09:56:30 07/06/2011
-- Module Name: grp_debouncer - RTL
-- Project Name: basic functions
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is a generic multiple input debouncing circuit.
-- It handles multiple inputs, like mechanical switch inputs, and outputs a debounced, stable registered version of the inputs.
-- A 'new_data' one-cycle strobe is also available, to sync downstream logic.
--
-- CONCEPTUAL CIRCUIT
-- ==================
--
-- W
-- /----------------/----------------\
-- | |
-- | |
-- | ______ ______ | _____
-- | W | | W |fdr | W | W |cmp \
-- \----/---| +1 |---/----| |--/--+----/----| \
-- | | | | | \
-- ------ | | \ |
-- | | | = |-----\
-- |> R | / | |
-- ---+-- | / |
-- | CNT_VAL---| / |
-- | |____/ |
-- | |
-- \------------\ |
-- | |
-- N ____ | |
-- /-------/---)) \ ____ | |
-- | ))XOR |-----) \ | |
-- | /------))___/ )OR |-----/ |
-- | | /---)___/ |
-- | | | |
-- | | \----------\ |
-- | | N | |
-- | \--------/-----------\ +----------------------+-----------\
-- | | | |
-- \---\ | | |
-- ______ | ______ | | ______ |
-- | fd | | | fd | | | |fde | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o]
-- N | | N N | | N | | | | N | N |
-- | | | | | \---|CE | | |
-- | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____
-- ------ ------ | ------ | N ____ \-----| \
-- | \----/----)) \ |AND |-----------[strb_o]
-- | ))XOR |-------|___/
-- \--------------------------/----))___/
-- N
--
--
-- PIPELINE LOGIC
-- ==============
--
-- This debouncer circuit detects edges in an input signal, and waits the signal to stabilize for the designated time
-- before transferring the stable signal to the registered output.
-- A one-clock-cyle strobe is pulsed at the output to signalize a new data available.
-- The core clock should be the system clock, to optimize use of global clock resources.
--
-- GROUP DEBOUNCING
-- ================
--
-- A change in state in any bit in the input word causes reload of the delay counter, and the output word is updated only
-- when all bits are stable for the specified period. Therefore, the grouping of signals and delay selection should match
-- behaviour of the selected signals.
--
-- RESOURCES USED
-- ==============
--
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers.
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
--
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
--
-- Copyright (C) 2011 Authors
-- --------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.opencores.org/lgpl.shtml
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-- The circuit can easily be extended to have a signature of which inputs changed at the data out port.
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
entity grp_debouncer is
Generic (
N : positive := 8; -- input bus width
CNT_VAL : positive := 10000); -- clock counts for debounce period
Port (
clk_i : in std_logic := 'X'; -- system clock
data_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- noisy input data
data_o : out std_logic_vector (N-1 downto 0); -- registered stable output data
strb_o : out std_logic -- strobe for new data available
);
end grp_debouncer;
 
architecture rtl of grp_debouncer is
-- datapath pipeline
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output
signal dat_strb : std_logic := '0'; -- data transfer strobe
signal dat_diff : std_logic := '0'; -- edge detector
-- debounce counter
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter
signal cnt_next : integer range CNT_VAL downto 0 := 0; -- combinatorial signal
begin
 
--=============================================================================================
-- DEBOUNCE COUNTER LOGIC
--=============================================================================================
-- This counter is implemented as a up-counter with reset and final count detection via compare,
-- instead of a down-counter with preset and final count detection via nonzero detection.
-- This is better for Spartan-6 and Virtex-6 CLB architecture, because it uses less control sets.
--
-- cnt_reg register transfer logic
cnt_reg_proc: process (clk_i) is
begin
if clk_i'event and clk_i = '1' then
cnt_reg <= cnt_next;
end if;
end process cnt_reg_proc;
-- cnt_next combinatorial logic
cnt_next_proc: cnt_next <= 0 when dat_diff = '1' or dat_strb = '1' else cnt_reg + 1;
-- final count combinatorial logic
final_cnt_proc: dat_strb <= '1' when cnt_reg = CNT_VAL else '0';
 
--=============================================================================================
-- DATAPATH SIGNAL PIPELINE
--=============================================================================================
-- input pipeline logic
pipeline_proc: process (clk_i) is
begin
-- edge detection pipeline
if clk_i'event and clk_i = '1' then
reg_A <= data_i;
reg_B <= reg_A;
end if;
if clk_i'event and clk_i = '1' then
if dat_strb = '1' then
reg_out <= reg_B;
end if;
end if;
end process pipeline_proc;
-- edge detector
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0';
--=============================================================================================
-- OUTPUT LOGIC
--=============================================================================================
-- new data strobe detection
strb_o_proc: strb_o <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0';
-- connect output ports
data_o_proc: data_o <= reg_out;
end rtl;
 
/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd
28,6 → 28,7
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
-- 6.25MHz, 1MHz and 500kHz
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
--
--
----------------------------------------------------------------------------------
50,6 → 51,8
--- output LEDs ----
led_o : out std_logic_vector (7 downto 0); -- output leds
--- debug outputs ---
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins
);
end spi_master_atlys_top;
80,14 → 83,28
--=============================================================================================
-- Type definitions
--=============================================================================================
type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch,
st_send_spi_data, st_wait_spi_ack );
type fsm_master_write_state_type is
(st_reset, st_wait_spi_idle, st_wait_new_switch, st_send_spi_data_sw, st_wait_spi_ack_sw,
st_send_spi_data_1, st_wait_spi_ack_1, st_wait_spi_di_req_2, st_wait_spi_ack_2,
st_wait_spi_di_req_3, st_wait_spi_ack_3);
 
type fsm_slave_write_state_type is
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2,
st_wait_spi_di_req_3, st_wait_spi_ack_3, st_wait_spi_end);
 
type fsm_slave_read_state_type is
(st_reset, st_wait_spi_do_valid_1, st_wait_spi_n_do_valid_1, st_wait_spi_do_valid_2,
st_wait_spi_n_do_valid_2, st_wait_spi_do_valid_3, st_wait_spi_n_do_valid_3);
 
--=============================================================================================
-- Signals for state machine control
--=============================================================================================
signal state_reg : fsm_state_type := st_reset;
signal state_next : fsm_state_type := st_reset;
signal m_wr_st_reg : fsm_master_write_state_type := st_reset;
signal m_wr_st_next : fsm_master_write_state_type := st_reset;
signal s_wr_st_reg : fsm_slave_write_state_type := st_reset;
signal s_wr_st_next : fsm_slave_write_state_type := st_reset;
signal s_rd_st_reg : fsm_slave_read_state_type := st_reset;
signal s_rd_st_next : fsm_slave_read_state_type := st_reset;
 
--=============================================================================================
-- Signals for internal operation
124,10 → 141,7
signal spi_di_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_m : std_logic_vector (N-1 downto 0);
-- spi master port debug flags
signal spi_rx_bit_m : std_logic;
signal spi_wr_ack_m : std_logic;
signal state_dbg_m : std_logic_vector (5 downto 0);
-- spi slave port control signals
signal spi_wren_reg_s : std_logic := '1';
signal spi_wren_next_s : std_logic := '1';
138,14 → 152,20
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_s : std_logic_vector (N-1 downto 0);
-- spi slave port debug flags
signal spi_wr_ack_s : std_logic;
signal spi_rx_bit_s : std_logic;
signal spi_wr_ack_s : std_logic;
signal state_dbg_s : std_logic_vector (5 downto 0);
-- slave data output regs --
signal s_do_1_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_1_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_next : std_logic_vector (N-1 downto 0) := (others => '0');
-- other signals
signal clear : std_logic := '0';
-- debug output signals
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0');
signal leds_reg : std_logic_vector (7 downto 0);
signal leds_next : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
begin
 
152,9 → 172,7
--=============================================================================================
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
--=============================================================================================
-- spi master port:
-- receives parallel data from the slide switches, transmits to slave port.
-- receives serial data from slave port, sends to 8bit parallel debug port.
-- spi master port: data and control signals driven by the master fsm
Inst_spi_master_port: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
164,63 → 182,34
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso,
spi_miso_i => spi_miso, -- driven by the spi slave
di_req_o => spi_di_req_m,
di_i => spi_di_reg_m,
wren_i => spi_wren_reg_m,
wr_ack_o => spi_wr_ack_m,
do_valid_o => spi_do_valid_m,
do_o => spi_do_m,
do_o => spi_do_m
------------ debug pins ------------
-- rx_bit_reg_o => spi_rx_bit_m,
-- state_dbg_o => state_dbg_m, -- monitor internal master state register
-- sck_ena_o => sck_ena_m, -- monitor internal sck_ena register
-- wren_o => spi_wren_o,
wr_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port
);
 
-- state_dbg_o(3 downto 0) <= state_dbg_m(3 downto 0); -- connect master state debug port
-- sck_ena_o <= sck_ena_m; -- sck_ena debug port
-- spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port
 
-- spi slave port
-- receives parallel data from the pushbuttons, transmits to master port.
-- receives serial data from master port, sends to the 8 LEDs.
-- spi slave port: data and control signals driven by the slave fsm
Inst_spi_slave_port: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3)
port map(
clk_i => gclk_i,
spi_ssel_i => spi_ssel, -- generated by the spi master
spi_sck_i => spi_sck, -- generated by the spi master
spi_mosi_i => spi_mosi,
spi_ssel_i => spi_ssel, -- driven by the spi master
spi_sck_i => spi_sck, -- driven by the spi master
spi_mosi_i => spi_mosi, -- driven by the spi master
spi_miso_o => spi_miso,
di_req_o => spi_di_req_s,
di_i => spi_di_reg_s,
wren_i => spi_wren_reg_s,
wr_ack_o => spi_wr_ack_s,
do_valid_o => spi_do_valid_s,
do_o => spi_do_s,
do_o => spi_do_s
------------ debug pins ------------
state_dbg_o => state_dbg_s, -- monitor internal state register
rx_bit_next_o => spi_rx_bit_s,
wr_ack_o => dbg(5),
do_transfer_o => dbg(4)
);
 
-- connect debug port pins to slave instance interface signals
dbg(7) <= spi_rx_bit_s;
dbg(6) <= spi_wren_reg_s;
dbg(3) <= spi_do_valid_s;
dbg(2) <= spi_di_req_s;
dbg(1) <= '0';
dbg(0) <= '0';
 
dbg(11 downto 8) <= state_dbg_s(3 downto 0);-- connect state register
spi_di_reg_s(7) <= btn_data(btLEFT); -- get the slave transmit data from pushbuttons
spi_di_reg_s(6) <= btn_data(btCENTER);
spi_di_reg_s(5 downto 1) <= B"10101";
spi_di_reg_s(0) <= btn_data(btRIGHT);
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data
 
-- debounce for the input switches, with new data strobe output
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 8, CNT_VAL => 20000) -- debounce 8 inputs with 200 us settling time
258,10 → 247,11
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- The clock generation block derives 3 internal clocks, divided down from the 100MHz input clock
-- core clock,
-- spi 2x base clock,
-- fsm clock,
-- All registers are clocked directly from the 100MHz system clock.
-- The clock generation block derives 2 clock enable signals, divided down from the 100MHz input
-- clock.
-- input sample clock enable,
-- fsm clock enable,
-----------------------------------------------------------------------------------------------
-- generate the sampling clock enable from the 100MHz board input clock
samp_ce_gen_proc: process (gclk_i) is
269,7 → 259,7
begin
if gclk_i'event and gclk_i = '1' then
if clk_cnt = SAMP_CE_DIV-1 then
samp_ce <= '1';
samp_ce <= '1'; -- generate a single pulse every SAMP_CE_DIV clocks
clk_cnt := 0;
else
samp_ce <= '0';
283,7 → 273,7
begin
if gclk_i'event and gclk_i = '1' then
if clk_cnt = FSM_CE_DIV-1 then
fsm_ce <= '1';
fsm_ce <= '1'; -- generate a single pulse every FSM_CE_DIV clocks
clk_cnt := 0;
else
fsm_ce <= '0';
301,7 → 291,7
if gclk_i'event and gclk_i = '1' then
if samp_ce = '1' then
clear <= btn_data(btUP); -- clear is button UP
leds_reg <= spi_do_s; -- update LEDs with spi_slave received data
leds_reg <= leds_next; -- update LEDs with spi_slave received data
end if;
end if;
end process samp_inputs_proc;
309,22 → 299,35
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
-- fsm state and data registers: synchronous to the system clock
fsm_reg_proc : process (gclk_i) is
begin
-- FFD registers clocked on rising edge and cleared on sync 'clear'
if gclk_i'event and gclk_i = '1' then
if clear = '1' then -- sync reset
state_reg <= st_reset; -- only provide local reset for the state register
if clear = '1' then -- sync reset
m_wr_st_reg <= st_reset; -- only provide local reset for the state registers
else
if fsm_ce = '1' then
state_reg <= state_next; -- state register
m_wr_st_reg <= m_wr_st_next; -- master write state register update
end if;
end if;
end if;
-- FFD registers clocked on rising edge and cleared on ssel = '1'
if gclk_i'event and gclk_i = '1' then
if spi_ssel = '1' then -- sync reset
s_wr_st_reg <= st_reset; -- only provide local reset for the state registers
s_rd_st_reg <= st_reset;
else
if fsm_ce = '1' then
s_wr_st_reg <= s_wr_st_next; -- slave write state register update
s_rd_st_reg <= s_rd_st_next; -- slave read state register update
end if;
end if;
end if;
-- FFD registers clocked on rising edge, with no reset
if gclk_i'event and gclk_i = '1' then
if fsm_ce = '1' then
--------- master write fsm signals -----------
spi_wren_reg_m <= spi_wren_next_m;
spi_di_reg_m <= spi_di_next_m;
spi_rst_reg <= spi_rst_next;
331,6 → 334,13
spi_ssel_reg <= spi_ssel;
sw_reg <= sw_next;
btn_reg <= btn_next;
--------- slave write fsm signals -----------
spi_wren_reg_s <= spi_wren_next_s;
spi_di_reg_s <= spi_di_next_s;
--------- slave read fsm signals -----------
s_do_1_reg <= s_do_1_next;
s_do_2_reg <= s_do_2_next;
s_do_3_reg <= s_do_3_next;
end if;
end if;
end process fsm_reg_proc;
339,14 → 349,15
-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES
--=============================================================================================
-- edge detector for new switch data
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for difference
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for edge
 
-- edge detector for new button data
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for difference
-- fsm state and combinatorial logic
-- the sequencer will wait for a new switch combination, and send the switch data to the spi port
fsm_combi_proc: process ( state_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, -- spi_di_reg_s,
spi_wren_reg_s, spi_ssel_reg, spi_rst_reg, sw_data,
sw_reg, new_switch, btn_data, btn_reg, new_button) is
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for edge
 
-- master port fsm state and combinatorial logic
fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m,
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg,
new_button) is
begin
spi_rst_next <= spi_rst_reg;
spi_di_next_m <= spi_di_reg_m;
353,49 → 364,214
spi_wren_next_m <= spi_wren_reg_m;
sw_next <= sw_reg;
btn_next <= btn_reg;
state_next <= state_reg;
case state_reg is
m_wr_st_next <= m_wr_st_reg;
case m_wr_st_reg is
when st_reset =>
spi_rst_next <= '1'; -- place spi interface on reset
spi_di_next_m <= (others => '0'); -- clear spi data port
spi_di_next_s <= (others => '0'); -- clear spi data port
spi_wren_next_m <= '0'; -- deassert write enable
spi_wren_next_s <= '0'; -- deassert write enable
state_next <= st_wait_spi_idle;
m_wr_st_next <= st_wait_spi_idle;
when st_wait_spi_idle =>
spi_wren_next_m <= '0'; -- remove write strobe on next clock
if spi_ssel_reg = '1' then
spi_rst_next <= '0'; -- remove reset when interface is idle
state_next <= st_wait_new_switch;
m_wr_st_next <= st_wait_new_switch;
end if;
 
when st_wait_new_switch =>
if new_switch = '1' then -- wait for new stable switch data
sw_next <= sw_data; -- load new switch data (end the mismatch condition)
state_next <= st_send_spi_data;
m_wr_st_next <= st_send_spi_data_sw;
elsif new_button = '1' then
btn_next <= btn_data; -- load new button data (end the mismatch condition)
if btn_data /= B"000001" then
state_next <= st_send_spi_data;
if btn_data(btUP) = '0' then
if btn_data(btDOWN) = '1' then
m_wr_st_next <= st_send_spi_data_sw;
elsif btn_data(btLEFT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btCENTER) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btRIGHT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
end if;
end if;
end if;
when st_send_spi_data =>
when st_send_spi_data_sw =>
spi_di_next_m <= sw_reg; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
state_next <= st_wait_spi_ack;
m_wr_st_next <= st_wait_spi_ack_sw;
 
when st_wait_spi_ack => -- the actual write happens on this state
spi_di_next_m <= sw_reg; -- load switch register to the spi port
spi_wren_next_m <= '0'; -- remove write strobe on next clock
state_next <= st_wait_spi_idle;
when st_wait_spi_ack_sw => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_send_spi_data_1 =>
spi_di_next_m <= X"A1"; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
m_wr_st_next <= st_wait_spi_ack_1;
 
when st_wait_spi_ack_1 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_wait_spi_di_req_2 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A2";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_2;
end if;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A3";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_3;
end if;
 
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_idle; -- wait transmission end
end if;
when others =>
state_next <= st_reset; -- state st_reset is safe state
m_wr_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_combi_proc;
end process fsm_m_wr_combi_proc;
 
-- slave port fsm state and combinatorial logic
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s,
spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is
begin
spi_wren_next_s <= spi_wren_reg_s;
spi_di_next_s <= spi_di_reg_s;
s_wr_st_next <= s_wr_st_reg;
case s_wr_st_reg is
when st_reset =>
spi_di_next_s <= X"D1"; -- write first data word
spi_wren_next_s <= '1'; -- set write enable
s_wr_st_next <= st_wait_spi_start;
when st_wait_spi_start =>
if spi_ssel_reg = '0' then -- wait for slave select
spi_wren_next_s <= '0'; -- remove write enable
s_wr_st_next <= st_wait_spi_di_req_2;
end if;
 
when st_wait_spi_di_req_2 =>
if spi_di_req_s = '1' then
spi_di_next_s <= X"D2";
spi_wren_next_s <= '1';
s_wr_st_next <= st_wait_spi_ack_2;
end if;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_s = '1' then
spi_di_next_s <= X"D3";
spi_wren_next_s <= '1';
s_wr_st_next <= st_wait_spi_ack_3;
end if;
 
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_end; -- wait transmission end
end if;
when st_wait_spi_end => -- wait interface to be deselected
if spi_ssel_reg = '1' then
s_wr_st_next <= st_reset; -- wait transmission start
end if;
when others =>
s_wr_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_wr_combi_proc;
 
-- slave port fsm state and combinatorial logic
fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
s_do_1_next <= s_do_1_reg;
s_do_2_next <= s_do_2_reg;
s_do_3_next <= s_do_3_reg;
s_rd_st_next <= s_rd_st_reg;
case s_rd_st_reg is
when st_reset =>
s_rd_st_next <= st_wait_spi_do_valid_1;
when st_wait_spi_do_valid_1 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_1_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_1;
end if;
 
when st_wait_spi_n_do_valid_1 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_2;
end if;
when st_wait_spi_do_valid_2 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_2_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_2;
end if;
 
when st_wait_spi_n_do_valid_2 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_3;
end if;
when st_wait_spi_do_valid_3 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_3_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_3;
end if;
when st_wait_spi_n_do_valid_3 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_reset;
end if;
 
when others =>
s_rd_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_rd_combi_proc;
 
leds_combi_proc: process (btn_data, leds_reg, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
leds_next <= leds_reg;
if btn_data(btRIGHT) = '1' then
leds_next <= s_do_3_reg;
elsif btn_data(btCENTER) = '1' then
leds_next <= s_do_2_reg;
elsif btn_data(btLEFT) = '1' then
leds_next <= s_do_1_reg;
elsif btn_data(btDOWN) = '1' then
leds_next <= s_do_1_reg;
end if;
end process leds_combi_proc;
 
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
405,7 → 581,7
spi_mosi_o_proc: spi_mosi_o <= spi_mosi;
spi_miso_o_proc: spi_miso_o <= spi_miso;
-- connect leds_reg signal to LED outputs
led_o_proc: led_o <= leds_reg;
led_o_proc: led_o <= leds_reg;
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
412,6 → 588,18
--=============================================================================================
-- connect the debug vector outputs
dbg_o_proc: dbg_o <= dbg;
-- connect debug port pins to spi ports instances interface signals
-- master signals mapped on dbg
dbg(11) <= spi_wren_reg_m;
dbg(10) <= spi_wr_ack_m;
dbg(9) <= spi_di_req_m;
dbg(8) <= spi_do_valid_m;
-- slave signals mapped on dbg
dbg(7) <= spi_wren_reg_s;
dbg(6) <= spi_wr_ack_s;
dbg(5) <= spi_di_req_s;
dbg(4) <= spi_do_valid_s;
 
end behavioral;
 
/spi_master_slave/trunk/syn/spi_master.vhd
13,6 → 13,7
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
143,6 → 144,8
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
193,7 → 196,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
206,7 → 209,7
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture RTL of spi_master is
architecture rtl of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
234,14 → 237,14
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic := '0';
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
251,8 → 254,8
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
309,7 → 312,7
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources.
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc: process (sclk_i) is
357,7 → 360,6
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
381,7 → 383,8
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
 
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
388,10 → 391,6
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
--
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
-- REDUCED DEMAND ON MISO SETUP TIME.
--
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
450,7 → 449,7
end process in_transfer_proc;
 
--=============================================================================================
-- RTL REGISTER PROCESSES
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
483,7 → 482,7
end process core_reg_proc;
 
--=============================================================================================
-- RTL combinatorial LOGIC PROCESSES
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
496,10 → 495,12
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(N-1); -- default to avoid latch inference
state_next <= state_reg; -- next state
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
case state_reg is
when (N+1) => -- this state is to enable SSEL before SCK
-- slave select
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
506,6 → 507,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy'
-- stretch do_valid
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
512,6 → 515,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) => -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
-- send bit out and shif bit in
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
519,6 → 524,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 2 => -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
-- raise data prefetch request
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
525,6 → 532,8
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if wren
-- load next word or end transmission
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
540,15 → 549,17
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 =>
-- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if wren = '1' then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N+1; -- start from idle: let one cycle for SSEL settling
spi_mosi_o <= di_reg(N-1); -- special case: shift out first tx bit from the MSb (look ahead)
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
588,9 → 599,9
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted or commented-out after debug.
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6));
state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg;
601,5 → 612,5
sck_ena_o_proc: sck_ena_o <= sck_ena_reg;
sck_ena_ce_o_proc: sck_ena_ce_o <= sck_ena_ce;
 
end architecture RTL;
end architecture rtl;
 
/spi_master_slave/trunk/syn/ATLYS_04.SET
0,0 → 1,621
:SELECT:DALL 0
:ACQUIRE:STOPAFTER RUNSTOP
:ACQUIRE:STATE 1
:ACQUIRE:MODE SAMPLE
:ACQUIRE:NUMENV INFINITE
:ACQUIRE:NUMAVG 128
:ACQUIRE:MAGNIVU 0
:HEADER 0
:LOCK NONE
:VERBOSE 1
:MESSAGE:SHOW ""
:MESSAGE:BOX 92,39,92,49
:MESSAGE:STATE 0
:ALIAS:STATE 0
:DISPLAY:COLOR:PALETTE NORMAL
:DISPLAY:STYLE:DOTSONLY 0
:DISPLAY:PERSISTENCE 0.0E+0
:DISPLAY:CLOCK TIMEONLY
:DISPLAY:FORMAT YT
:DISPLAY:GRATICULE FULL
:DISPLAY:INTENSITY:WAVEFORM 40
:DISPLAY:INTENSITY:GRATICULE 20
:DISPLAY:INTENSITY:BACKLIGHT MEDIUM
:DISPLAY:INTENSITY:GLITCH 0
:DISPLAY:GLITCH 0
:DISPLAY:DIGITAL:HEIGHT MEDIUM
:FILTERVU:FREQUENCY 100000000
:HARDCOPY:INKSAVER 1
:HARDCOPY:LAYOUT LANDSCAPE
:HARDCOPY:PREVIEW 0
:PICTBRIDGE:PAPERSIZE DEFLT
:PICTBRIDGE:IMAGESIZE DEFLT
:PICTBRIDGE:PAPERTYPE DEFLT
:PICTBRIDGE:PRINTQUAL DEFLT
:PICTBRIDGE:DATEPRINT DEFLT
:PICTBRIDGE:IDPRINT OFF
:SAVE:IMAGE:LAYOUT LANDSCAPE
:SAVE:IMAGE:FILEFORMAT BMP
:SAVE:IMAGE:INKSAVER 0
:SAVE:WAVEFORM:FILEFORMAT SPREADSHEET
:SAVE:WAVEFORM:GATING NONE
:SAVE:WAVEFORM:SPREADSHEET:RESOLUTION FULL
:SAVE:ASSIGN:TYPE IMAGE
:D0:THRESHOLD 1.2600
:D1:THRESHOLD 1.2600
:D2:THRESHOLD 1.2600
:D3:THRESHOLD 1.2600
:D4:THRESHOLD 1.2600
:D5:THRESHOLD 1.2600
:D6:THRESHOLD 1.2600
:D7:THRESHOLD 1.2600
:D8:THRESHOLD 1.2600
:D9:THRESHOLD 1.2600
:D10:THRESHOLD 1.2600
:D11:THRESHOLD 1.2600
:D12:THRESHOLD 1.2600
:D13:THRESHOLD 1.2600
:D14:THRESHOLD 1.2600
:D15:THRESHOLD 1.2600
:D0:POSITION 60.0000E-3
:D1:POSITION 60.0000E-3
:D2:POSITION -3.9400
:D3:POSITION -3.4400
:D4:POSITION -2.4400
:D5:POSITION -1.9400
:D6:POSITION -1.4400
:D7:POSITION -940.0000E-3
:D8:POSITION -440.0000E-3
:D9:POSITION 60.0000E-3
:D10:POSITION 560.0000E-3
:D11:POSITION 1.0600
:D12:POSITION 1.5600
:D13:POSITION 2.0600
:D14:POSITION 2.5600
:D15:POSITION 3.0600
:D0:LABEL ""
:D1:LABEL ""
:D2:LABEL ""
:D3:LABEL ""
:D4:LABEL "s_do_valid"
:D5:LABEL "s_di_req"
:D6:LABEL "s_wr_ack"
:D7:LABEL "s_wren"
:D8:LABEL "m_do_valid"
:D9:LABEL "m_di_req"
:D10:LABEL "m_wr_ack"
:D11:LABEL "m_wren"
:D12:LABEL "MISO"
:D13:LABEL "MOSI"
:D14:LABEL "SCK"
:D15:LABEL "SSEL"
:HORIZONTAL:POSITION 50.0000
:HORIZONTAL:SCALE 100.0000E-9
:HORIZONTAL:RECORDLENGTH 1000000
:HORIZONTAL:DELAY:MODE 1
:HORIZONTAL:DELAY:TIME 263.0000E-9
:SELECT:CH1 0
:SELECT:CH2 0
:SELECT:CH3 0
:SELECT:CH4 0
:SELECT:MATH 0
:SELECT:REF1 0
:SELECT:REF2 0
:SELECT:D0 0
:SELECT:D1 0
:SELECT:D2 0
:SELECT:D3 0
:SELECT:D4 1
:SELECT:D5 1
:SELECT:D6 1
:SELECT:D7 1
:SELECT:D8 1
:SELECT:D9 1
:SELECT:D10 1
:SELECT:D11 1
:SELECT:D12 1
:SELECT:D13 1
:SELECT:D14 1
:SELECT:D15 1
:SELECT:BUS1 0
:SELECT:BUS2 0
:SELECT:CONTROL D15
:CH1:AMPSVIAVOLTS:ENABLE 0
:CH2:AMPSVIAVOLTS:ENABLE 0
:CH3:AMPSVIAVOLTS:ENABLE 0
:CH4:AMPSVIAVOLTS:ENABLE 0
:CH1:AMPSVIAVOLTS:FACTOR 10.0000
:CH2:AMPSVIAVOLTS:FACTOR 10.0000
:CH3:AMPSVIAVOLTS:FACTOR 10.0000
:CH4:AMPSVIAVOLTS:FACTOR 10.0000
:CH1:PROBE:GAIN 100.0000E-3
:CH2:PROBE:GAIN 100.0000E-3
:CH3:PROBE:GAIN 100.0000E-3
:CH4:PROBE:GAIN 100.0000E-3
:CH1:PROBE:FORCEDRANGE 0.0E+0
:CH2:PROBE:FORCEDRANGE 0.0E+0
:CH3:PROBE:FORCEDRANGE 0.0E+0
:CH4:PROBE:FORCEDRANGE 0.0E+0
:CH1:BANDWIDTH 100.0000E+6
:CH2:BANDWIDTH 100.0000E+6
:CH3:BANDWIDTH 100.0000E+6
:CH4:BANDWIDTH 100.0000E+6
:CH1:COUPLING DC
:CH2:COUPLING DC
:CH3:COUPLING DC
:CH4:COUPLING DC
:CH1:DESKEW 0.0E+0
:CH2:DESKEW 0.0E+0
:CH3:DESKEW 0.0E+0
:CH4:DESKEW 0.0E+0
:CH1:OFFSET 143.2000E-3
:CH2:OFFSET 0.0E+0
:CH3:OFFSET 0.0E+0
:CH4:OFFSET 0.0E+0
:CH1:INVERT 0
:CH2:INVERT 0
:CH3:INVERT 0
:CH4:INVERT 0
:CH1:POSITION 0.0E+0
:CH2:POSITION 0.0E+0
:CH3:POSITION 0.0E+0
:CH4:POSITION 0.0E+0
:CH1:SCALE 2.0000
:CH2:SCALE 1.0000
:CH3:SCALE 1.0000
:CH4:SCALE 1.0000
:CH1:YUNITS "V"
:CH2:YUNITS "V"
:CH3:YUNITS "V"
:CH4:YUNITS "V"
:CH1:TERMINATION 1.0000E+6
:CH2:TERMINATION 1.0000E+6
:CH3:TERMINATION 1.0000E+6
:CH4:TERMINATION 1.0000E+6
:CH1:LABEL "\x0eACK"
:CH2:LABEL ""
:CH3:LABEL ""
:CH4:LABEL ""
:AUXIN:PROBE:GAIN 100.0000E-3
:AUXIN:PROBE:FORCEDRANGE 0.0E+0
:REF1:VERTICAL:POSITION 0.0E+0
:REF2:VERTICAL:POSITION 0.0E+0
:REF1:VERTICAL:SCALE 100.0000E-3
:REF2:VERTICAL:SCALE 100.0000E-3
:REF1:HORIZONTAL:DELAY:TIME -20.0000E-6
:REF2:HORIZONTAL:DELAY:TIME -20.0000E-6
:REF1:HORIZONTAL:SCALE 4.0000E-6
:REF2:HORIZONTAL:SCALE 4.0000E-6
:MATH:TYPE DUAL
:MATH:DEFINE "CH1+CH2"
:MATH:VERTICAL:SCALE 100.0000E-3
:MATH:VERTICAL:POSITION 0.0E+0
:MATH:VERTICAL:UNITS "V"
:MATH:HORIZONTAL:SCALE 10.0000E-6
:MATH:HORIZONTAL:POSITION 50.0200
:MATH:HORIZONTAL:UNITS "s"
:MATH:SPECTRAL:MAG DB
:MATH:SPECTRAL:WINDOW HANNING
:MATH:SPECTRAL:GATING:INDICATORS 0
:MATH:LABEL ""
:TRIGGER:A:MODE NORMAL
:TRIGGER:A:TYPE EDGE
:TRIGGER:A:LEVEL 1.2600
:TRIGGER:A:LEVEL:CH1 160.0000E-3
:TRIGGER:A:LEVEL:CH2 0.0E+0
:TRIGGER:A:LEVEL:CH3 0.0E+0
:TRIGGER:A:LEVEL:CH4 0.0E+0
:TRIGGER:A:LEVEL:AUXIN 0.0E+0
:TRIGGER:A:LEVEL:D0 1.2600
:TRIGGER:A:LEVEL:D1 1.2600
:TRIGGER:A:LEVEL:D2 1.2600
:TRIGGER:A:LEVEL:D3 1.2600
:TRIGGER:A:LEVEL:D4 1.2600
:TRIGGER:A:LEVEL:D5 1.2600
:TRIGGER:A:LEVEL:D6 1.2600
:TRIGGER:A:LEVEL:D7 1.2600
:TRIGGER:A:LEVEL:D8 1.2600
:TRIGGER:A:LEVEL:D9 1.2600
:TRIGGER:A:LEVEL:D10 1.2600
:TRIGGER:A:LEVEL:D11 1.2600
:TRIGGER:A:LEVEL:D12 1.2600
:TRIGGER:A:LEVEL:D13 1.2600
:TRIGGER:A:LEVEL:D14 1.2600
:TRIGGER:A:LEVEL:D15 1.2600
:TRIGGER:A:UPPERTHRESHOLD:CH1 240.0000E-3
:TRIGGER:A:UPPERTHRESHOLD:CH2 1.4000
:TRIGGER:A:UPPERTHRESHOLD:CH3 1.4000
:TRIGGER:A:UPPERTHRESHOLD:CH4 1.4000
:TRIGGER:A:LOWERTHRESHOLD:CH1 160.0000E-3
:TRIGGER:A:LOWERTHRESHOLD:CH2 0.0E+0
:TRIGGER:A:LOWERTHRESHOLD:CH3 0.0E+0
:TRIGGER:A:LOWERTHRESHOLD:CH4 0.0E+0
:TRIGGER:A:LOWERTHRESHOLD:EXT 0.0E+0
:TRIGGER:A:LOWERTHRESHOLD:D0 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D1 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D2 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D3 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D4 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D5 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D6 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D7 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D8 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D9 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D10 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D11 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D12 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D13 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D14 1.2600
:TRIGGER:A:LOWERTHRESHOLD:D15 1.2600
:TRIGGER:A:HOLDOFF:TIME 337.4240E-6
:TRIGGER:A:EDGE:SOURCE D15
:TRIGGER:A:EDGE:COUPLING DC
:TRIGGER:A:EDGE:SLOPE FALL
:TRIGGER:A:LOGIC:CLASS LOGIC
:TRIGGER:A:LOGIC:FUNCTION AND
:TRIGGER:A:LOGIC:THRESHOLD:CH1 160.0000E-3
:TRIGGER:A:LOGIC:THRESHOLD:CH2 0.0E+0
:TRIGGER:A:LOGIC:THRESHOLD:CH3 0.0E+0
:TRIGGER:A:LOGIC:THRESHOLD:CH4 0.0E+0
:TRIGGER:A:LOGIC:THRESHOLD:D0 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D1 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D2 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D3 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D4 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D5 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D6 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D7 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D8 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D9 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D10 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D11 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D12 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D13 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D14 1.2600
:TRIGGER:A:LOGIC:THRESHOLD:D15 1.2600
:TRIGGER:A:LOGIC:INPUT:CH1 X
:TRIGGER:A:LOGIC:INPUT:CH2 X
:TRIGGER:A:LOGIC:INPUT:CH3 X
:TRIGGER:A:LOGIC:INPUT:CH4 X
:TRIGGER:A:LOGIC:INPUT:CLOCK:SOURCE NONE
:TRIGGER:A:LOGIC:INPUT:CLOCK:EDGE RISE
:TRIGGER:A:LOGIC:INPUT:D0 X
:TRIGGER:A:LOGIC:INPUT:D1 X
:TRIGGER:A:LOGIC:INPUT:D2 X
:TRIGGER:A:LOGIC:INPUT:D3 X
:TRIGGER:A:LOGIC:INPUT:D4 X
:TRIGGER:A:LOGIC:INPUT:D5 X
:TRIGGER:A:LOGIC:INPUT:D6 X
:TRIGGER:A:LOGIC:INPUT:D7 X
:TRIGGER:A:LOGIC:INPUT:D8 X
:TRIGGER:A:LOGIC:INPUT:D9 X
:TRIGGER:A:LOGIC:INPUT:D10 X
:TRIGGER:A:LOGIC:INPUT:D11 X
:TRIGGER:A:LOGIC:INPUT:D12 X
:TRIGGER:A:LOGIC:INPUT:D13 X
:TRIGGER:A:LOGIC:INPUT:D14 X
:TRIGGER:A:LOGIC:INPUT:D15 X
:TRIGGER:A:LOGIC:PATTERN:WHEN TRUE
:TRIGGER:A:LOGIC:PATTERN:WHEN:LESSLIMIT 8.0000E-9
:TRIGGER:A:LOGIC:PATTERN:WHEN:MORELIMIT 8.0000E-9
:TRIGGER:A:LOGIC:PATTERN:DELTATIME 8.0000E-9
:TRIGGER:A:SETHOLD:CLOCK:SOURCE CH1
:TRIGGER:A:SETHOLD:CLOCK:EDGE RISE
:TRIGGER:A:SETHOLD:CLOCK:THRESHOLD 160.0000E-3
:TRIGGER:A:SETHOLD:DATA:SOURCE NONE
:TRIGGER:A:SETHOLD:DATA:THRESHOLD 9.9100E+37
:TRIGGER:A:SETHOLD:HOLDTIME 2.0000E-9
:TRIGGER:A:SETHOLD:SETTIME 2.0000E-9
:TRIGGER:A:SETHOLD:THRESHOLD:CH1 160.0000E-3
:TRIGGER:A:SETHOLD:THRESHOLD:CH2 0.0E+0
:TRIGGER:A:SETHOLD:THRESHOLD:CH3 0.0E+0
:TRIGGER:A:SETHOLD:THRESHOLD:CH4 0.0E+0
:TRIGGER:A:SETHOLD:THRESHOLD:D0 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D1 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D2 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D3 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D4 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D5 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D6 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D7 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D8 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D9 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D10 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D11 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D12 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D13 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D14 1.2600
:TRIGGER:A:SETHOLD:THRESHOLD:D15 1.2600
:TRIGGER:A:PULSE:CLASS WIDTH
:TRIGGER:A:PULSEWIDTH:POLARITY POSITIVE
:TRIGGER:A:PULSEWIDTH:WHEN MORETHAN
:TRIGGER:A:PULSEWIDTH:WIDTH 95.0340E-6
:TRIGGER:A:RUNT:POLARITY POSITIVE
:TRIGGER:A:RUNT:WHEN OCCURS
:TRIGGER:A:RUNT:WIDTH 95.0340E-6
:TRIGGER:A:TRANSITION:POLARITY POSITIVE
:TRIGGER:A:TRANSITION:WHEN SLOWER
:TRIGGER:A:TRANSITION:DELTATIME 95.0340E-6
:TRIGGER:A:VIDEO:STANDARD NTSC
:TRIGGER:A:VIDEO:SYNC ALLLINES
:TRIGGER:A:VIDEO:LINE 1
:TRIGGER:A:VIDEO:HOLDOFF:FIELD 0.0E+0
:TRIGGER:A:VIDEO:POLARITY POSITIVE
:TRIGGER:A:BUS:SOURCE B1
:TRIGGER:A:BUS:B1:RS232C:CONDITION TXSTART
:TRIGGER:A:BUS:B2:RS232C:CONDITION TXSTART
:TRIGGER:A:BUS:B1:RS232C:RX:DATA:SIZE 1
:TRIGGER:A:BUS:B2:RS232C:RX:DATA:SIZE 1
:TRIGGER:A:BUS:B1:RS232C:RX:DATA:VALUE "XXXXXXXX"
:TRIGGER:A:BUS:B2:RS232C:RX:DATA:VALUE "XXXXXXXX"
:TRIGGER:A:BUS:B1:RS232C:TX:DATA:SIZE 1
:TRIGGER:A:BUS:B2:RS232C:TX:DATA:SIZE 1
:TRIGGER:A:BUS:B1:RS232C:TX:DATA:VALUE "XXXXXXXX"
:TRIGGER:A:BUS:B2:RS232C:TX:DATA:VALUE "XXXXXXXX"
:TRIGGER:A:BUS:B1:PARALLEL:VALUE "X"
:TRIGGER:A:BUS:B2:PARALLEL:VALUE "XXXX"
:TRIGGER:EXTERNAL:PROBE 10.0000
:BUS:B1:RS232C:PARITY NONE
:BUS:B2:RS232C:PARITY NONE
:BUS:B1:RS232C:BITRATE 9600
:BUS:B2:RS232C:BITRATE 9600
:BUS:B1:RS232C:POLARITY NORMAL
:BUS:B2:RS232C:POLARITY NORMAL
:BUS:B1:RS232C:DATABITS 8
:BUS:B2:RS232C:DATABITS 8
:BUS:B1:RS232C:TX:SOURCE CH1
:BUS:B2:RS232C:TX:SOURCE CH1
:BUS:B1:RS232C:RX:SOURCE D12
:BUS:B2:RS232C:RX:SOURCE OFF
:BUS:B1:RS232C:DISPLAYMODE FRAME
:BUS:B2:RS232C:DISPLAYMODE FRAME
:BUS:B1:RS232C:DELIMITER LF
:BUS:B2:RS232C:DELIMITER LF
:BUS:B1:STATE 0
:BUS:B2:STATE 0
:BUS:B1:TYPE PARALLEL
:BUS:B2:TYPE PARALLEL
:BUS:B1:POSITION -2.5600
:BUS:B2:POSITION 600.0000E-3
:BUS:B1:DISPLAY:TYPE BUS
:BUS:B2:DISPLAY:TYPE BUS
:BUS:B1:DISPLAY:FORMAT HEXADECIMAL
:BUS:B2:DISPLAY:FORMAT HEXADECIMAL
:BUS:B1:LABEL "Parallel"
:BUS:B2:LABEL "ST_S"
:BUS:B1:PARALLEL:WIDTH 1
:BUS:B2:PARALLEL:WIDTH 4
:BUS:B1:PARALLEL:CLOCK:ISCLOCKED YES
:BUS:B2:PARALLEL:CLOCK:ISCLOCKED NO
:BUS:B1:PARALLEL:CLOCK:SOURCE D15
:BUS:B2:PARALLEL:CLOCK:SOURCE D15
:BUS:B1:PARALLEL:CLOCK:EDGE RISING
:BUS:B2:PARALLEL:CLOCK:EDGE RISING
:BUS:B1:PARALLEL:BIT0:SOURCE D0
:BUS:B1:PARALLEL:BIT1:SOURCE D1
:BUS:B1:PARALLEL:BIT2:SOURCE D2
:BUS:B1:PARALLEL:BIT3:SOURCE D3
:BUS:B1:PARALLEL:BIT4:SOURCE D4
:BUS:B1:PARALLEL:BIT5:SOURCE D5
:BUS:B1:PARALLEL:BIT6:SOURCE D6
:BUS:B1:PARALLEL:BIT7:SOURCE D7
:BUS:B1:PARALLEL:BIT8:SOURCE D8
:BUS:B1:PARALLEL:BIT9:SOURCE D9
:BUS:B1:PARALLEL:BIT10:SOURCE D10
:BUS:B1:PARALLEL:BIT11:SOURCE D11
:BUS:B1:PARALLEL:BIT12:SOURCE D12
:BUS:B1:PARALLEL:BIT13:SOURCE D13
:BUS:B1:PARALLEL:BIT14:SOURCE D14
:BUS:B1:PARALLEL:BIT15:SOURCE D15
:BUS:B1:PARALLEL:BIT16:SOURCE CH1
:BUS:B1:PARALLEL:BIT17:SOURCE CH2
:BUS:B1:PARALLEL:BIT18:SOURCE CH3
:BUS:B1:PARALLEL:BIT19:SOURCE CH4
:BUS:B2:PARALLEL:BIT0:SOURCE D8
:BUS:B2:PARALLEL:BIT1:SOURCE D9
:BUS:B2:PARALLEL:BIT2:SOURCE D10
:BUS:B2:PARALLEL:BIT3:SOURCE D11
:BUS:B2:PARALLEL:BIT4:SOURCE D10
:BUS:B2:PARALLEL:BIT5:SOURCE D11
:BUS:B2:PARALLEL:BIT6:SOURCE D6
:BUS:B2:PARALLEL:BIT7:SOURCE D7
:BUS:B2:PARALLEL:BIT8:SOURCE D8
:BUS:B2:PARALLEL:BIT9:SOURCE D9
:BUS:B2:PARALLEL:BIT10:SOURCE D10
:BUS:B2:PARALLEL:BIT11:SOURCE D11
:BUS:B2:PARALLEL:BIT12:SOURCE D12
:BUS:B2:PARALLEL:BIT13:SOURCE D13
:BUS:B2:PARALLEL:BIT14:SOURCE D14
:BUS:B2:PARALLEL:BIT15:SOURCE D15
:BUS:B2:PARALLEL:BIT16:SOURCE CH1
:BUS:B2:PARALLEL:BIT17:SOURCE CH2
:BUS:B2:PARALLEL:BIT18:SOURCE CH3
:BUS:B2:PARALLEL:BIT19:SOURCE CH4
:BUS:LOWERTHRESHOLD:CH1 160.0000E-3
:BUS:LOWERTHRESHOLD:CH2 0.0E+0
:BUS:LOWERTHRESHOLD:CH3 0.0E+0
:BUS:LOWERTHRESHOLD:CH4 0.0E+0
:BUS:UPPERTHRESHOLD:CH1 240.0000E-3
:BUS:UPPERTHRESHOLD:CH2 1.4000
:BUS:UPPERTHRESHOLD:CH3 1.4000
:BUS:UPPERTHRESHOLD:CH4 1.4000
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:CONDITION TXSTART
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:CONDITION TXSTART
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:RX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:RX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:RX:DATA:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:RX:DATA:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:TX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:TX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:TX:DATA:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:TX:DATA:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:PARALLEL:VALUE "X"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:PARALLEL:VALUE "XXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:SOURCE B1
:SEARCH:SEARCH1:TRIGGER:A:TYPE EDGE
:SEARCH:SEARCH1:TRIGGER:A:LEVEL 0.0E+0
:SEARCH:SEARCH1:TRIGGER:A:LEVEL:CH1 0.0E+0
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/spi_master_slave/trunk/syn/spi_master_scope_photos.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/spi_master_slave/trunk/syn/spi_master_atlys_test.vhd
36,6 → 36,10
spi_mosi_o : out std_logic;
spi_miso_o : out std_logic;
led_o : out std_logic_vector(7 downto 0);
s_do_o : out std_logic_vector (7 downto 0);
m_do_o : out std_logic_vector (7 downto 0);
m_state_o : out std_logic_vector (3 downto 0);
s_state_o : out std_logic_vector (3 downto 0);
dbg_o : out std_logic_vector(11 downto 0)
);
end component;
61,9 → 65,21
-- debug output signals
signal leds : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
-- debug ports
signal spi_do_s : std_logic_vector (7 downto 0) := (others => '0');
signal spi_state_s : std_logic_vector (3 downto 0) := (others => '0');
-- debug ports --
signal s_do_reg : std_logic_vector (7 downto 0);
signal m_do_reg : std_logic_vector (7 downto 0);
-- master signals mapped on dbg
signal wren_m : std_logic;
signal wr_ack_m : std_logic;
signal di_req_m : std_logic;
signal do_valid_m : std_logic;
signal master_state : std_logic_vector (3 downto 0);
-- slave signals mapped on dbg
signal wren_s : std_logic;
signal wr_ack_s : std_logic;
signal di_req_s : std_logic;
signal do_valid_s : std_logic;
signal slave_state : std_logic_vector (3 downto 0);
begin
 
--=============================================================================================
85,11 → 101,22
sw_i => sw_data,
btn_i => btn_data,
led_o => leds,
m_state_o => master_state,
s_state_o => slave_state,
dbg_o => dbg
);
 
spi_do_s <= dbg(7 downto 0);
spi_state_s <= dbg(11 downto 8);
-- master signals mapped on dbg
wren_m <= dbg(11);
wr_ack_m <= dbg(10);
di_req_m <= dbg(9);
do_valid_m <= dbg(8);
-- slave signals mapped on dbg
wren_s <= dbg(7);
wr_ack_s <= dbg(6);
di_req_s <= dbg(5);
do_valid_s <= dbg(4);
 
--=============================================================================================
-- CLOCK GENERATION
109,8 → 136,12
begin
wait for 100 ns; -- wait until global set/reset completes
 
btn_data(btRESET) <= '1';
wait for 1 us;
btn_data(btRESET) <= '0';
wait for 900 ns;
sw_data <= X"5A";
btn_data(btRIGHT) <= '1';
wait; -- will wait forever
end process tb;
/spi_master_slave/trunk/syn/spi_master_atlys_top_bit.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/spi_master_slave/trunk/syn/spi_test_ct.wcfg
0,0 → 1,116
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/dropbox/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="testbench" />
<top_module name="textio" />
<top_module name="vcomponents" />
<top_module name="vital_primitives" />
<top_module name="vital_timing" />
<top_module name="vpackage" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="22" />
<wvobject fp_name="/testbench/dbg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dbg[11:0]</obj_property>
<obj_property name="ObjectShortName">dbg[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/sysclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sysclk</obj_property>
<obj_property name="ObjectShortName">sysclk</obj_property>
</wvobject>
<wvobject fp_name="/testbench/sw_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sw_data[7:0]</obj_property>
<obj_property name="ObjectShortName">sw_data[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/btn_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">btn_data[5:0]</obj_property>
<obj_property name="ObjectShortName">btn_data[5:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_ssel" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_ssel</obj_property>
<obj_property name="ObjectShortName">spi_ssel</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_sck" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_sck</obj_property>
<obj_property name="ObjectShortName">spi_sck</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_mosi" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_mosi</obj_property>
<obj_property name="ObjectShortName">spi_mosi</obj_property>
</wvobject>
<wvobject fp_name="/testbench/dbg[3]" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">dbg[3]</obj_property>
</wvobject>
<wvobject fp_name="/testbench/spi_miso" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">spi_miso</obj_property>
<obj_property name="ObjectShortName">spi_miso</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wren_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wren_m</obj_property>
<obj_property name="ObjectShortName">wren_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wr_ack_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wr_ack_m</obj_property>
<obj_property name="ObjectShortName">wr_ack_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/di_req_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">di_req_m</obj_property>
<obj_property name="ObjectShortName">di_req_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/do_valid_m" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">do_valid_m</obj_property>
<obj_property name="ObjectShortName">do_valid_m</obj_property>
</wvobject>
<wvobject fp_name="/testbench/m_do_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">m_do_reg[7:0]</obj_property>
<obj_property name="ObjectShortName">m_do_reg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/master_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">master_state[3:0]</obj_property>
<obj_property name="ObjectShortName">master_state[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wren_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wren_s</obj_property>
<obj_property name="ObjectShortName">wren_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/wr_ack_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wr_ack_s</obj_property>
<obj_property name="ObjectShortName">wr_ack_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/di_req_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">di_req_s</obj_property>
<obj_property name="ObjectShortName">di_req_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/do_valid_s" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">do_valid_s</obj_property>
<obj_property name="ObjectShortName">do_valid_s</obj_property>
</wvobject>
<wvobject fp_name="/testbench/s_do_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_do_reg[7:0]</obj_property>
<obj_property name="ObjectShortName">s_do_reg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/leds" type="array" db_ref_id="1">
<obj_property name="ElementShortName">leds[7:0]</obj_property>
<obj_property name="ObjectShortName">leds[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/testbench/slave_state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">slave_state[3:0]</obj_property>
<obj_property name="ObjectShortName">slave_state[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>
/spi_master_slave/trunk/syn/spi_slave.vhd
115,6 → 115,10
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
-- Simulated in iSim with the master core for continuous transmission mode.
-- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
--
--
-----------------------------------------------------------------------------------------------------------------------
121,12 → 125,11
-- TODO
-- ====
--
--
-----------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
entity spi_slave is
Generic (
150,7 → 153,7
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
165,7 → 168,7
-- synthesis tool will remove the receive logic from the generated circuitry.
--================================================================================================================
 
architecture RTL of spi_slave is
architecture rtl of spi_slave is
-- constants to control FlipFlop synthesis
constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge
constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge
180,25 → 183,25
-- By using GSR for the initialization, and reducing RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
------------------------------------------------------------------------------------------
-- internal state signals for register and combinational stages
-- internal state signals for register and combinatorial stages
signal state_next : natural range N downto 0 := 0; -- state 0 is idle state
signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state
-- shifter signals for register and combinational stages
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector (N-1 downto 0);
signal sh_reg : std_logic_vector (N-1 downto 0);
-- mosi and miso connections
signal rx_bit_next : std_logic := '0';
signal tx_bit_next : std_logic := '0';
signal tx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinational stages
signal rx_bit_next : std_logic;
signal tx_bit_next : std_logic;
signal tx_bit_reg : std_logic;
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector (N-1 downto 0);
-- internal wren_i stretcher for fsm combinational stage
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinational stages
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector (N-1 downto 0);
signal do_buffer_reg : std_logic_vector (N-1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
291,7 → 294,7
end process in_transfer_proc;
 
--=============================================================================================
-- RTL CORE REGISTER PROCESSES
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT_EDGE
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
317,9 → 320,9
end process core_reg_proc;
 
--=============================================================================================
-- RTL COMBINATIONAL LOGIC PROCESSES
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinational logic
-- state and datapath combinatorial logic
core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
begin
332,15 → 335,16
di_req_next <= di_req_reg; -- data input request
state_next <= state_reg; -- fsm control state
case state_reg is
when (N) =>
-- acknowledge write enable
wr_ack_next <= '1'; -- acknowledge data in transfer
do_transfer_next <= '0'; -- reset transfer signal
-- stretch do_valid
wr_ack_next <= '0'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
tx_bit_next <= sh_reg(N-1); -- output next MSbit
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N-1) downto (PREFETCH+3) =>
-- send bit out and shif bit in
do_transfer_next <= '0'; -- reset transfer signal
350,6 → 354,7
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH+2) downto 3 =>
-- raise data prefetch request
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
358,6 → 363,7
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
state_next <= state_reg - 1; -- update next state at each sck pulse
when 2 =>
-- transfer parallel data on next state
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
368,6 → 374,7
do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle
do_buffer_next <= sh_next; -- get next data directly into rx buffer
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 =>
-- restart from state 'N' if more sck pulses come
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
374,7 → 381,6
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
if wren = '1' then -- load tx register if valid data present at di_reg
wr_ack_next <= '1'; -- acknowledge data in transfer
state_next <= N; -- next state is top bit of new data
383,44 → 389,53
sh_next <= (others => '0'); -- load null data (output '0' if no load)
state_next <= 0; -- next state is idle state
end if;
when 0 =>
-- idle state: start and end of transmission
if CPHA = '1' then
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
else
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= not wr_ack_reg; -- will request data if shifter empty
sh_next <= di_reg; -- load parallel data from di_reg into shifter
end if;
sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
wr_ack_next <= '1'; -- acknowledge data in transfer
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data
state_next <= N; -- next state is top bit of new data
when others =>
state_next <= 0; -- safe state
end case;
end process core_combi_proc;
 
--=============================================================================================
-- RTL OUTPUT LOGIC PROCESSES
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_miso_o_proc: spi_miso_o <= tx_bit_reg; -- connect MISO driver
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output
 
-----------------------------------------------------------------------------------------------
-- MISO driver process: copy next tx bit at reset
-----------------------------------------------------------------------------------------------
-- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
-- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is
begin
if spi_ssel_i = '1' then
spi_miso_o <= tx_bit_next; -- copy next => reg at reset
else
spi_miso_o <= tx_bit_reg;
end if;
end process spi_miso_o_proc;
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted or commented-out after debug.
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
rx_bit_next_proc: rx_bit_next_o <= rx_bit_next;
wren_o_proc: wren_o <= wren;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture RTL;
end architecture rtl;
 

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