URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
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/
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/spi_master_slave/trunk/rtl/spi_slave.vhd
73,26 → 73,26
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
-- disclaimer. |
-- |
-- disclaimer. |
-- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser |
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/spi_master_slave/trunk/rtl/spi_master.vhd
90,10 → 90,10
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
108,7 → 108,7
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/spi_master_slave/trunk/rtl/readme.txt
31,7 → 31,13
|
Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board. |
|
LICENSING |
--------- |
|
This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. |
|
|
|
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer. |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |
/spi_master_slave/trunk/rtl/grp_debouncer.vhd
40,21 → 40,23
-- | | | | |
-- | | \----------\ | |
-- | | N | | |
-- | \--------/-----------\ +----------------------+-----------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ |
-- ------ ------ | ------ | N ____ \-----| \ |
-- | \----/----)) \ |AND |-----------[strb_o] |
-- | ))XOR |-------|___/ |
-- \--------------------------/----))___/ |
-- N |
-- | \--------/-----------\ +----------------------+---------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ ______ |
-- ------ ------ | ------ | N ____ \---| \ | fd | |
-- | \---/---)) \ |AND |-----| |----[strb_o] |
-- | ))XOR |-----|___/ | | |
-- \-------------------------/---))___/ | | |
-- N | | |
-- |> | |
-- ------ |
-- |
-- |
-- PIPELINE LOGIC |
75,12 → 77,12
-- RESOURCES USED |
-- ============== |
-- |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers. |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers. |
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2. |
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. |
-- |
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock. |
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
88,8 → 90,8
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
104,12 → 106,13
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. |
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). |
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
138,6 → 141,8
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors |
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output |
signal dat_strb : std_logic := '0'; -- data transfer strobe |
signal strb_reg : std_logic := '0'; -- registered strobe |
signal strb_next : std_logic := '0'; -- lookahead strobe |
signal dat_diff : std_logic := '0'; -- edge detector |
-- debounce counter |
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter |
169,11 → 174,14
-- input pipeline logic |
pipeline_proc: process (clk_i) is |
begin |
-- edge detection pipeline |
if clk_i'event and clk_i = '1' then |
-- edge detection pipeline |
reg_A <= data_i; |
reg_B <= reg_A; |
-- new data strobe pipeline delay |
strb_reg <= strb_next; |
end if; |
-- output data pipeline |
if clk_i'event and clk_i = '1' then |
if dat_strb = '1' then |
reg_out <= reg_B; |
182,14 → 190,14
end process pipeline_proc; |
-- edge detector |
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0'; |
-- lookahead new data strobe |
next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
|
--============================================================================================= |
-- OUTPUT LOGIC |
--============================================================================================= |
-- new data strobe detection |
strb_o_proc: strb_o <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
-- connect output ports |
data_o_proc: data_o <= reg_out; |
|
strb_o_proc: strb_o <= strb_reg; |
end rtl; |
|
/spi_master_slave/trunk/license/lgpl.txt
0,0 → 1,165
GNU LESSER GENERAL PUBLIC LICENSE |
Version 3, 29 June 2007 |
|
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> |
Everyone is permitted to copy and distribute verbatim copies |
of this license document, but changing it is not allowed. |
|
|
This version of the GNU Lesser General Public License incorporates |
the terms and conditions of version 3 of the GNU General Public |
License, supplemented by the additional permissions listed below. |
|
0. Additional Definitions. |
|
As used herein, "this License" refers to version 3 of the GNU Lesser |
General Public License, and the "GNU GPL" refers to version 3 of the GNU |
General Public License. |
|
"The Library" refers to a covered work governed by this License, |
other than an Application or a Combined Work as defined below. |
|
An "Application" is any work that makes use of an interface provided |
by the Library, but which is not otherwise based on the Library. |
Defining a subclass of a class defined by the Library is deemed a mode |
of using an interface provided by the Library. |
|
A "Combined Work" is a work produced by combining or linking an |
Application with the Library. The particular version of the Library |
with which the Combined Work was made is also called the "Linked |
Version". |
|
The "Minimal Corresponding Source" for a Combined Work means the |
Corresponding Source for the Combined Work, excluding any source code |
for portions of the Combined Work that, considered in isolation, are |
based on the Application, and not on the Linked Version. |
|
The "Corresponding Application Code" for a Combined Work means the |
object code and/or source code for the Application, including any data |
and utility programs needed for reproducing the Combined Work from the |
Application, but excluding the System Libraries of the Combined Work. |
|
1. Exception to Section 3 of the GNU GPL. |
|
You may convey a covered work under sections 3 and 4 of this License |
without being bound by section 3 of the GNU GPL. |
|
2. Conveying Modified Versions. |
|
If you modify a copy of the Library, and, in your modifications, a |
facility refers to a function or data to be supplied by an Application |
that uses the facility (other than as an argument passed when the |
facility is invoked), then you may convey a copy of the modified |
version: |
|
a) under this License, provided that you make a good faith effort to |
ensure that, in the event an Application does not supply the |
function or data, the facility still operates, and performs |
whatever part of its purpose remains meaningful, or |
|
b) under the GNU GPL, with none of the additional permissions of |
this License applicable to that copy. |
|
3. Object Code Incorporating Material from Library Header Files. |
|
The object code form of an Application may incorporate material from |
a header file that is part of the Library. You may convey such object |
code under terms of your choice, provided that, if the incorporated |
material is not limited to numerical parameters, data structure |
layouts and accessors, or small macros, inline functions and templates |
(ten or fewer lines in length), you do both of the following: |
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a) Give prominent notice with each copy of the object code that the |
Library is used in it and that the Library and its use are |
covered by this License. |
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b) Accompany the object code with a copy of the GNU GPL and this license |
document. |
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4. Combined Works. |
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You may convey a Combined Work under terms of your choice that, |
taken together, effectively do not restrict modification of the |
portions of the Library contained in the Combined Work and reverse |
engineering for debugging such modifications, if you also do each of |
the following: |
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a) Give prominent notice with each copy of the Combined Work that |
the Library is used in it and that the Library and its use are |
covered by this License. |
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b) Accompany the Combined Work with a copy of the GNU GPL and this license |
document. |
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c) For a Combined Work that displays copyright notices during |
execution, include the copyright notice for the Library among |
these notices, as well as a reference directing the user to the |
copies of the GNU GPL and this license document. |
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d) Do one of the following: |
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0) Convey the Minimal Corresponding Source under the terms of this |
License, and the Corresponding Application Code in a form |
suitable for, and under terms that permit, the user to |
recombine or relink the Application with a modified version of |
the Linked Version to produce a modified Combined Work, in the |
manner specified by section 6 of the GNU GPL for conveying |
Corresponding Source. |
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1) Use a suitable shared library mechanism for linking with the |
Library. A suitable mechanism is one that (a) uses at run time |
a copy of the Library already present on the user's computer |
system, and (b) will operate properly with a modified version |
of the Library that is interface-compatible with the Linked |
Version. |
|
e) Provide Installation Information, but only if you would otherwise |
be required to provide such information under section 6 of the |
GNU GPL, and only to the extent that such information is |
necessary to install and execute a modified version of the |
Combined Work produced by recombining or relinking the |
Application with a modified version of the Linked Version. (If |
you use option 4d0, the Installation Information must accompany |
the Minimal Corresponding Source and Corresponding Application |
Code. If you use option 4d1, you must provide the Installation |
Information in the manner specified by section 6 of the GNU GPL |
for conveying Corresponding Source.) |
|
5. Combined Libraries. |
|
You may place library facilities that are a work based on the |
Library side by side in a single library together with other library |
facilities that are not Applications and are not covered by this |
License, and convey such a combined library under terms of your |
choice, if you do both of the following: |
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a) Accompany the combined library with a copy of the same work based |
on the Library, uncombined with any other library facilities, |
conveyed under the terms of this License. |
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b) Give prominent notice with the combined library that part of it |
is a work based on the Library, and explaining where to find the |
accompanying uncombined form of the same work. |
|
6. Revised Versions of the GNU Lesser General Public License. |
|
The Free Software Foundation may publish revised and/or new versions |
of the GNU Lesser General Public License from time to time. Such new |
versions will be similar in spirit to the present version, but may |
differ in detail to address new problems or concerns. |
|
Each version is given a distinguishing version number. If the |
Library as you received it specifies that a certain numbered version |
of the GNU Lesser General Public License "or any later version" |
applies to it, you have the option of following the terms and |
conditions either of that published version or of any later version |
published by the Free Software Foundation. If the Library as you |
received it does not specify a version number of the GNU Lesser |
General Public License, you may choose any version of the GNU Lesser |
General Public License ever published by the Free Software Foundation. |
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If the Library as you received it specifies that a proxy can decide |
whether future versions of the GNU Lesser General Public License shall |
apply, that proxy's public statement of acceptance of any version is |
permanent authorization for you to choose that version for the |
Library. |
/spi_master_slave/trunk/syn/spi_master.vhd
90,10 → 90,10
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
108,7 → 108,7
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/spi_master_slave/trunk/syn/grp_debouncer.vhd
40,21 → 40,23
-- | | | | |
-- | | \----------\ | |
-- | | N | | |
-- | \--------/-----------\ +----------------------+-----------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-------------)----------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ |
-- ------ ------ | ------ | N ____ \-----| \ |
-- | \----/----)) \ |AND |-----------[strb_o] |
-- | ))XOR |-------|___/ |
-- \--------------------------/----))___/ |
-- N |
-- | \--------/-----------\ +----------------------+---------\ |
-- | | | | |
-- \---\ | | | |
-- ______ | ______ | | ______ | |
-- | fd | | | fd | | | |fde | | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o] |
-- N | | N N | | N | | | | N | N | |
-- | | | | | \---|CE | | | |
-- | | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ ______ |
-- ------ ------ | ------ | N ____ \---| \ | fd | |
-- | \---/---)) \ |AND |-----| |----[strb_o] |
-- | ))XOR |-----|___/ | | |
-- \-------------------------/---))___/ | | |
-- N | | |
-- |> | |
-- ------ |
-- |
-- |
-- PIPELINE LOGIC |
75,12 → 77,12
-- RESOURCES USED |
-- ============== |
-- |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) registers. |
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers. |
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2. |
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. |
-- |
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clk_i. |
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock. |
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
88,8 → 90,8
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
104,12 → 106,13
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. |
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). |
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
138,6 → 141,8
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors |
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output |
signal dat_strb : std_logic := '0'; -- data transfer strobe |
signal strb_reg : std_logic := '0'; -- registered strobe |
signal strb_next : std_logic := '0'; -- lookahead strobe |
signal dat_diff : std_logic := '0'; -- edge detector |
-- debounce counter |
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter |
169,11 → 174,14
-- input pipeline logic |
pipeline_proc: process (clk_i) is |
begin |
-- edge detection pipeline |
if clk_i'event and clk_i = '1' then |
-- edge detection pipeline |
reg_A <= data_i; |
reg_B <= reg_A; |
-- new data strobe pipeline delay |
strb_reg <= strb_next; |
end if; |
-- output data pipeline |
if clk_i'event and clk_i = '1' then |
if dat_strb = '1' then |
reg_out <= reg_B; |
182,14 → 190,14
end process pipeline_proc; |
-- edge detector |
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0'; |
-- lookahead new data strobe |
next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
|
--============================================================================================= |
-- OUTPUT LOGIC |
--============================================================================================= |
-- new data strobe detection |
strb_o_proc: strb_o <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0'; |
-- connect output ports |
data_o_proc: data_o <= reg_out; |
|
strb_o_proc: strb_o <= strb_reg; |
end rtl; |
|
/spi_master_slave/trunk/syn/spi_slave.vhd
73,26 → 73,26
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
-- disclaimer. |
-- |
-- disclaimer. |
-- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser |
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/spi_master_slave/trunk/syn/readme.txt
24,7 → 24,13
spi_master_atlys_top_bit.zip bitgen file to program the Atlys board |
|
|
LICENSING |
--------- |
|
This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. |
|
|
|
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer, or send me e-mail: jdoin@opencores.org |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |