OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

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    /spi_master_slave/trunk/syn
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Rev 23 → Rev 24

/spi_master_atlys_top.twr
31,75 → 31,93
-----------------
All values displayed in nanoseconds (ns)
 
Setup/Hold to clock gclk_i
Setup/Hold to clock pclk_i
------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
btn_i<0> | 3.220(R)| SLOW | -1.908(R)| FAST |gclk_i_BUFGP | 0.000|
btn_i<1> | 2.732(R)| SLOW | -1.473(R)| FAST |gclk_i_BUFGP | 0.000|
btn_i<2> | 2.624(R)| SLOW | -1.423(R)| FAST |gclk_i_BUFGP | 0.000|
btn_i<3> | 2.466(R)| SLOW | -1.367(R)| SLOW |gclk_i_BUFGP | 0.000|
btn_i<4> | 2.808(R)| SLOW | -1.482(R)| FAST |gclk_i_BUFGP | 0.000|
btn_i<5> | 2.631(R)| SLOW | -1.435(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<0> | 4.138(R)| SLOW | -2.205(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<1> | 5.757(R)| SLOW | -3.265(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<2> | 5.825(R)| SLOW | -3.246(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<3> | 4.946(R)| SLOW | -2.785(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<4> | 3.431(R)| SLOW | -1.904(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<5> | 3.569(R)| SLOW | -2.000(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<6> | 3.411(R)| SLOW | -1.943(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<7> | 5.265(R)| SLOW | -2.971(R)| FAST |gclk_i_BUFGP | 0.000|
btn_i<0> | 3.281(R)| SLOW | -1.883(R)| FAST |pclk_i_BUFGP | 0.000|
btn_i<1> | 2.636(R)| SLOW | -1.373(R)| FAST |pclk_i_BUFGP | 0.000|
btn_i<2> | 2.349(R)| SLOW | -1.227(R)| FAST |pclk_i_BUFGP | 0.000|
btn_i<3> | 2.429(R)| SLOW | -1.296(R)| FAST |pclk_i_BUFGP | 0.000|
btn_i<4> | 2.683(R)| SLOW | -1.357(R)| FAST |pclk_i_BUFGP | 0.000|
btn_i<5> | 2.506(R)| SLOW | -1.310(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<0> | 4.238(R)| SLOW | -2.204(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<1> | 5.454(R)| SLOW | -2.988(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<2> | 5.564(R)| SLOW | -3.092(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<3> | 4.954(R)| SLOW | -2.667(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<4> | 3.356(R)| SLOW | -1.807(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<5> | 3.819(R)| SLOW | -2.067(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<6> | 3.504(R)| SLOW | -1.935(R)| FAST |pclk_i_BUFGP | 0.000|
sw_i<7> | 4.898(R)| SLOW | -2.712(R)| FAST |pclk_i_BUFGP | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
 
Clock gclk_i to Pad
Clock pclk_i to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
dbg_o<4> | 9.886(R)| SLOW | 4.102(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<5> | 9.856(R)| SLOW | 4.079(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<7> | 10.279(R)| SLOW | 4.343(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<8> | 10.485(R)| SLOW | 4.438(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<9> | 10.661(R)| SLOW | 4.583(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<10> | 10.595(R)| SLOW | 4.516(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<11> | 10.797(R)| SLOW | 4.632(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<0> | 10.127(R)| SLOW | 4.227(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<1> | 9.955(R)| SLOW | 4.135(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<2> | 10.096(R)| SLOW | 4.211(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<3> | 9.531(R)| SLOW | 3.887(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<4> | 10.129(R)| SLOW | 4.244(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<5> | 16.930(R)| SLOW | 8.194(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<6> | 12.027(R)| SLOW | 5.407(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<7> | 11.196(R)| SLOW | 4.818(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<0> | 9.636(R)| SLOW | 3.930(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<1> | 9.683(R)| SLOW | 3.987(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<2> | 9.651(R)| SLOW | 3.945(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<3> | 9.718(R)| SLOW | 4.091(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<4> | 9.623(R)| SLOW | 4.055(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<5> | 9.875(R)| SLOW | 4.135(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<6> | 9.742(R)| SLOW | 4.088(R)| FAST |gclk_i_BUFGP | 0.000|
m_do_o<7> | 9.568(R)| SLOW | 4.000(R)| FAST |gclk_i_BUFGP | 0.000|
m_state_o<0>| 11.544(R)| SLOW | 5.167(R)| FAST |gclk_i_BUFGP | 0.000|
m_state_o<1>| 11.702(R)| SLOW | 5.283(R)| FAST |gclk_i_BUFGP | 0.000|
m_state_o<2>| 11.667(R)| SLOW | 5.272(R)| FAST |gclk_i_BUFGP | 0.000|
m_state_o<3>| 11.707(R)| SLOW | 5.314(R)| FAST |gclk_i_BUFGP | 0.000|
spi_miso_o | 11.814(R)| SLOW | 5.115(R)| FAST |gclk_i_BUFGP | 0.000|
spi_mosi_o | 13.768(R)| SLOW | 5.317(R)| FAST |gclk_i_BUFGP | 0.000|
spi_sck_o | 11.645(R)| SLOW | 5.148(R)| FAST |gclk_i_BUFGP | 0.000|
spi_ssel_o | 12.580(R)| SLOW | 5.649(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<4> | 10.259(R)| SLOW | 4.367(R)| FAST |pclk_i_BUFGP | 0.000|
dbg_o<5> | 10.673(R)| SLOW | 4.584(R)| FAST |pclk_i_BUFGP | 0.000|
dbg_o<7> | 11.287(R)| SLOW | 4.943(R)| FAST |pclk_i_BUFGP | 0.000|
dbg_o<8> | 10.559(R)| SLOW | 4.549(R)| FAST |pclk_i_BUFGP | 0.000|
dbg_o<9> | 11.050(R)| SLOW | 4.864(R)| FAST |pclk_i_BUFGP | 0.000|
dbg_o<11> | 11.417(R)| SLOW | 5.029(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<0> | 10.269(R)| SLOW | 4.340(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<1> | 10.286(R)| SLOW | 4.343(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<2> | 10.086(R)| SLOW | 4.243(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<3> | 9.662(R)| SLOW | 4.013(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<4> | 10.628(R)| SLOW | 4.638(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<5> | 16.982(R)| SLOW | 8.242(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<6> | 11.879(R)| SLOW | 5.270(R)| FAST |pclk_i_BUFGP | 0.000|
led_o<7> | 11.522(R)| SLOW | 5.043(R)| FAST |pclk_i_BUFGP | 0.000|
spi_miso_o | 12.331(R)| SLOW | 5.494(R)| FAST |pclk_i_BUFGP | 0.000|
spi_mosi_o | 13.082(R)| SLOW | 5.597(R)| FAST |pclk_i_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
 
Clock to Setup on destination clock gclk_i
Clock sclk_i to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
dbg_o<10> | 10.866(R)| SLOW | 4.745(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<0> | 9.804(R)| SLOW | 4.076(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<1> | 10.049(R)| SLOW | 4.245(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<2> | 9.996(R)| SLOW | 4.197(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<3> | 10.252(R)| SLOW | 4.438(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<4> | 10.157(R)| SLOW | 4.402(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<5> | 10.068(R)| SLOW | 4.306(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<6> | 10.140(R)| SLOW | 4.388(R)| FAST |sclk_i_BUFGP | 0.000|
m_do_o<7> | 9.935(R)| SLOW | 4.259(R)| FAST |sclk_i_BUFGP | 0.000|
m_state_o<0>| 12.092(R)| SLOW | 5.558(R)| FAST |sclk_i_BUFGP | 0.000|
m_state_o<1>| 11.789(R)| SLOW | 5.330(R)| FAST |sclk_i_BUFGP | 0.000|
m_state_o<2>| 12.048(R)| SLOW | 5.490(R)| FAST |sclk_i_BUFGP | 0.000|
m_state_o<3>| 12.089(R)| SLOW | 5.504(R)| FAST |sclk_i_BUFGP | 0.000|
spi_mosi_o | 13.069(R)| SLOW | 5.577(R)| FAST |sclk_i_BUFGP | 0.000|
spi_sck_o | 11.491(R)| SLOW | 5.149(R)| FAST |sclk_i_BUFGP | 0.000|
spi_ssel_o | 12.854(R)| SLOW | 5.864(R)| FAST |sclk_i_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
 
Clock to Setup on destination clock pclk_i
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i | 4.888| | | |
pclk_i | 5.916| | | |
sclk_i | 4.466| | | |
---------------+---------+---------+---------+---------+
 
Clock to Setup on destination clock sclk_i
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
pclk_i | 3.370| | | |
sclk_i | 3.391| | | |
---------------+---------+---------+---------+---------+
 
Analysis completed Mon Aug 29 00:08:54 2011
 
Analysis completed Thu Sep 01 13:07:46 2011
--------------------------------------------------------------------------------
 
Trace Settings:
106,7 → 124,7
-------------------------
Trace Settings
 
Peak Memory Usage: 177 MB
Peak Memory Usage: 180 MB
 
 
 
/spi_master_atlys_top.syr
104,23 → 104,23
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
Parsing entity <spi_slave>.
Parsing architecture <rtl> of entity <spi_slave>.
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
Parsing entity <spi_master>.
Parsing architecture <rtl> of entity <spi_master>.
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
Parsing entity <grp_debouncer>.
Parsing architecture <rtl> of entity <grp_debouncer>.
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
Parsing entity <spi_master_atlys_top>.
Parsing architecture <rtl> of entity <spi_master_atlys_top>.
 
137,9 → 137,9
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.
 
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 459. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 521. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 571. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 460. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 522. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 572. Case statement is complete. others clause is never selected
 
=========================================================================
* HDL Synthesis *
146,27 → 146,27
=========================================================================
 
Synthesizing Unit <spi_master_atlys_top>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
N = 8
CPOL = '0'
CPHA = '0'
PREFETCH = 3
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <sh_reg_dbg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <sck_ena_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <sck_ena_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <do_transfer_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <wren_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <rx_bit_reg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_n_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port <core_n_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <sh_reg_dbg_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <do_transfer_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <wren_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port <rx_bit_next_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 224: Output port <strb_o> of the instance <Inst_sw_debouncer> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 233: Output port <strb_o> of the instance <Inst_btn_debouncer> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <sh_reg_dbg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <sck_ena_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <sck_ena_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <do_transfer_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <wren_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <rx_bit_reg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_n_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 185: Output port <core_n_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <sh_reg_dbg_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <do_transfer_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <wren_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 206: Output port <rx_bit_next_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 225: Output port <strb_o> of the instance <Inst_sw_debouncer> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 234: Output port <strb_o> of the instance <Inst_btn_debouncer> is unconnected or connected to loadless signal.
Found 1-bit register for signal <samp_ce_gen_proc.clk_cnt>.
Found 1-bit register for signal <fsm_ce>.
Found 1-bit register for signal <fsm_ce_gen_proc.clk_cnt>.
193,7 → 193,7
| Transitions | 20 |
| Inputs | 2 |
| Outputs | 3 |
| Clock | gclk_i (rising_edge) |
| Clock | pclk_i (rising_edge) |
| Reset | spi_ssel_o (positive) |
| Reset type | synchronous |
| Reset State | st_reset |
207,7 → 207,7
| Transitions | 36 |
| Inputs | 11 |
| Outputs | 10 |
| Clock | gclk_i (rising_edge) |
| Clock | pclk_i (rising_edge) |
| Reset | clear (positive) |
| Reset type | synchronous |
| Reset State | st_reset |
222,7 → 222,7
| Transitions | 20 |
| Inputs | 5 |
| Outputs | 9 |
| Clock | gclk_i (rising_edge) |
| Clock | pclk_i (rising_edge) |
| Reset | spi_ssel_o (positive) |
| Reset type | synchronous |
| Reset State | st_reset |
230,10 → 230,10
| Encoding | Gray |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 1-bit adder for signal <samp_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_1_OUT<0>> created at line 276.
Found 1-bit adder for signal <fsm_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_3_OUT<0>> created at line 290.
Found 8-bit comparator equal for signal <_n0380> created at line 362
Found 6-bit comparator equal for signal <_n0400> created at line 365
Found 1-bit adder for signal <samp_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_1_OUT<0>> created at line 277.
Found 1-bit adder for signal <fsm_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_3_OUT<0>> created at line 291.
Found 8-bit comparator equal for signal <_n0380> created at line 363
Found 6-bit comparator equal for signal <_n0400> created at line 366
Summary:
inferred 2 Adder/Subtractor(s).
inferred 71 D-type flip-flop(s).
243,7 → 243,7
Unit <spi_master_atlys_top> synthesized.
 
Synthesizing Unit <spi_master>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master.vhd".
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd".
N = 8
CPOL = '0'
CPHA = '0'
291,7 → 291,7
Unit <spi_master> synthesized.
 
Synthesizing Unit <spi_slave>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_slave.vhd".
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd".
N = 8
CPOL = '0'
CPHA = '0'
329,36 → 329,38
Unit <spi_slave> synthesized.
 
Synthesizing Unit <grp_debouncer_1>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
N = 8
CNT_VAL = 20000
CNT_VAL = 200
Found 8-bit register for signal <reg_A>.
Found 8-bit register for signal <reg_B>.
Found 1-bit register for signal <strb_reg>.
Found 8-bit register for signal <reg_out>.
Found 15-bit register for signal <cnt_reg>.
Found 16-bit adder for signal <n0024> created at line 162.
Found 8-bit comparator not equal for signal <n0008> created at line 184
Found 8-bit comparator not equal for signal <n0010> created at line 190
Found 8-bit register for signal <cnt_reg>.
Found 9-bit adder for signal <n0026> created at line 167.
Found 8-bit comparator not equal for signal <n0009> created at line 192
Found 8-bit comparator not equal for signal <n0011> created at line 194
Summary:
inferred 1 Adder/Subtractor(s).
inferred 39 D-type flip-flop(s).
inferred 33 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <grp_debouncer_1> synthesized.
 
Synthesizing Unit <grp_debouncer_2>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
N = 6
CNT_VAL = 20000
CNT_VAL = 200
Found 6-bit register for signal <reg_A>.
Found 6-bit register for signal <reg_B>.
Found 1-bit register for signal <strb_reg>.
Found 6-bit register for signal <reg_out>.
Found 15-bit register for signal <cnt_reg>.
Found 16-bit adder for signal <n0024> created at line 162.
Found 6-bit comparator not equal for signal <n0008> created at line 184
Found 6-bit comparator not equal for signal <n0010> created at line 190
Found 8-bit register for signal <cnt_reg>.
Found 9-bit adder for signal <n0026> created at line 167.
Found 6-bit comparator not equal for signal <n0009> created at line 192
Found 6-bit comparator not equal for signal <n0011> created at line 194
Summary:
inferred 1 Adder/Subtractor(s).
inferred 33 D-type flip-flop(s).
inferred 27 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <grp_debouncer_2> synthesized.
 
368,14 → 370,13
Macro Statistics
# Adders/Subtractors : 7
1-bit adder : 3
16-bit adder : 2
4-bit subtractor : 2
# Registers : 73
1-bit register : 49
15-bit register : 2
9-bit adder : 2
# Registers : 75
1-bit register : 51
4-bit register : 2
6-bit register : 4
8-bit register : 16
8-bit register : 18
# Comparators : 14
4-bit comparator greater : 8
6-bit comparator equal : 1
426,9 → 427,9
4-bit subtractor : 2
# Counters : 5
1-bit up counter : 3
15-bit up counter : 2
# Registers : 206
Flip-Flops : 206
8-bit up counter : 2
# Registers : 208
Flip-Flops : 208
# Comparators : 14
4-bit comparator greater : 8
6-bit comparator equal : 1
510,6 → 511,8
Optimizing unit <spi_master> ...
 
Optimizing unit <spi_slave> ...
WARNING:Xst:2677 - Node <Inst_sw_debouncer/strb_reg> of sequential type is unconnected in block <spi_master_atlys_top>.
WARNING:Xst:2677 - Node <Inst_btn_debouncer/strb_reg> of sequential type is unconnected in block <spi_master_atlys_top>.
WARNING:Xst:1293 - FF/Latch <fsm_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process.
534,8 → 537,8
Final Register Report
 
Macro Statistics
# Registers : 232
Flip-Flops : 232
# Registers : 218
Flip-Flops : 218
 
=========================================================================
 
558,30 → 561,30
 
Primitive and Black Box Usage:
------------------------------
# BELS : 259
# BELS : 202
# GND : 1
# INV : 4
# LUT1 : 28
# LUT2 : 3
# LUT3 : 26
# LUT1 : 14
# LUT2 : 4
# LUT3 : 28
# LUT4 : 17
# LUT5 : 62
# LUT6 : 55
# MUXCY : 28
# LUT5 : 54
# LUT6 : 45
# MUXCY : 14
# MUXF7 : 4
# VCC : 1
# XORCY : 30
# FlipFlops/Latches : 232
# FD : 97
# XORCY : 16
# FlipFlops/Latches : 218
# FD : 84
# FD_1 : 1
# FDC : 8
# FDE : 111
# FDE : 110
# FDP_1 : 1
# FDR : 10
# FDRE : 4
# Clock Buffers : 2
# Clock Buffers : 3
# BUFG : 1
# BUFGP : 1
# BUFGP : 2
# IO Buffers : 62
# IBUF : 14
# OBUF : 48
593,23 → 596,23
 
 
Slice Logic Utilization:
Number of Slice Registers: 232 out of 54576 0%
Number of Slice LUTs: 195 out of 27288 0%
Number used as Logic: 195 out of 27288 0%
Number of Slice Registers: 218 out of 54576 0%
Number of Slice LUTs: 166 out of 27288 0%
Number used as Logic: 166 out of 27288 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 301
Number with an unused Flip Flop: 69 out of 301 22%
Number with an unused LUT: 106 out of 301 35%
Number of fully used LUT-FF pairs: 126 out of 301 41%
Number of unique control sets: 23
Number of LUT Flip Flop pairs used: 272
Number with an unused Flip Flop: 54 out of 272 19%
Number with an unused LUT: 106 out of 272 38%
Number of fully used LUT-FF pairs: 112 out of 272 41%
Number of unique control sets: 24
 
IO Utilization:
Number of IOs: 63
Number of bonded IOBs: 63 out of 218 28%
Number of IOs: 64
Number of bonded IOBs: 64 out of 218 29%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
Number of BUFG/BUFGCTRLs: 3 out of 16 18%
 
---------------------------
Partition Resource Summary:
632,7 → 635,8
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
gclk_i | BUFGP | 203 |
pclk_i | BUFGP | 161 |
sclk_i | BUFGP | 28 |
Inst_spi_master_port/spi_clk_reg | BUFG | 29 |
-----------------------------------+------------------------+-------+
 
644,7 → 648,7
---------------
Speed Grade: -2
 
Minimum period: 5.267ns (Maximum Frequency: 189.861MHz)
Minimum period: 5.283ns (Maximum Frequency: 189.286MHz)
Minimum input arrival time before clock: 2.083ns
Maximum output required time after clock: 7.216ns
Maximum combinational path delay: No path found
654,31 → 658,53
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'gclk_i'
Clock period: 5.267ns (frequency: 189.861MHz)
Total number of paths / destination ports: 2605 / 280
Timing constraint: Default period analysis for Clock 'pclk_i'
Clock period: 5.283ns (frequency: 189.286MHz)
Total number of paths / destination ports: 1509 / 201
-------------------------------------------------------------------------
Delay: 5.267ns (Levels of Logic = 4)
Delay: 5.283ns (Levels of Logic = 4)
Source: sw_reg_5 (FF)
Destination: m_wr_st_reg_FSM_FFd4 (FF)
Source Clock: gclk_i rising
Destination Clock: gclk_i rising
Destination: btn_reg_0 (FF)
Source Clock: pclk_i rising
Destination Clock: pclk_i rising
 
Data Path: sw_reg_5 to m_wr_st_reg_FSM_FFd4
Data Path: sw_reg_5 to btn_reg_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 3 0.525 1.196 sw_reg_5 (sw_reg_5)
LUT6:I1->O 2 0.254 0.834 _n038082 (_n038081)
LUT6:I4->O 8 0.250 0.944 _n038083 (_n0380)
LUT5:I4->O 1 0.254 0.682 m_wr_st_reg_FSM_FFd2-In1 (m_wr_st_reg_FSM_FFd2-In1)
LUT6:I5->O 1 0.254 0.000 m_wr_st_reg_FSM_FFd2-In2 (m_wr_st_reg_FSM_FFd2-In)
FDR:D 0.074 m_wr_st_reg_FSM_FFd2
LUT6:I4->O 3 0.250 0.766 _n038083 (_n0380)
LUT5:I4->O 6 0.254 0.876 _n0418_inv1_rstpot (_n0418_inv1_rstpot)
LUT3:I2->O 1 0.254 0.000 btn_reg_0_dpot (btn_reg_0_dpot)
FDE:D 0.074 btn_reg_0
----------------------------------------
Total 5.267ns (1.611ns logic, 3.656ns route)
(30.6% logic, 69.4% route)
Total 5.283ns (1.611ns logic, 3.672ns route)
(30.5% logic, 69.5% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'sclk_i'
Clock period: 3.764ns (frequency: 265.675MHz)
Total number of paths / destination ports: 173 / 52
-------------------------------------------------------------------------
Delay: 3.764ns (Levels of Logic = 1)
Source: Inst_spi_master_port/state_reg_3 (FF)
Destination: Inst_spi_master_port/sh_reg_7 (FF)
Source Clock: sclk_i rising
Destination Clock: sclk_i rising
 
Data Path: Inst_spi_master_port/state_reg_3 to Inst_spi_master_port/sh_reg_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 21 0.525 1.740 Inst_spi_master_port/state_reg_3 (Inst_spi_master_port/state_reg_3)
LUT6:I1->O 8 0.254 0.943 Inst_spi_master_port/_n0278_inv1 (Inst_spi_master_port/_n0278_inv)
FDE:CE 0.302 Inst_spi_master_port/sh_reg_0
----------------------------------------
Total 3.764ns (1.081ns logic, 2.683ns route)
(28.7% logic, 71.3% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
Clock period: 4.344ns (frequency: 230.203MHz)
Total number of paths / destination ports: 214 / 36
694,7 → 720,7
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 0.525 1.156 Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N10)
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N14)
MUXF7:I0->O 1 0.163 0.000 Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
FD_1:D 0.074 Inst_spi_slave_port/tx_bit_reg
----------------------------------------
702,13 → 728,13
(46.8% logic, 53.2% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
Timing constraint: Default OFFSET IN BEFORE for Clock 'pclk_i'
Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset: 2.083ns (Levels of Logic = 1)
Source: sw_i<7> (PAD)
Destination: Inst_sw_debouncer/reg_A_7 (FF)
Destination Clock: gclk_i rising
Destination Clock: pclk_i rising
 
Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
Gate Net
721,25 → 747,24
(67.3% logic, 32.7% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
Total number of paths / destination ports: 37 / 31
Timing constraint: Default OFFSET OUT AFTER for Clock 'pclk_i'
Total number of paths / destination ports: 17 / 16
-------------------------------------------------------------------------
Offset: 7.216ns (Levels of Logic = 3)
Source: Inst_spi_master_port/state_reg_2 (FF)
Offset: 5.464ns (Levels of Logic = 2)
Source: Inst_spi_master_port/wren (FF)
Destination: spi_mosi_o (PAD)
Source Clock: gclk_i rising
Source Clock: pclk_i rising
 
Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o
Data Path: Inst_spi_master_port/wren to spi_mosi_o
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 20 0.525 1.394 Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)
LUT2:I0->O 2 0.250 1.156 Inst_spi_master_port/spi_mosi_o_SW0 (N0)
LUT6:I1->O 2 0.254 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
FD:C->Q 8 0.525 1.052 Inst_spi_master_port/wren (Inst_spi_master_port/wren)
LUT6:I4->O 2 0.250 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o)
----------------------------------------
Total 7.216ns (3.941ns logic, 3.275ns route)
(54.6% logic, 45.4% route)
Total 5.464ns (3.687ns logic, 1.777ns route)
(67.5% logic, 32.5% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
762,7 → 787,28
(69.2% logic, 30.8% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'sclk_i'
Total number of paths / destination ports: 20 / 16
-------------------------------------------------------------------------
Offset: 7.216ns (Levels of Logic = 3)
Source: Inst_spi_master_port/state_reg_2 (FF)
Destination: spi_mosi_o (PAD)
Source Clock: sclk_i rising
 
Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 20 0.525 1.394 Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)
LUT2:I0->O 2 0.250 1.156 Inst_spi_master_port/spi_mosi_o_SW0 (N4)
LUT6:I1->O 2 0.254 0.725 Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
OBUF:I->O 2.912 spi_mosi_o_OBUF (spi_mosi_o)
----------------------------------------
Total 7.216ns (3.941ns logic, 3.275ns route)
(54.6% logic, 45.4% route)
 
=========================================================================
 
Cross Clock Domains Report:
--------------------------
 
772,29 → 818,41
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
Inst_spi_master_port/spi_clk_reg| 3.682| | 2.224| |
gclk_i | 4.633| | 3.198| |
pclk_i | 3.012| | 2.135| |
sclk_i | 4.633| | 3.198| |
--------------------------------+---------+---------+---------+---------+
 
Clock to Setup on destination clock gclk_i
Clock to Setup on destination clock pclk_i
--------------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
Inst_spi_master_port/spi_clk_reg| 2.078| 1.855| | |
gclk_i | 5.267| | | |
Inst_spi_master_port/spi_clk_reg| 2.078| | | |
pclk_i | 5.283| | | |
sclk_i | 3.198| | | |
--------------------------------+---------+---------+---------+---------+
 
Clock to Setup on destination clock sclk_i
--------------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
Inst_spi_master_port/spi_clk_reg| | 1.855| | |
pclk_i | 3.244| | | |
sclk_i | 3.764| | | |
--------------------------------+---------+---------+---------+---------+
 
=========================================================================
 
 
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.29 secs
Total CPU time to Xst completion: 6.39 secs
-->
 
Total memory usage is 188108 kilobytes
Total memory usage is 179340 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 26 ( 0 filtered)
Number of warnings : 28 ( 0 filtered)
Number of infos : 24 ( 0 filtered)
 
/spi_master_atlys_top_guide.ncd
1,3 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
###3828:XlxV32DM 3fff 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12d0eNq1W0mSM6kOvkwfIJkTO/oqFQEJRPSma1HLP+ruj0lDpp22q/x6UWUssJiE9EmC5fKXSvaiwnq9fqpNXZbL9ftLx1wL8s/fpqyXSr3+Lb29CGFrnVxbI9Xq3GXL1/pp2+dHWfsvQ601f+oPzEUsy/zlKDgorL3w0f5Vhm4jhmkZDOvnRwm9u8i6K7O7Umt9ry1joI2nXkzjuTW6Z4NMYvIU9Vex1prF80HC9EbBQWHthcpwzNpBRw46cr2jAitVO5C1g979ukBrO1pn3RcnEZO2mn14apNtTPX3yGgu+YpL7udslGid9G1pnaXU1y/BL/0l1RHXv8bPE3XyM8DPBRiHGcNLnewX1s0yu6kbkdqiyQVmmnPfbyHaAuhtTrX9qE3lI6s+ZMF4icmrbkAa68OG3Daz/rX+NzaRNj3ZB+sYtXEQnYNh1DbGIUor9TqEZe38Uxcl5WmobQZpiFBm8yptXmsnWyK3wQjRV8GxVWijEaKz9oxJG44QjXf7huS2CR+wAZ417+S2LDauJJfazsMzCw4Kay98tH/fX8KsndNHynONVacO/h8lTdGv1O9otLiIS7ioS/zzr0rpYou4/qW27WLj9S9tdZUPc/3c2om7/rO1sXftoNV2rd8LfY/1e1rou2/fBX0P7buk72v73pXLZzKdez3787Ot8zVK077r+rf86UPSKl3rIPUlrm1s4iLrya41bdRpjDZvnI8an6Lz+6xi3XVZNKUVLGecB2MR/eBsoxyc3SIG57oubP4q2N38VTC7+augdvNXQe/mr4Ls2lXOEWlxmKpe5oicPY7ImDkiue/BH3pwtMKoxqVCNW66wNe/StVqnv665OP0m66cPJGncjKgnPqIGyMthhxvkYt3/wlp9KFfkc6UqAGtbIZS0IId6a7HoFbOWlQDpDIMUxlCEhXVgDBhHgo1uXTxb8dLXNaLvHgQfznFfyPx38l9PMj9+kTuy0HuA+wKnaPPZHeCb3SbmLsnDWk9SoNaSRq4fIaDfLqDfK4H+dwO0uN341QhMjQQh1pSfIRijlCJwwhtmZqkmPMz+aUdCGadfDdOfW+6bhy9zToUDgvS2arJZKGk9d+TpFmUi8YEZMhKRVSUISsCawsyZGVibeHs2MgGDrb2O0phumLVlwCSpaZkJaZY584n11cj6/4tr/f04WfFMfN7Ht/lXEuph77so9Z3NqVO6qgvPd+TJ/pSinhkHCfj/Cbj7cC46rbBOL3JOB0Zl8l4e4fxlw1T7bUemnR+1NXvWscQfYBBqXp7gH11qqP9knd4s27aQJd1kWdhg0LaqUqhiRUDtjYWzmoBVguwWoAVamMLELW3bKPKHeAIRWTCqBaQTO+gtU6OK9pGxvNXbVkoVfJFtQr1H8i+nrKfb0EFV47+nnIcpyF5JOtua8MgTyYb1cpWmwZ5nJTSj9c/ZcVGppnnjofrRyDy0siReOX2nfFuWrIk+l61ezRRHJUhqOv1xnhrxYy3PKjjM3Vrwo1BCNCDPvYg0hODMO3AXv07UP83mKFv6L53o6F3c9N7uN/7duidpvkahqFJEJgZC99Ub+QYRBTQ3nXg5IYmz6jgLYqyERU9TJ0So4KPKLpgdGpijssiGRU8MFEyozar0E99YNQ+4LT2xrw78Bh1Koxa25bU57wQtbMornNOtBTo8eksqD90esZ+QluwhDor1hZcIZ34nKfj10Sibn4VifoHJ9zME17YCZ/qs6pRR0csXRuBHUXbCX62ZIcx9Ao6jcZ1Ah1H49vxC/oonoDmXfyxeB7R0l484/Xxqd2LZ9Cwdpq7ejZ7opOrp7xlZHQvbXaMjO6l8oaR0b20mZHJdVWeDQU99e+oWkBhj1Ls2Ee3/EcoRfl0glLsVCZKiN/YfNXN1D2UYvWbjMsJSrHqPcZhOUEpVr7D+EutEzC3HhhKaduNdIZSFISy2lTvoZS2aR2TtEWehTILYefQKc9YMZRiUuGsFmC1AKsFWCFKURBv6S0RpeA5aWRCKQrCP70DRCl4ThqZoxRjjhrMTckXzzSYO2qwFTXYTnOFo46LO801Vdm1j+VEg6V8o8HifQ22HjSYvz62tO6gysKdaMEYWFMbxnANptxCdKbBMEBmDNNgyilGJg22akZGDaacIDLTYCsbCtNgsi77QYOtcx/Vf+Zn5TM/K77ptZQzPyu8x1guZ36Wf5OxOPOz1jf9LPCnpNj7WZ7oOz8LnCO5nPhZGbyqqbh6y1EQez9rJVb3/awMXtVUXIPVAqzIzwroUJWdn+WIzPysgA5V3vlZlshMg7Xmtbd82S5Sg+z7KfuaR6+OsHsEb7syOI/JzgPDvKzp8nTFwlwiC+4Wd84oYKb1FQ8cc8CGZ3XjgA0Ha/h0ZRzDkk5OqdufVq6h/VMNba+vg82mAiRXBdXlC4cIMrl8202ErjCN/cAFehq9rVtuTzSPjDdRt5+cYxO343zQwbyxQHp5OJ/t+hgzhwNm9rvAYnAnKlBub83QBn/UVLB0+Ybxj5IJPf5nOGM5l84vN8mEeD+ZoA/GWh5kgqcKesbQ3vXGy81WbQ+3yh27uSNx64nlkOnN/TjGFM3caLW8tx89+7jbjw32Q97sh7u/H+ZsP1jyh8u02iVzuqGw9+CcF0936AS+ueuLnuhu88KJdZblnc37shKyzzGPtHBMFD0xEWMREMoPGMqHeGgjceOK0YeYKDpD3mzMFMnB6GVTFiyVjrniqsxmtw66xUBIrcNwjFWKUSF0Y0ViVAjzWOkYFTLgVjAOGGDBgGnT15SZ0B7iUtV6zAHCFQrKQ9Q6jN9QHqJRKWeRGBXTIRgualTMWWDWo1JZfqOw/RNz/yDOZZVhtXLWQljKSrh9UQ/a2PvCAxDdUkK1mNUI+q3MrFrOagp2AGBq6mHCux6c8onoIxNZfz8ykdq3Abmx2h2F9X0fBQ+FFQoRCmGXn4y4ZX52EDOkOiOubIF9CyjPEn4XOB4duBMHBcI4Ch4KKxQiFMIuZYWBojpZul9BEaFYmIeEqYnWAbuPIkxkmf+Y4D7AOC3ddRu7MDKi2QxUuV6kBFQZJqo0JzlRf8iJlkNOdL0PNx+kQnm030O0nwNOBkgVANI9DpVPcOiEnxTIHzh0F/8f+YDtkDZgnfRg5pn/KNz8XI/I9FGoID2NeraLWYhE+67fzRW7m7sMyr4WO9iuj3HCSyniXE6wqnoPqnYMfDcX4tKrEz6Ge+NZcvxxNmIPXctyAl31mxN2Z+kXl59OeD/P8FpYezvMc93PU5xAQvPmPNfTOH757TxPgl/bkzj+YWPlWZj2PRSF1j0Idp8AkUAQzGKjzQ+CWXdKEbFbM2TzA8vvKC8YFTNEKxvDsG25IGgCrJYLgzFWYErIUqKI8FGwDAlJZO8YrFOS2jIslVlbBHuC8UWMpteNqGPYZZnDVp5zR6xHqTDLUF0G810WHonJFsiSW3WNFwPDCt1K7FZTHbvAJwwjs6wOJzN4VBiZgSrWmll8KRkZ8QHGvPpWLrA4oyCgIPdIQ8OEBYflul+1RVYLsFqA1QKsEElpvJUVHKyRwDVSVIcpTSs8oyLOzLztHpsCdXoc37GN8xDNjxOz2MfXGMuTa4zrk2uMd24sxLFq92yyXG40tomvmajwxCH019cvFFBqsg0VVQ9uT6ei6smMeqt6OhVUDyqZTgXVYwAkdyqpnkhUzN5/R2VaTrLqxvqRYTe3uZvucVwznl2+22/Seh9oqgPQ1NefRT6PiNMwxHl71USdXTW5uWFyB1nOzAUHkgmBJODHA2y0HDb2K9R3A5j5NoCZHkaRwplx3Qug4zZVWXd2gVCLx7nPM/jgTnFhvrkGoH6ZRHsW23x0XaXO+ebSZIQ5L7+cszmLBebww13czvTJwxn5w4wACgpVfjkjfRY7y/63M3pFHMNxIgUmkn8zkS9lINVu94EBBzDBjUshvcEwj8YkqiMIYYxlZIQQxjJOBCGM3RiZ0qp6ITJBCMrw2xmeaFI6Cx4Ku6iEguG0BjzD78A0OwMz8zAzK6mO7jKZwKhg+I11jIoPdGxkVAg1KlWIivhSGQ0jXBmqGxqiN7YwwBWX3lMd3ddCfO0Y+DSWtUWoq4yETh2/jowpdOeYRTQbo4JFVHg53zFkbfC1i3MwbIfrqhgftMIqERXtuLErawt23BjWJ+JiY9lS0bUvqfvVzur4VJ8MTHOapnk9mmaOmB4gquMF+fggKvQ8G3m8/Hliinm2MRyiQA9s8mmwJ5ru/d81qPHmiqZafhf0356k0nYBGNkl714AJqq3kv4ml7NkYVRPp/rY6rgXrI409iTQEuWbEztNrUXx6h4e31mEJ3Z1NzF3ElmB7n95m0JqULRVSkkhdN2v25scePNo4M2jcVzl6wjqO8+MTm8wVFB/8YNcFuCyABd61anh1rlxu5eZGIPILAshV9Ynvf30nIqPK9GDzInMi8SIRy7sbSRc7+hU0PQ6KqLOGeLzVo1vmvjTTakTdUrPT3UkRvTOUG/AYve8Eh+95MKeVa58hHjPmN50Lux5Iz16XPhTSN4W30thKKVR0Q2Lmqhz5vNVaMsg6nm7agN1n6e69ye5gPBDh3o7c6jhXSC9jto/D7QhnTwPVPLNDLI8ZJDxeaDXr2aQ9VsZ5E2cGROvXs0gh/9LBnk7C+KL92KfGSS0zplinxkOz7aLfcLL7dq2Zxw3HgPtLi/UilmLsVCZWK2ctZhJhVtmTZbYu0fK3ybINkpIBm6ChjiTgRsmAyGKFrZd3ndmTDu7kXzcbh9HYgPgSfpXTMdgvF7c4PWi6TfA8kVeME5S5ukMP4t6sYTP/wCoJ9N0###5060:XlxV32DM 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9o105J9ltXgjwD3eqBeGElurloeK/duw/wPa1sgi###5024:XlxV32DM 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18f4eNq1W8luLTmO/Zn8AI0x2Hi/YkBDCKhN5yKXRv57i+Q5iriu50I3XLmwpaAkTqIoitId+/vff+V6vLm38PlLKrGF9w/vBL4dfsKjwXt4n+Uu5cdo0rp3tPb81p20nlJ+eH/q4O3R7NHspbloc37g9sA9m0dV3O3R6tA6cQ8ZG1q6W9uw1ll+DCPsTJptH2/J5fePvk1wKh1C9m0KGd+13XtruzikKmh22lUTwsqjzdBlBVeKt5tuJlrRTddBR3gIHyC8KNabeOMx2GPwFH7+yeAEikc0ij4EFTs+RjmMmkqZfzLq0apKma2ilPknErYbJyTMkFB4w/SfqpkPaEUxJki+OdOYVYSzWfmQf3//5fegGD56BFdRodGgo2MCDWrSTSINepngv+uWw5t/K2/prXz+T+z9bQ/j/Y/Y2luN73+kLU228/ufXazq/V9Txln8eSX9ug4tvHMotdOf3jV8X/Ydon0HHTZJChapu0+llJJ/n7QnqSEk/dtWg/DQ37ZpWsrEyE86wOeN3pwrKUWW4yviaoiD+yHi8wvinIHY/xBx+Yp4AHH4CeK/Qs0wvElB7GoacxJzzeGGw8ij9qfxT1Gtv7vESJ1IngW+v01q0wanklE5WSlamUM2JeFvVEbCteXuFipHVI6oHFGJM3NOuYpEdRhX16EU3A1WClfS3ku23Xp3dadp3ODlmET31xfLjw6Wn/4py9/iN5Yf4s/saEvfWX76IeL8neXnHyLevrP87YeWT/ObFF4s/7rhL5ZPY5qi/tby56SZnYtJWCWzsr1afr9RvVj+CypHVI6oHFHdll9otGqHt+W3G/yw/LWRbvFp+bne4Kflx3+zfA/Lz/+U5afvLN//0PLTd5bvf2j56TvL9z+0/PSd5fv/luWnV8uP1w3/reWnbyw/0fITLT/R8tOr5cd+o3qx/P2JyhGVIypHVL+x/PRi+bHd4N9Zfnqx/Fhv8NPy079ZfoDlb/9YtPOt5dcfxg7fWn77IeJvLb//EPG3ln/9lyw/v1p+um74by0/f2P5mZafafmZlp9fLT/1G9Xvox1afqblZ1p+/sby84vlp3aDf2f5+cXyU73BD8vPwU/L9+VtBlIXbT/C9vfb9v/VhIk/4lwCKY73uQjc/X3It7+/m3yH+/uU73h/l/d7LZUFTtqtGrjd4E3A/f4O8n3d3/l9rcVx3uBrdhsP7F2+Dfu4seco4Ad24f3bteyPe6AIPc/WN2BXQEHPejd0bXjQFPnhD2rWY+T2XK4Oxn9+3VD2UGD94TkhsbSXCYllf5mQWOrLhMRyvExILFPzf0Zl5F1MYvvGM8Wf7cm55a+iFoq6/79F/c8S7l8kLK8S7t+4yJh+KOH2RcKcKOHxf5Xw/DKZa3W9Sti+SLi/Snh846tj/qGE+1cJL0p4/sMS1lcJz282jfizcEk8ouVfwvncHFLBoVNUoBkr6WC5mXWIkLauKZv23GcUvPJNweUH+M7BxWfvlbkLzt9gySBNL/Tck2S56g4kVo3Kwcr53JNycJTseO5JqbgnKkdUjqgcUa09KZVApjYq41jK6HebKGP054aoUGYtg0sP6Mo3xmfflWd07oau/GL2g0Ltj23Qj6XMeOfdVvwn0JWrCy48oCvvl559mUpM57ihEHxbgj9HTME1w5Y9OQnbIwHqx0KUlcFenuGsQJVBM5j4gAqD7RkAKFQY7M+joEKFiUvny99QsG3JkL/nkI584Sa5UfmKTSOM7gn3AvcL7giXaGV+Ad4G4JLwlC/CL8IvgV8L3gnvAu8L3ghvAm8LXgmvAq+AJ/KfhP+0+E/kPwn/afGfyH8S/tPiP5H/JPynxX8i/0n4T4v/RP6T8J8W/9lZAv9jVqai3UG4z4DPgOqXfBGeCE8CTwseCZcJ83HBA+GSy/ZhwT3hksT2fsEd4bKSvVt8DvIpCWo3Fvwi/BL4mi/mlWdFss/LTnbayS52si872Wknu2arl51stJNN7GRbdrLRTjaxk23R3Wgnm9jJtuxko51sYifbspONdrKJnWy0k82RTyd8usWnI58afbuln0H9DNHPWPoZ1M8Q/YxrwTvhkmIfyx5GI1xy7KMteCW8CrwueCG8CLwsPqkHJ3pwSw+OenCiB7f04KgHJ3pwtx4K4UXgC/9B+CHw44afhJ8CPxf8IPwQ+LHgO+G7wHeul8F1OmSdjrVOB9fpkHU61jqlfpLoJy39JOoniX7S0k8aJ+GnwM8FPwg/BH4s+E74LvCbz43wTeDbgmfCs8DzgifCk8DTgkfCo8DjgtP/DPE/Y62LynmsMo91zWPlvFSZl7rmpW6EbwLfFjwRngS++NEbpOPTUBuNy66fUjvsKinHHXdKJyBh7rZybNbKy73T3Jh24+BXOGd4EAIxVvWOBSdOAUlbGDvG+Siaj+Pzlz+a7FJWXlbK6pFSr6T86ayDlJeV2mGW1uHYgWEHhh0YdnQoIFGMRPR6yWUlvmWAlDog+o4OHR06OnR2SOiQ0CGhQwLJBl4aeKmG0dv92q8wfa20h1Ts+zBKUqrvSF7h2wyz5FtKRbwVo6z6FkC6qrFypLu8OA/ibhLUIFNskGgKCy1YbCcV2dmkZEM/UQIuK0fLjoF+Z2WiDLspQErjc1qPCiClsFOmwLuZTsdlrwqml74azXTeTM191O9zgcW5YSD/cl129Sn6MpaPjnvTqSmDpPFmsalFxmnaeRbXJnbuLwlsN5sQq5wVlSuhMjwqc7IAiYScVpFI0SqhETJQUdZ0FIanjqZ0Ac92oSkeB0ZFxwpJHOhjkunCZmefMfxcEIxSAzES7JPZJw32SRyeKAXFOYmnsnOgFFclQkfmOTwW4iGtkFmhyGKHWvHoHNk5po0VNu3URsE0hbb00wkhz4VEd/CzLbVQ0i2xc6xsIs8NHEa39MPKRmU2iJMpl9qrVjL7ZAoYWUkXR9kMTpNMfLoxKxK8iuZ1yc3gU4P5EGni07JkpWjPC0vrpJSSyhMLmVqRpSIhgNi3+pMGf+JRdisH4OKV1bokuFWHg+9RaXWNC+sA/WHmI2G1lt1KRRngHNQTFYii5zTP45R4MWd2q2eeoK9MvP+0IGVxDk61r5TgWBlTzgs4xsrXAcL5Sc53cl7hPD04ZtnAOXSv38q5nq/07YzxVR98gb6poaxviTqML9BfLhwKvBL4O8hWAVtUJByWYRyGUdjqZEtP/glvSMQmrgPMXEClz176Rqd5PZymJrkDTg/GerBp0LNxDuPRkm39apY4pHRTFN9rXeDe7ITad5IcIHnocyRpwssVORLeTV1PsEJy+zS9wm92Tp/uJbIiBtRQYPcaR2j0w6G7Db0iXSY3A62chCBtIVtHe0rkQPmg67UoRkSqnxYKr9mn0XmUcM6Ej0LuuRoCyspJ3LEq9FzemYCf59ClHEuCxBM8ikSBxnTCw+pspobkh/WBgV1Rw70DwyfEAjQ84tJSMxOdtxHzcLyIm/FHPVVM/WpgXLF5i5lJi6DREp5SN+/pFjUjs53RhuqIge0+o+zwyGL8OqTBo9qaK8WSThp3k2x3HFThqwMJqhLP4yaoEp4qoZWNYw8MOUlQA4xj4ObltOdzWlYrr8ixHKOBRzpp0dL3sD1Cb1/s9ZdqbXuwX2xj6dgqOqJl5URDnWNd0ei9P71N9TZmbiYaJkWU6cLCPJuF7moZARa4/PUJy+MaUA3MndeM4DLbFUus6z5JybebvPgsIS9+RshrmS5Iq3o4Pu1wVuk8dW40YrgsYlC1BnN8Sjfaxr/Ksm7ZlH6/6evuY5vpxc304mZ6rcs8HXY9hikPMkzWhA7TSrqwcOyRRfzEru7uh4ag5tYTIcU9MJszclBnM09PHTGBzkgONiN2hS140wPv2Mm7W5d98RNhw86wwVGu+zGT0JYECWmru5+0dVo2+5bBNh277KPz9CQVU0VpjBoZOQ1WKmIXPQBon8imi9FVQygmRoKoiAFTZ/znGIFVz0pa8c3OLd+yiiBv83Yx9tnNJ2pFD4TTqZl5X+IMvHoDKuHYH6LdJ5mDuJuJ1juPNieONs4E01Wi55EDxh+s1GUjcoqPETnFk6u8FsZU9Ky2HYv81hMrT8TXOCOmN80UB80TSfigOQHjvjy5P8j9aUxbHhGuSpn2KLMxz9iQpa4Fm5PLeGoodZuYpSw5YVHhk8WhhqIZDr9/WlbCODufnJ3krECvuv1Ue0KsZSWrFSwG6NeBxQG1Vqp1h1ob1drAqkNZwXKhek+o14H3QjWfULM+uNW0iQkTKczxFKZSmArePcp1/C2oiPWJMMr8dQtBoUahMAeE6RQGzNuIai5fhKkUpmAiBoSpFKZAmPthpa56f696m11dVo3nkIteQzekhrfhNleJcm3rbaeiDHSQ2ZyXoA7wJFbJgf5RUzFy8Kh4fqB6IdMaMdUEX5VOPLO286bjoVLSWHKg1ofRcsq1h8oXQl+tqKOevTWALXp4kL717iuasiMyMh36broEOyFtemHu+6cerHUFdYshpdTMnhy4xfrkwK0dZikdBKmGJ5eFb0oMcOyViF9KWHkXDQ0k/1KYfznteG2YMjAhzJBjt2KSBI2zbdF2wQGzO2E8uk96lDhpd8CVlrcgX/dLDXr0TYEfJrhdWdjRQQUvFPyEwA4ltKm4rr4UoVxdiLo3POhXgQPKBsErBYeghikDUwamDEwlIdxAZqeSpxOLQgRU3QVLdqnADakGVa63s5ZK3qzU/c8XOwpIz6mJBk0EaKJDE42aqNBAQNmhAYcSmhk0TSVeLehVDXiUSL2NRk1UaMChxPco1MQJTQRo4qQmKjVxQBPUQGWyBRLrUF8QYRdkxTTToytXsOvZr6RHk7qJkhDuX+e9qlSTlx1Kc2F+rlgKT/ruj74eGtrYdxm/JpZ5BS4kNSKRJlv0vBCWJg2UtEnPJ1c2CoYRw27joe7QmdGQ9KGhVSa2ZIoP20myrVUh7Uk6U0cBuZKtuEebu9gmDsXzJyiSa5YDgGZtT2257haN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xO2TBvbtpCWoS3CXkC4xbyZ3XQKXkhVZV2QnIu+K/EQUXVE4MVPcvvFMPLYj3qqoo7rXnbRVcUfF/mWktZCO6l518lalHdW96MxalXVU95ozbVWu3oK22K3YVhYd2f2tCEpSa5IeoRbhFpEW0RaxFvEWiTT/ueHN60/KyDb/Vc2Hj/VguZwX09VnhD8vRvXv8DGFj4fFrJ5Un8liOVjWv35N4eekGsyrz6PHcjxdYEaS/NdosCy/yOkctprP8P9irn69zP5IPqvftZUq+ueBgr9+4efrm5gWHyVB50kIhSYPS9VgXI8/zwf633ha1dBmhPivKf+f5Gdy8t8vjPL/BzTtQPQ=###4980:XlxV32DM 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aQN6W/u9H/nMX+unTecDVqgB8/r8cErululrWMv8tYap7cmxgUfyiWma3udO7gW93T3+BzK90Kg=###4872:XlxV32DM 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DtIyXlBR+hPaR8XnWPWD84KOoRSdDg5RHKzisxGd/wehttqd###4496:XlxV32DM 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90ryGZh8dIZYmZkmEv5nLGPBbdK3Ur3tm9M4BPvW6wY6jJqmAPYq6+QDPBhe1M+thouQ1UJNZiWWKT1v0Ih6RWT4EQOvmeS5qF4Ex2CgvkD6tCFGAz0LpJdTYTx25vVBBCSCoxiN8zC2UfqUIdqLsngYrBkf9qQsugUCH6d7tj2nCmnxQet4MLLWYovsZWPM3D2809GHLpZ+ZaZd2W/XBjranrDlskbrTaO9Roz5WiAr1niWsJPeR8Hh2Gsn/uNyNPIJgyyH78qsXzP9M6neR8tfYr636bTebhlMzNVgvApPdu+FbPQgQbgaS25ibmuQalyy68qU9KZBIq2Lre5Lt8F9DebiLcuJ+dlgyulh2dxgRToySMHKVWmaoeRVA3PvkzaQic+GQweOskuyk5GONZFBOp+vqfyS3zAKOQnaMkDuZTMTdFVavz7u5YceK5MTQ3O9fm3GpxGC+42jrbEalbrjRdF0cI8QNFpyh90CPdtox1EvDoO4jzVBuOQOPoeUr9cR415D0ohhKMiVzU4BpWoype9c3ObFG98MSQQgRPRFoplWQE4dCxPnXVhjdbn6VFEzEmRi/VmD8WqiV7XY3koJuFQ43isLZ0mL2tdtz/VFiONRTzY88bYn2fVfYtUvNgYFiBsKc9WTmaljmsz70u7sLhRHCa8wbejFoSSBioxczwaSYJkcWhJb3kZmjiSFzgcab9mc/4jvUt7f6jIA0COf97e6QSHqf/L+Vtfbu21EIPnzVtfZA2zNSs3SiVUpfEStU90L0hmNcKq6IDpVe6dqC8Sp7GC72+p4txbNUSkZfFYLFbnLwsCb2ArN0yeUinEtDL1CqvZKTt6lQkvve8NxfMcDhQAODuHNSA+OyZ72FntNenJKZbstVJSvelJ/XC9SbZcGJbHTk2Iee5IKXegmURkcyEmCO+Gpg5tw9HYnYxGMfcaGYTFIZaimHrxsJpOvjWEYownT2/NqrwVglDTxvN31Fe/jkgB1bx1kSYJnuV2uTLDFSBLkagEZZGYmaW+MLrbMMJGJSBvY8k1S5xujwTdIg3iDeCPa06PDPpx9ePtAzF/i9pT0Yo2AOXBXDLttKoMYgxiDp/X2G0Zl7pTs8SYMTWkLRV+WjvdlKdKCWN32YvVkuWAe6X/+w9lj+n+ENPlO+ff/hhR+TWUUUNlB5QO6dtD1Ad076P6A6g6qH1DbQe0D6juof0DPDno+oLGDxg66jw10Hh+Q20HuA/I7yH9AYQeFDyjuoPgBpQ1UP9t7nzvo/IB2eZ3pA9rldX5H7fI6P1K+d3mdXzZ2eZ0fKd+7vM6PlO9dXudHyvcur/Mj5XuX1/mRcv3I6yPl+pHXR8p1l1f+SLnu8sofKdddXvkj5brLK3+kXHd55Y+U6y6v/JFX3eWVP/Kqu7zyR151l1f+yKvu8sofedVdXvkjr7rLK3/kVXd55Y+86i6v/JFX2+WVP/Jqu7zyR15tl1f5yKvt8iofebVdXuUjr7bLq3zk1XZ5lY+82i6v8pFX2+VVPvJqu7zKR15tl1f5yKvt8iofebVdXuUjr7bLq3zk1XZ5lY+82i6v8pFX3+VVPvLqu7zKR159l9f1kVff5XV95NV3eV0fofRdXtdn5/sur+uzvV1fHgAU3i38r4CUavyEK9zxik+KaaQSfIjpCiEcxxFbHDFPWIgjpRSDk+44EYOPPvj5vY8733GKkYCRZpztJrab32FSTKnMqP5fZkojuhljTegX7294+E/4fZIHB/4vx7kXQ/l9Uv7L1QVgLwzFXjMK7pBx4GQfmbd9aZjH/ZuRtvb+L6M3yN+NTmV+z4X9BZ3F/39EBxEQUu5wUru+GnSH62du9BlyuNPclpjnhOccXjBRxfQRm32+SlCBkfU7ymR9in+yMCn5+XdGYS3+LXYTvMnm/38+UoiXLHrqyqm9k97/AUHJ7b4=###1900:XlxV32DM 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b50eNqtW0u23CgM3ZKFwDYv6+gFVPwZZtajOtl7Y7BB2BJguyc5lXpCwNWVEEKlrV7MqhUqHLtOo560MaOezWpG9x0Y6/7t8r+4T6setHXfZaPN6D5r80rPrgXQCf/9+wf6ZfrpfobvHzT6B2b76180+KN+/YNG/YBdv+hE8eMV6H2yzk2m0TpVThaVNghu4utk4L/Plwpoj9GVpSJqJzP7xfYv9Ji45TdaIEKnMj3TGRP6F0aP9lrCeswLPR7bXZPf4yMLaWbcWXY1xmg3Xxe1qcyu03nsvirtkDQZWfOdEL1kDcQiZtATglt7x64d2dVfdr1rUY/nMQ/HecYEF5upi40nF7NtLiYv7rmDQXQwfEFFQyjdv6K0IpR+46xZlHusxUaHxxtuooibdCU38ShA1T1UleQF+lWIi4JjQcuc0bHw4TxP12cPt1qoW31yt/r0Rbe6AN0LIHYSFJyGCAlUtybH4+furKI7v9Gjo/O8Op9IUFCvzt0uuqF+FVw6Elz0Havyu5NXss+CFdfuZY4YVXRPdY+TXlvRTYvzeeSCw63O4TA4nMr9bYSvU/a5gDL6vDSBAqYW8c6bixpYyYWNQWEUeuddKrFOMaZMo8ukCqOnw+U8SGtHQJoykOz4df+rg6SqIJlmkIyHwMSsjY6yBCST8qWdL0qCNPJF8TGMPfZaIQ2jp8NLA6RAIF0e8Q6rkI7NkG6SSw2kXUIGyb4Cye4g4WbgAJJKIGGXg4RtIGlTT0egGaYgezioqjooD5TB8QVQYfT2N52AQgKUyoD6PX+xZ4DSfjr1IopFDZykwd1BSbLhgoDSEO/3xo+HKGsIx4Rx/tPvbLwivOyIq4O02ujqIERPztXTXmvRs4vR87gqrZoYRzex+Gyc+9FTNo4hDO7EUTuD3fco3lWHV0ANMSbCAZQhQPWPgLofE2WgRn83UOxZnOYNEg4ovQjnsWaTzlagwugQFyNQPQEqv3uPaxtQT+KiDBUIztQ36ciluYj3BkATAdTJJQcHoA4ALnm8BL1styyV3bJgDzboPWNBfQQr91kxdZggbaKEIafCNWsN0v0pseNPmUN6qJ4y6nwTiaNVKpIYEG8rh2U1M78SCgU64sNjoiImFEFZ2t6QZqxzPUqItM4PDjZGGQHBPPZJ5W0b764g6tENd2ATrTUe/B0Jf+HE36mNv0D4C1X+gnhqcPyts32oXmNUlb2qgb3DDfYOhGFQZS9Upe0NacY2bCLDsVeou7CFwlbWhdEB5fGNF1weZ1ZLuJsn9c4EG3ehyl1FboDn+NgnfPa0Up0qBk8xgfjugiI7W/SYWNVCM0rWrVQwDHsu5JxThHOqyue6NOc1KovLdZ/Fqs8W43Wx0giXdw2JObGiGRj5SYyc15yR3fhFy/KReqBUZdJVPHQDHnjDGkisgVWb16XtDekcaSQxDKsxDIWMsHvhZ2H0LDww3/F7Hf0+cua344zZOZPXb2BRWxQbWdZsEdOU4/YJK+1rmttO3FdHbpM9x5ylcb+6pGcNFE5ufaxplwgntymePPUdIBNlt+pGn6r5t/PONJ6V9Lu9Zoajf5ga498TdpKsviHbNcuGqnWrrDrLertfrdcdzNglDGEJb+sLj9xnOUvTRKJ8DnGepRtaN84n4dMsg3/fuasFY84DqbI2ET+fcz9f/TO3lfw886n6G7xJ1kxlVqEAccxiiTQSaf4EHYl0KSq07gCZ8y338/sZesnPB1JWzGOT9aNoKRGIj11lTdC1+1hNFptl04Nyi6w5y+6ee4674KWR+DkQPweWR0j8HE5dLldpOPWXIPsUIHD01rndEhXazu3hZZdUe1TIerZCVJhTAQ7m/EXscyq4X+YLa6r4heiTnKSzxsDGfDzu8btEOk/k3EGfCvKmeI/X1RMCxDpUW+5lY+4V0V8o+nPxPfJq7bkBfShU3ertMWwlJc/Hanf76F/STeddPjtGTOM5t6Y7EEwmw3TF7ymbVSn3EPjIP8J0l1MLbtQubWs2kM4fsXkLG/orVHyShEJ3ROrBqFXUuW49jCeR3Pak2baiA8eBsIrjYN1WwzFqY4JbDmVC/l41L18cGCag8FpqiH5g9zCSPZROHopV6eRB9hGarHGTqr58GIm3gmztDnSXeWH0JGa0tvnsstET8LAvEPvmj0fzejYvnUq6eCmxPQz3a090dTENsSTwFZt72cBnm4ua43HdENvJHqQEBT1PH1kqqEtrCgZW9HjMK6z95+sbCHNiHkVTfOgg2fgXDkL13HKQsG/SBAFTnpSNJn8WpZZKDzWHVa9t3oI8J8cU5bhgJvR/ib015dXc4n1AS1O01gaWHAfJ+CqM7uNfh1GN4zOWmB/4Afj6/Xa//Fc9iYinxoO1v+Y+ysPeF0LiwJ7DcNRf6aktVNuOWcyp2rYUpfvqqxDf3pJG32pveaEnkqiiZ2pqTYJL92vFRtKaAkUGyoc8A1rMNQNKluJapq4zDeKOzYt2rLur6MXxg+416EXIRp+O60q7rvBlIH3O8EIPydWPSv7Qkbd0mDG/yy/hNtmGs224/0r21hVr22Zr2+pr+l3UgDadsjeqVk2k3TDlo5Z6W47/9Am1lLadlzrbFHn7qnW2AduVf7bY/Z688sprvzW8bzVNrPZO0+l3ecFuH5pm5hUD2/FdaDEqH+tq+j3d0Bzbh0IfT01DLn3PGv0jDMftDRECglP8lar7fiLf9+T7hXw/pe9tt6U0KaOxiv7fG8Shs1lEXVLgkJVAuidWryqGyWqgcDemHsmj1z1OKMl4tvYwCNEg/bS4fGbBpfGzdaRuGLnxyX/a9y5JL3r71uk3Lmc8zfxkbcjasDYbPJ5NXqeEeMsP+EpaULxOqP9FCz7GYrwxvxaxsKIWyifplyjPRkb8/wPF/soT###2068:XlxV32DM 19b1 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/spi_master_atlys_top.vhd
21,7 → 21,7
-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board gclk_i to clock all registers.
-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board pclk_i to clock all registers.
-- this change made the design go up to 288MHz, after synthesis.
-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
-- external monitoring pins to the VHDCI ports.
42,10 → 42,11
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3; -- prefetch lookahead cycles
CLK_PERIOD : time := 10 ns; -- clock period for gclk_i (default 100MHz)
DEBOUNCE_TIME : time := 200 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation)
CLK_PERIOD : time := 10 ns; -- clock period for pclk_i (default 100MHz)
DEBOUNCE_TIME : time := 2 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation)
Port (
gclk_i : in std_logic := 'X'; -- board clock input 100MHz
sclk_i : in std_logic := 'X'; -- board clock input 100MHz
pclk_i : in std_logic := 'X'; -- board clock input 100MHz
--- SPI interface ---
spi_ssel_o : out std_logic; -- spi port SSEL
spi_sck_o : out std_logic; -- spi port SCK
71,7 → 72,7
--=============================================================================================
-- Constants
--=============================================================================================
-- clock divider count values from gclk_i (100MHz board clock)
-- clock divider count values from pclk_i (100MHz board clock)
-- these constants shall not be zero
constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
184,8 → 185,8
Inst_spi_master_port: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => gclk_i, -- system clock is used for serial and parallel ports
pclk_i => gclk_i,
sclk_i => sclk_i, -- system clock is used for serial and parallel ports
pclk_i => pclk_i,
rst_i => spi_rst_reg,
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
205,7 → 206,7
Inst_spi_slave_port: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => gclk_i,
clk_i => pclk_i,
spi_ssel_i => spi_ssel, -- driven by the spi master
spi_sck_i => spi_sck, -- driven by the spi master
spi_mosi_i => spi_mosi, -- driven by the spi master
224,7 → 225,7
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time
port map(
clk_i => gclk_i, -- system clock
clk_i => pclk_i, -- system clock
data_i => sw_i, -- noisy input data
data_o => sw_data -- registered stable output data
);
233,7 → 234,7
Inst_btn_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time
port map(
clk_i => gclk_i, -- system clock
clk_i => pclk_i, -- system clock
data_i => btn_i, -- noisy input data
data_o => btn_data -- registered stable output data
);
264,10 → 265,10
-- fsm clock enable,
-----------------------------------------------------------------------------------------------
-- generate the sampling clock enable from the 100MHz board input clock
samp_ce_gen_proc: process (gclk_i) is
samp_ce_gen_proc: process (pclk_i) is
variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
begin
if gclk_i'event and gclk_i = '1' then
if pclk_i'event and pclk_i = '1' then
if clk_cnt = SAMP_CE_DIV-1 then
samp_ce <= '1'; -- generate a single pulse every SAMP_CE_DIV clocks
clk_cnt := 0;
278,10 → 279,10
end if;
end process samp_ce_gen_proc;
-- generate the fsm clock enable from the 100MHz board input clock
fsm_ce_gen_proc: process (gclk_i) is
fsm_ce_gen_proc: process (pclk_i) is
variable clk_cnt : integer range FSM_CE_DIV-1 downto 0 := 0;
begin
if gclk_i'event and gclk_i = '1' then
if pclk_i'event and pclk_i = '1' then
if clk_cnt = FSM_CE_DIV-1 then
fsm_ce <= '1'; -- generate a single pulse every FSM_CE_DIV clocks
clk_cnt := 0;
296,9 → 297,9
-- INPUTS LOGIC
--=============================================================================================
-- registered inputs
samp_inputs_proc: process (gclk_i) is
samp_inputs_proc: process (pclk_i) is
begin
if gclk_i'event and gclk_i = '1' then
if pclk_i'event and pclk_i = '1' then
if samp_ce = '1' then
clear <= btn_data(btUP); -- clear is button UP
leds_reg <= leds_next; -- update LEDs with spi_slave received data
310,10 → 311,10
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the system clock
fsm_reg_proc : process (gclk_i) is
fsm_reg_proc : process (pclk_i) is
begin
-- FFD registers clocked on rising edge and cleared on sync 'clear'
if gclk_i'event and gclk_i = '1' then
if pclk_i'event and pclk_i = '1' then
if clear = '1' then -- sync reset
m_wr_st_reg <= st_reset; -- only provide local reset for the state registers
else
323,7 → 324,7
end if;
end if;
-- FFD registers clocked on rising edge and cleared on ssel = '1'
if gclk_i'event and gclk_i = '1' then
if pclk_i'event and pclk_i = '1' then
if spi_ssel = '1' then -- sync reset
s_wr_st_reg <= st_reset; -- only provide local reset for the state registers
s_rd_st_reg <= st_reset;
335,7 → 336,7
end if;
end if;
-- FFD registers clocked on rising edge, with no reset
if gclk_i'event and gclk_i = '1' then
if pclk_i'event and pclk_i = '1' then
if fsm_ce = '1' then
--------- master write fsm signals -----------
spi_wren_reg_m <= spi_wren_next_m;
/fuseRelaunch.cmd
1,7 → 336,7
-intstyle "ise" -incremental -lib "secureip" -o "C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn/testbench_isim_par.exe" -prj "C:/dropbox/Dropbox/VHDL_training/OpenCores/spimasterslave/spi_master_slave/trunk/syn/testbench_par.prj" "work.testbench"
-intstyle "ise" -incremental -lib "secureip" -o "C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn/testbench_isim_par.exe" -prj "C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn/testbench_par.prj" "work.testbench"
/grp_debouncer.vhd
113,6 → 113,7
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output.
-- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim).
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
145,8 → 146,8
signal strb_next : std_logic := '0'; -- lookahead strobe
signal dat_diff : std_logic := '0'; -- edge detector
-- debounce counter
signal cnt_reg : integer range CNT_VAL downto 0 := 0; -- debounce period counter
signal cnt_next : integer range CNT_VAL downto 0 := 0; -- combinatorial signal
signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter
signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal
begin
 
--=============================================================================================
/spi_master_atlys_top_map.psr
30,11 → 30,11
=========================================================================
---- Statistics
Number of SRLs added by SRL Inferencing | 4
Number of LUTs removed by SmartOpt Trimming | 511
Number of LUTs removed by SmartOpt Trimming | 463
Number of registers removed by SRL Inferencing | 8
Number of registers removed by Equivalence Removal | 4
 
Overall change in number of design objects | -519
Overall change in number of design objects | -471
 
 
---- Details
61,517 → 61,469
Inst_spi_slave_port/state_reg_1_1 | Equivalence Removal
Inst_spi_slave_port/state_reg_2_1 | Equivalence Removal
Inst_spi_slave_port/state_reg_2_2 | Equivalence Removal
][1017_599 | SmartOpt Trimming
][124_6 | SmartOpt Trimming
][128_7 | SmartOpt Trimming
][132_8 | SmartOpt Trimming
][139_9 | SmartOpt Trimming
][146_10 | SmartOpt Trimming
][153_11 | SmartOpt Trimming
][160_12 | SmartOpt Trimming
][167_13 | SmartOpt Trimming
][174_14 | SmartOpt Trimming
][181_15 | SmartOpt Trimming
][188_16 | SmartOpt Trimming
][195_17 | SmartOpt Trimming
][202_18 | SmartOpt Trimming
][209_19 | SmartOpt Trimming
][216_20 | SmartOpt Trimming
][225_21 | SmartOpt Trimming
][229_22 | SmartOpt Trimming
][233_23 | SmartOpt Trimming
][240_24 | SmartOpt Trimming
][247_25 | SmartOpt Trimming
][254_26 | SmartOpt Trimming
][261_27 | SmartOpt Trimming
][268_28 | SmartOpt Trimming
][275_29 | SmartOpt Trimming
][282_30 | SmartOpt Trimming
][289_31 | SmartOpt Trimming
][296_32 | SmartOpt Trimming
][303_33 | SmartOpt Trimming
][310_34 | SmartOpt Trimming
][317_35 | SmartOpt Trimming
][331_38 | SmartOpt Trimming
][340_53 | SmartOpt Trimming
][344_58 | SmartOpt Trimming
][348_63 | SmartOpt Trimming
][352_68 | SmartOpt Trimming
][356_73 | SmartOpt Trimming
][360_78 | SmartOpt Trimming
][364_83 | SmartOpt Trimming
][500_179 | SmartOpt Trimming
][504_183 | SmartOpt Trimming
][508_187 | SmartOpt Trimming
][512_191 | SmartOpt Trimming
][516_196 | SmartOpt Trimming
][520_200 | SmartOpt Trimming
][524_205 | SmartOpt Trimming
][532_216 | SmartOpt Trimming
][536_221 | SmartOpt Trimming
][540_226 | SmartOpt Trimming
][544_231 | SmartOpt Trimming
][548_236 | SmartOpt Trimming
][552_241 | SmartOpt Trimming
][556_246 | SmartOpt Trimming
][576_265 | SmartOpt Trimming
][580_269 | SmartOpt Trimming
][584_273 | SmartOpt Trimming
][588_277 | SmartOpt Trimming
][592_281 | SmartOpt Trimming
][596_285 | SmartOpt Trimming
][822_441 | SmartOpt Trimming
][827_445 | SmartOpt Trimming
][832_448 | SmartOpt Trimming
][848_460 | SmartOpt Trimming
][852_464 | SmartOpt Trimming
][856_469 | SmartOpt Trimming
][860_474 | SmartOpt Trimming
][863_475 | SmartOpt Trimming
][937_536 | SmartOpt Trimming
][940_539 | SmartOpt Trimming
][943_542 | SmartOpt Trimming
][946_545 | SmartOpt Trimming
][949_548 | SmartOpt Trimming
][952_551 | SmartOpt Trimming
][958_556 | SmartOpt Trimming
][const_100_161 | SmartOpt Trimming
][const_101_162 | SmartOpt Trimming
][const_102_163 | SmartOpt Trimming
][const_103_164 | SmartOpt Trimming
][const_104_165 | SmartOpt Trimming
][const_105_166 | SmartOpt Trimming
][const_106_167 | SmartOpt Trimming
][const_107_168 | SmartOpt Trimming
][const_108_171 | SmartOpt Trimming
][const_109_172 | SmartOpt Trimming
][const_110_177 | SmartOpt Trimming
][const_111_178 | SmartOpt Trimming
][const_112_181 | SmartOpt Trimming
][const_113_182 | SmartOpt Trimming
][const_114_185 | SmartOpt Trimming
][const_115_186 | SmartOpt Trimming
][const_116_189 | SmartOpt Trimming
][const_117_190 | SmartOpt Trimming
][const_118_194 | SmartOpt Trimming
][const_119_195 | SmartOpt Trimming
][const_120_198 | SmartOpt Trimming
][const_121_199 | SmartOpt Trimming
][const_122_203 | SmartOpt Trimming
][const_123_204 | SmartOpt Trimming
][const_124_208 | SmartOpt Trimming
][const_125_209 | SmartOpt Trimming
][const_126_214 | SmartOpt Trimming
][const_127_215 | SmartOpt Trimming
][const_128_219 | SmartOpt Trimming
][const_129_220 | SmartOpt Trimming
][const_130_224 | SmartOpt Trimming
][const_131_225 | SmartOpt Trimming
][const_132_229 | SmartOpt Trimming
][const_133_230 | SmartOpt Trimming
][const_134_234 | SmartOpt Trimming
][const_135_235 | SmartOpt Trimming
][const_136_239 | SmartOpt Trimming
][const_137_240 | SmartOpt Trimming
][const_138_244 | SmartOpt Trimming
][const_139_245 | SmartOpt Trimming
][const_140_251 | SmartOpt Trimming
][const_142_254 | SmartOpt Trimming
][const_144_258 | SmartOpt Trimming
][const_146_262 | SmartOpt Trimming
][const_148_266 | SmartOpt Trimming
][const_150_270 | SmartOpt Trimming
][const_152_274 | SmartOpt Trimming
][const_154_278 | SmartOpt Trimming
][const_156_282 | SmartOpt Trimming
][const_158_286 | SmartOpt Trimming
][const_160_287 | SmartOpt Trimming
][const_161_288 | SmartOpt Trimming
][const_162_292 | SmartOpt Trimming
][const_163_293 | SmartOpt Trimming
][const_164_294 | SmartOpt Trimming
][const_165_295 | SmartOpt Trimming
][const_166_296 | SmartOpt Trimming
][const_167_297 | SmartOpt Trimming
][const_168_298 | SmartOpt Trimming
][const_169_299 | SmartOpt Trimming
][const_170_300 | SmartOpt Trimming
][const_171_301 | SmartOpt Trimming
][const_172_302 | SmartOpt Trimming
][const_173_303 | SmartOpt Trimming
][const_174_304 | SmartOpt Trimming
][const_175_305 | SmartOpt Trimming
][const_176_306 | SmartOpt Trimming
][const_177_307 | SmartOpt Trimming
][const_179_308 | SmartOpt Trimming
][const_180_309 | SmartOpt Trimming
][const_182_310 | SmartOpt Trimming
][const_183_311 | SmartOpt Trimming
][const_185_312 | SmartOpt Trimming
][const_186_313 | SmartOpt Trimming
][const_188_314 | SmartOpt Trimming
][const_189_315 | SmartOpt Trimming
][const_191_316 | SmartOpt Trimming
][const_192_317 | SmartOpt Trimming
][const_194_318 | SmartOpt Trimming
][const_195_319 | SmartOpt Trimming
][const_197_320 | SmartOpt Trimming
][const_198_321 | SmartOpt Trimming
][const_200_322 | SmartOpt Trimming
][const_201_323 | SmartOpt Trimming
][const_203_324 | SmartOpt Trimming
][const_204_325 | SmartOpt Trimming
][const_206_326 | SmartOpt Trimming
][const_207_327 | SmartOpt Trimming
][const_209_328 | SmartOpt Trimming
][const_210_329 | SmartOpt Trimming
][const_212_330 | SmartOpt Trimming
][const_213_331 | SmartOpt Trimming
][const_215_332 | SmartOpt Trimming
][const_216_333 | SmartOpt Trimming
][const_218_334 | SmartOpt Trimming
][const_219_335 | SmartOpt Trimming
][const_221_336 | SmartOpt Trimming
][const_222_337 | SmartOpt Trimming
][const_224_338 | SmartOpt Trimming
][const_225_339 | SmartOpt Trimming
][const_226_343 | SmartOpt Trimming
][const_227_344 | SmartOpt Trimming
][const_228_345 | SmartOpt Trimming
][const_229_346 | SmartOpt Trimming
][const_230_347 | SmartOpt Trimming
][const_231_348 | SmartOpt Trimming
][const_232_349 | SmartOpt Trimming
][const_233_350 | SmartOpt Trimming
][const_234_351 | SmartOpt Trimming
][const_235_352 | SmartOpt Trimming
][const_236_353 | SmartOpt Trimming
][const_237_354 | SmartOpt Trimming
][const_239_355 | SmartOpt Trimming
][const_240_356 | SmartOpt Trimming
][const_242_357 | SmartOpt Trimming
][const_243_358 | SmartOpt Trimming
][const_245_359 | SmartOpt Trimming
][const_246_360 | SmartOpt Trimming
][const_248_361 | SmartOpt Trimming
][const_249_362 | SmartOpt Trimming
][const_24_36 | SmartOpt Trimming
][const_251_363 | SmartOpt Trimming
][const_252_364 | SmartOpt Trimming
][const_254_365 | SmartOpt Trimming
][const_255_366 | SmartOpt Trimming
][const_257_367 | SmartOpt Trimming
][const_258_368 | SmartOpt Trimming
][const_25_37 | SmartOpt Trimming
][const_260_369 | SmartOpt Trimming
][const_261_370 | SmartOpt Trimming
][const_263_371 | SmartOpt Trimming
][const_264_372 | SmartOpt Trimming
][const_266_373 | SmartOpt Trimming
][const_267_374 | SmartOpt Trimming
][const_269_375 | SmartOpt Trimming
][const_26_39 | SmartOpt Trimming
][const_270_376 | SmartOpt Trimming
][const_272_377 | SmartOpt Trimming
][const_273_378 | SmartOpt Trimming
][const_274_380 | SmartOpt Trimming
][const_275_381 | SmartOpt Trimming
][const_276_382 | SmartOpt Trimming
][const_277_383 | SmartOpt Trimming
][const_278_384 | SmartOpt Trimming
][const_279_385 | SmartOpt Trimming
][const_27_40 | SmartOpt Trimming
][const_280_386 | SmartOpt Trimming
][const_281_387 | SmartOpt Trimming
][const_282_388 | SmartOpt Trimming
][const_283_389 | SmartOpt Trimming
][const_284_390 | SmartOpt Trimming
][const_285_391 | SmartOpt Trimming
][const_286_392 | SmartOpt Trimming
][const_287_393 | SmartOpt Trimming
][const_288_396 | SmartOpt Trimming
][const_289_397 | SmartOpt Trimming
][const_28_43 | SmartOpt Trimming
][const_290_401 | SmartOpt Trimming
][const_291_402 | SmartOpt Trimming
][const_292_405 | SmartOpt Trimming
][const_293_406 | SmartOpt Trimming
][const_294_409 | SmartOpt Trimming
][const_295_410 | SmartOpt Trimming
][const_296_413 | SmartOpt Trimming
][const_297_414 | SmartOpt Trimming
][const_298_417 | SmartOpt Trimming
][const_299_418 | SmartOpt Trimming
][const_29_44 | SmartOpt Trimming
][const_300_421 | SmartOpt Trimming
][const_301_422 | SmartOpt Trimming
][const_302_425 | SmartOpt Trimming
][const_303_426 | SmartOpt Trimming
][const_304_427 | SmartOpt Trimming
][const_305_428 | SmartOpt Trimming
][const_307_429 | SmartOpt Trimming
][const_308_430 | SmartOpt Trimming
][const_30_51 | SmartOpt Trimming
][const_310_431 | SmartOpt Trimming
][const_311_432 | SmartOpt Trimming
][const_313_433 | SmartOpt Trimming
][const_314_434 | SmartOpt Trimming
][const_316_436 | SmartOpt Trimming
][const_317_440 | SmartOpt Trimming
][const_318_444 | SmartOpt Trimming
][const_319_447 | SmartOpt Trimming
][const_31_52 | SmartOpt Trimming
][const_320_449 | SmartOpt Trimming
][const_321_450 | SmartOpt Trimming
][const_323_451 | SmartOpt Trimming
][const_324_452 | SmartOpt Trimming
][const_326_453 | SmartOpt Trimming
][const_327_454 | SmartOpt Trimming
][const_329_455 | SmartOpt Trimming
][const_32_56 | SmartOpt Trimming
][const_330_456 | SmartOpt Trimming
][const_332_458 | SmartOpt Trimming
][const_333_459 | SmartOpt Trimming
][const_334_462 | SmartOpt Trimming
][const_335_463 | SmartOpt Trimming
][const_336_467 | SmartOpt Trimming
][const_337_468 | SmartOpt Trimming
][const_338_472 | SmartOpt Trimming
][const_339_473 | SmartOpt Trimming
][const_33_57 | SmartOpt Trimming
][const_340_476 | SmartOpt Trimming
][const_341_477 | SmartOpt Trimming
][const_342_479 | SmartOpt Trimming
][const_343_480 | SmartOpt Trimming
][const_345_482 | SmartOpt Trimming
][const_346_483 | SmartOpt Trimming
][const_348_484 | SmartOpt Trimming
][const_349_485 | SmartOpt Trimming
][const_34_61 | SmartOpt Trimming
][const_350_486 | SmartOpt Trimming
][const_351_487 | SmartOpt Trimming
][const_352_488 | SmartOpt Trimming
][const_353_489 | SmartOpt Trimming
][const_354_490 | SmartOpt Trimming
][const_355_491 | SmartOpt Trimming
][const_356_492 | SmartOpt Trimming
][const_357_493 | SmartOpt Trimming
][const_358_494 | SmartOpt Trimming
][const_359_495 | SmartOpt Trimming
][const_35_62 | SmartOpt Trimming
][const_360_496 | SmartOpt Trimming
][const_361_497 | SmartOpt Trimming
][const_362_498 | SmartOpt Trimming
][const_363_499 | SmartOpt Trimming
][const_364_504 | SmartOpt Trimming
][const_365_505 | SmartOpt Trimming
][const_366_509 | SmartOpt Trimming
][const_367_510 | SmartOpt Trimming
][const_368_514 | SmartOpt Trimming
][const_369_515 | SmartOpt Trimming
][const_36_66 | SmartOpt Trimming
][const_370_518 | SmartOpt Trimming
][const_371_519 | SmartOpt Trimming
][const_372_522 | SmartOpt Trimming
][const_373_523 | SmartOpt Trimming
][const_374_528 | SmartOpt Trimming
][const_375_529 | SmartOpt Trimming
][const_376_530 | SmartOpt Trimming
][const_377_531 | SmartOpt Trimming
][const_378_534 | SmartOpt Trimming
][const_379_535 | SmartOpt Trimming
][const_37_67 | SmartOpt Trimming
][const_380_537 | SmartOpt Trimming
][const_381_538 | SmartOpt Trimming
][const_383_540 | SmartOpt Trimming
][const_384_541 | SmartOpt Trimming
][const_386_543 | SmartOpt Trimming
][const_387_544 | SmartOpt Trimming
][const_389_546 | SmartOpt Trimming
][const_38_71 | SmartOpt Trimming
][const_390_547 | SmartOpt Trimming
][const_392_549 | SmartOpt Trimming
][const_393_550 | SmartOpt Trimming
][const_395_552 | SmartOpt Trimming
][const_396_553 | SmartOpt Trimming
][const_398_554 | SmartOpt Trimming
][const_399_555 | SmartOpt Trimming
][const_39_72 | SmartOpt Trimming
][const_401_557 | SmartOpt Trimming
][const_402_558 | SmartOpt Trimming
][const_405_560 | SmartOpt Trimming
][const_407_563 | SmartOpt Trimming
][const_409_566 | SmartOpt Trimming
][const_40_76 | SmartOpt Trimming
][const_411_568 | SmartOpt Trimming
][const_412_569 | SmartOpt Trimming
][const_413_570 | SmartOpt Trimming
][const_415_571 | SmartOpt Trimming
][const_416_572 | SmartOpt Trimming
][const_418_573 | SmartOpt Trimming
][const_419_574 | SmartOpt Trimming
][const_41_77 | SmartOpt Trimming
][const_421_575 | SmartOpt Trimming
][const_422_576 | SmartOpt Trimming
][const_424_577 | SmartOpt Trimming
][const_425_578 | SmartOpt Trimming
][const_427_579 | SmartOpt Trimming
][const_428_580 | SmartOpt Trimming
][const_42_81 | SmartOpt Trimming
][const_430_581 | SmartOpt Trimming
][const_431_582 | SmartOpt Trimming
][const_433_583 | SmartOpt Trimming
][const_434_584 | SmartOpt Trimming
][const_436_585 | SmartOpt Trimming
][const_437_586 | SmartOpt Trimming
][const_439_589 | SmartOpt Trimming
][const_43_82 | SmartOpt Trimming
][const_440_590 | SmartOpt Trimming
][const_442_593 | SmartOpt Trimming
][const_443_594 | SmartOpt Trimming
][const_445_597 | SmartOpt Trimming
][const_446_598 | SmartOpt Trimming
][const_449_600 | SmartOpt Trimming
][const_44_89 | SmartOpt Trimming
][const_450_602 | SmartOpt Trimming
][const_451_603 | SmartOpt Trimming
][const_453_605 | SmartOpt Trimming
][const_454_606 | SmartOpt Trimming
][const_456_607 | SmartOpt Trimming
][const_457_608 | SmartOpt Trimming
][const_458_609 | SmartOpt Trimming
][const_459_610 | SmartOpt Trimming
][const_45_90 | SmartOpt Trimming
][const_460_611 | SmartOpt Trimming
][const_461_612 | SmartOpt Trimming
][const_463_613 | SmartOpt Trimming
][const_464_614 | SmartOpt Trimming
][const_466_617 | SmartOpt Trimming
][const_467_618 | SmartOpt Trimming
][const_469_620 | SmartOpt Trimming
][const_46_93 | SmartOpt Trimming
][const_470_621 | SmartOpt Trimming
][const_472_625 | SmartOpt Trimming
][const_473_626 | SmartOpt Trimming
][const_475_629 | SmartOpt Trimming
][const_476_630 | SmartOpt Trimming
][const_478_633 | SmartOpt Trimming
][const_479_634 | SmartOpt Trimming
][const_47_94 | SmartOpt Trimming
][const_481_637 | SmartOpt Trimming
][const_482_638 | SmartOpt Trimming
][const_484_644 | SmartOpt Trimming
][const_485_645 | SmartOpt Trimming
][const_487_647 | SmartOpt Trimming
][const_488_648 | SmartOpt Trimming
][const_48_97 | SmartOpt Trimming
][const_490_650 | SmartOpt Trimming
][const_491_651 | SmartOpt Trimming
][const_493_653 | SmartOpt Trimming
][const_494_654 | SmartOpt Trimming
][const_496_656 | SmartOpt Trimming
][const_497_657 | SmartOpt Trimming
][const_499_659 | SmartOpt Trimming
][const_49_98 | SmartOpt Trimming
][const_500_660 | SmartOpt Trimming
][const_502_662 | SmartOpt Trimming
][const_503_663 | SmartOpt Trimming
][const_505_665 | SmartOpt Trimming
][const_506_666 | SmartOpt Trimming
][const_508_668 | SmartOpt Trimming
][const_509_669 | SmartOpt Trimming
][const_50_101 | SmartOpt Trimming
][const_511_671 | SmartOpt Trimming
][const_512_672 | SmartOpt Trimming
][const_514_674 | SmartOpt Trimming
][const_515_675 | SmartOpt Trimming
][const_517_677 | SmartOpt Trimming
][const_518_678 | SmartOpt Trimming
][const_51_102 | SmartOpt Trimming
][const_520_680 | SmartOpt Trimming
][const_521_681 | SmartOpt Trimming
][const_523_683 | SmartOpt Trimming
][const_524_684 | SmartOpt Trimming
][const_526_686 | SmartOpt Trimming
][const_527_687 | SmartOpt Trimming
][const_529_692 | SmartOpt Trimming
][const_52_105 | SmartOpt Trimming
][const_530_693 | SmartOpt Trimming
][const_532_695 | SmartOpt Trimming
][const_533_696 | SmartOpt Trimming
][const_535_698 | SmartOpt Trimming
][const_536_699 | SmartOpt Trimming
][const_538_701 | SmartOpt Trimming
][const_539_702 | SmartOpt Trimming
][const_53_106 | SmartOpt Trimming
][const_541_704 | SmartOpt Trimming
][const_542_705 | SmartOpt Trimming
][const_544_707 | SmartOpt Trimming
][const_545_708 | SmartOpt Trimming
][const_547_710 | SmartOpt Trimming
][const_548_711 | SmartOpt Trimming
][const_54_109 | SmartOpt Trimming
][const_550_713 | SmartOpt Trimming
][const_551_714 | SmartOpt Trimming
][const_553_716 | SmartOpt Trimming
][const_554_717 | SmartOpt Trimming
][const_556_719 | SmartOpt Trimming
][const_557_720 | SmartOpt Trimming
][const_559_722 | SmartOpt Trimming
][const_55_110 | SmartOpt Trimming
][const_560_723 | SmartOpt Trimming
][const_562_725 | SmartOpt Trimming
][const_563_726 | SmartOpt Trimming
][const_565_728 | SmartOpt Trimming
][const_566_729 | SmartOpt Trimming
][const_568_731 | SmartOpt Trimming
][const_569_732 | SmartOpt Trimming
][const_56_111 | SmartOpt Trimming
][const_571_734 | SmartOpt Trimming
][const_572_735 | SmartOpt Trimming
][const_57_112 | SmartOpt Trimming
][const_58_116 | SmartOpt Trimming
][const_59_117 | SmartOpt Trimming
][const_60_118 | SmartOpt Trimming
][const_61_119 | SmartOpt Trimming
][const_62_121 | SmartOpt Trimming
][const_63_122 | SmartOpt Trimming
][const_64_123 | SmartOpt Trimming
][const_65_124 | SmartOpt Trimming
][const_66_125 | SmartOpt Trimming
][const_67_126 | SmartOpt Trimming
][const_68_127 | SmartOpt Trimming
][const_69_128 | SmartOpt Trimming
][const_70_129 | SmartOpt Trimming
][const_71_130 | SmartOpt Trimming
][const_72_131 | SmartOpt Trimming
][const_73_132 | SmartOpt Trimming
][const_74_133 | SmartOpt Trimming
][const_75_134 | SmartOpt Trimming
][const_76_135 | SmartOpt Trimming
][const_77_136 | SmartOpt Trimming
][const_78_138 | SmartOpt Trimming
][const_79_139 | SmartOpt Trimming
][const_80_140 | SmartOpt Trimming
][const_81_141 | SmartOpt Trimming
][const_82_142 | SmartOpt Trimming
][const_83_143 | SmartOpt Trimming
][const_84_144 | SmartOpt Trimming
][const_85_145 | SmartOpt Trimming
][const_86_146 | SmartOpt Trimming
][const_87_147 | SmartOpt Trimming
][const_88_148 | SmartOpt Trimming
][const_89_149 | SmartOpt Trimming
][const_90_150 | SmartOpt Trimming
][const_91_151 | SmartOpt Trimming
][const_92_152 | SmartOpt Trimming
][const_93_153 | SmartOpt Trimming
][const_94_155 | SmartOpt Trimming
][const_95_156 | SmartOpt Trimming
][const_96_157 | SmartOpt Trimming
][const_97_158 | SmartOpt Trimming
][const_98_159 | SmartOpt Trimming
][const_99_160 | SmartOpt Trimming
][100_5 | SmartOpt Trimming
][104_6 | SmartOpt Trimming
][111_7 | SmartOpt Trimming
][118_8 | SmartOpt Trimming
][125_9 | SmartOpt Trimming
][132_10 | SmartOpt Trimming
][139_11 | SmartOpt Trimming
][148_12 | SmartOpt Trimming
][152_13 | SmartOpt Trimming
][156_14 | SmartOpt Trimming
][163_15 | SmartOpt Trimming
][170_16 | SmartOpt Trimming
][177_17 | SmartOpt Trimming
][184_18 | SmartOpt Trimming
][191_19 | SmartOpt Trimming
][205_22 | SmartOpt Trimming
][214_38 | SmartOpt Trimming
][218_43 | SmartOpt Trimming
][222_48 | SmartOpt Trimming
][226_53 | SmartOpt Trimming
][230_58 | SmartOpt Trimming
][234_63 | SmartOpt Trimming
][238_68 | SmartOpt Trimming
][246_81 | SmartOpt Trimming
][250_86 | SmartOpt Trimming
][254_91 | SmartOpt Trimming
][258_96 | SmartOpt Trimming
][262_101 | SmartOpt Trimming
][406_199 | SmartOpt Trimming
][410_204 | SmartOpt Trimming
][414_209 | SmartOpt Trimming
][418_214 | SmartOpt Trimming
][422_219 | SmartOpt Trimming
][426_224 | SmartOpt Trimming
][430_229 | SmartOpt Trimming
][450_246 | SmartOpt Trimming
][454_250 | SmartOpt Trimming
][458_253 | SmartOpt Trimming
][462_257 | SmartOpt Trimming
][466_261 | SmartOpt Trimming
][470_265 | SmartOpt Trimming
][696_419 | SmartOpt Trimming
][701_422 | SmartOpt Trimming
][706_425 | SmartOpt Trimming
][722_437 | SmartOpt Trimming
][726_442 | SmartOpt Trimming
][730_447 | SmartOpt Trimming
][734_451 | SmartOpt Trimming
][807_505 | SmartOpt Trimming
][813_510 | SmartOpt Trimming
][828_521 | SmartOpt Trimming
][887_562 | SmartOpt Trimming
][924_592 | SmartOpt Trimming
][96_4 | SmartOpt Trimming
][const_100_143 | SmartOpt Trimming
][const_101_144 | SmartOpt Trimming
][const_102_146 | SmartOpt Trimming
][const_103_147 | SmartOpt Trimming
][const_104_148 | SmartOpt Trimming
][const_105_149 | SmartOpt Trimming
][const_106_150 | SmartOpt Trimming
][const_107_151 | SmartOpt Trimming
][const_108_152 | SmartOpt Trimming
][const_109_153 | SmartOpt Trimming
][const_110_154 | SmartOpt Trimming
][const_111_155 | SmartOpt Trimming
][const_112_156 | SmartOpt Trimming
][const_113_157 | SmartOpt Trimming
][const_114_158 | SmartOpt Trimming
][const_115_159 | SmartOpt Trimming
][const_116_162 | SmartOpt Trimming
][const_117_163 | SmartOpt Trimming
][const_118_167 | SmartOpt Trimming
][const_119_168 | SmartOpt Trimming
][const_120_170 | SmartOpt Trimming
][const_121_171 | SmartOpt Trimming
][const_122_173 | SmartOpt Trimming
][const_123_174 | SmartOpt Trimming
][const_124_176 | SmartOpt Trimming
][const_125_177 | SmartOpt Trimming
][const_126_180 | SmartOpt Trimming
][const_127_181 | SmartOpt Trimming
][const_128_183 | SmartOpt Trimming
][const_129_184 | SmartOpt Trimming
][const_130_187 | SmartOpt Trimming
][const_131_188 | SmartOpt Trimming
][const_132_191 | SmartOpt Trimming
][const_133_192 | SmartOpt Trimming
][const_134_197 | SmartOpt Trimming
][const_135_198 | SmartOpt Trimming
][const_136_202 | SmartOpt Trimming
][const_137_203 | SmartOpt Trimming
][const_138_207 | SmartOpt Trimming
][const_139_208 | SmartOpt Trimming
][const_140_212 | SmartOpt Trimming
][const_141_213 | SmartOpt Trimming
][const_142_217 | SmartOpt Trimming
][const_143_218 | SmartOpt Trimming
][const_144_222 | SmartOpt Trimming
][const_145_223 | SmartOpt Trimming
][const_146_227 | SmartOpt Trimming
][const_147_228 | SmartOpt Trimming
][const_148_234 | SmartOpt Trimming
][const_150_236 | SmartOpt Trimming
][const_152_240 | SmartOpt Trimming
][const_154_244 | SmartOpt Trimming
][const_156_247 | SmartOpt Trimming
][const_158_251 | SmartOpt Trimming
][const_160_254 | SmartOpt Trimming
][const_162_258 | SmartOpt Trimming
][const_164_262 | SmartOpt Trimming
][const_166_266 | SmartOpt Trimming
][const_168_267 | SmartOpt Trimming
][const_169_268 | SmartOpt Trimming
][const_170_271 | SmartOpt Trimming
][const_171_272 | SmartOpt Trimming
][const_172_273 | SmartOpt Trimming
][const_173_274 | SmartOpt Trimming
][const_174_275 | SmartOpt Trimming
][const_175_276 | SmartOpt Trimming
][const_176_277 | SmartOpt Trimming
][const_177_278 | SmartOpt Trimming
][const_178_279 | SmartOpt Trimming
][const_179_280 | SmartOpt Trimming
][const_180_281 | SmartOpt Trimming
][const_181_282 | SmartOpt Trimming
][const_182_283 | SmartOpt Trimming
][const_183_284 | SmartOpt Trimming
][const_184_285 | SmartOpt Trimming
][const_185_286 | SmartOpt Trimming
][const_187_287 | SmartOpt Trimming
][const_188_288 | SmartOpt Trimming
][const_190_289 | SmartOpt Trimming
][const_191_290 | SmartOpt Trimming
][const_193_291 | SmartOpt Trimming
][const_194_292 | SmartOpt Trimming
][const_196_293 | SmartOpt Trimming
][const_197_294 | SmartOpt Trimming
][const_199_295 | SmartOpt Trimming
][const_200_296 | SmartOpt Trimming
][const_202_297 | SmartOpt Trimming
][const_203_298 | SmartOpt Trimming
][const_205_299 | SmartOpt Trimming
][const_206_300 | SmartOpt Trimming
][const_208_301 | SmartOpt Trimming
][const_209_302 | SmartOpt Trimming
][const_211_303 | SmartOpt Trimming
][const_212_304 | SmartOpt Trimming
][const_214_305 | SmartOpt Trimming
][const_215_306 | SmartOpt Trimming
][const_217_307 | SmartOpt Trimming
][const_218_308 | SmartOpt Trimming
][const_220_309 | SmartOpt Trimming
][const_221_310 | SmartOpt Trimming
][const_223_311 | SmartOpt Trimming
][const_224_312 | SmartOpt Trimming
][const_226_313 | SmartOpt Trimming
][const_227_314 | SmartOpt Trimming
][const_229_315 | SmartOpt Trimming
][const_230_316 | SmartOpt Trimming
][const_232_317 | SmartOpt Trimming
][const_233_318 | SmartOpt Trimming
][const_234_321 | SmartOpt Trimming
][const_235_322 | SmartOpt Trimming
][const_236_323 | SmartOpt Trimming
][const_237_324 | SmartOpt Trimming
][const_238_325 | SmartOpt Trimming
][const_239_326 | SmartOpt Trimming
][const_240_327 | SmartOpt Trimming
][const_241_328 | SmartOpt Trimming
][const_242_329 | SmartOpt Trimming
][const_243_330 | SmartOpt Trimming
][const_244_331 | SmartOpt Trimming
][const_245_332 | SmartOpt Trimming
][const_247_333 | SmartOpt Trimming
][const_248_334 | SmartOpt Trimming
][const_250_335 | SmartOpt Trimming
][const_251_336 | SmartOpt Trimming
][const_253_337 | SmartOpt Trimming
][const_254_338 | SmartOpt Trimming
][const_256_339 | SmartOpt Trimming
][const_257_340 | SmartOpt Trimming
][const_259_341 | SmartOpt Trimming
][const_260_342 | SmartOpt Trimming
][const_262_343 | SmartOpt Trimming
][const_263_344 | SmartOpt Trimming
][const_265_345 | SmartOpt Trimming
][const_266_346 | SmartOpt Trimming
][const_268_347 | SmartOpt Trimming
][const_269_348 | SmartOpt Trimming
][const_271_349 | SmartOpt Trimming
][const_272_350 | SmartOpt Trimming
][const_274_351 | SmartOpt Trimming
][const_275_352 | SmartOpt Trimming
][const_277_353 | SmartOpt Trimming
][const_278_354 | SmartOpt Trimming
][const_280_355 | SmartOpt Trimming
][const_281_356 | SmartOpt Trimming
][const_282_358 | SmartOpt Trimming
][const_283_359 | SmartOpt Trimming
][const_284_360 | SmartOpt Trimming
][const_285_361 | SmartOpt Trimming
][const_286_362 | SmartOpt Trimming
][const_287_363 | SmartOpt Trimming
][const_288_364 | SmartOpt Trimming
][const_289_365 | SmartOpt Trimming
][const_290_366 | SmartOpt Trimming
][const_291_367 | SmartOpt Trimming
][const_292_368 | SmartOpt Trimming
][const_293_369 | SmartOpt Trimming
][const_294_370 | SmartOpt Trimming
][const_295_371 | SmartOpt Trimming
][const_296_374 | SmartOpt Trimming
][const_297_375 | SmartOpt Trimming
][const_298_379 | SmartOpt Trimming
][const_299_380 | SmartOpt Trimming
][const_300_383 | SmartOpt Trimming
][const_301_384 | SmartOpt Trimming
][const_302_387 | SmartOpt Trimming
][const_303_388 | SmartOpt Trimming
][const_304_391 | SmartOpt Trimming
][const_305_392 | SmartOpt Trimming
][const_306_395 | SmartOpt Trimming
][const_307_396 | SmartOpt Trimming
][const_308_399 | SmartOpt Trimming
][const_309_400 | SmartOpt Trimming
][const_310_403 | SmartOpt Trimming
][const_311_404 | SmartOpt Trimming
][const_312_405 | SmartOpt Trimming
][const_313_406 | SmartOpt Trimming
][const_315_407 | SmartOpt Trimming
][const_316_408 | SmartOpt Trimming
][const_318_409 | SmartOpt Trimming
][const_319_410 | SmartOpt Trimming
][const_321_411 | SmartOpt Trimming
][const_322_412 | SmartOpt Trimming
][const_324_414 | SmartOpt Trimming
][const_325_418 | SmartOpt Trimming
][const_326_421 | SmartOpt Trimming
][const_327_424 | SmartOpt Trimming
][const_328_426 | SmartOpt Trimming
][const_329_427 | SmartOpt Trimming
][const_32_20 | SmartOpt Trimming
][const_331_428 | SmartOpt Trimming
][const_332_429 | SmartOpt Trimming
][const_334_430 | SmartOpt Trimming
][const_335_431 | SmartOpt Trimming
][const_337_432 | SmartOpt Trimming
][const_338_433 | SmartOpt Trimming
][const_33_21 | SmartOpt Trimming
][const_340_435 | SmartOpt Trimming
][const_341_436 | SmartOpt Trimming
][const_342_440 | SmartOpt Trimming
][const_343_441 | SmartOpt Trimming
][const_344_445 | SmartOpt Trimming
][const_345_446 | SmartOpt Trimming
][const_346_449 | SmartOpt Trimming
][const_347_450 | SmartOpt Trimming
][const_348_453 | SmartOpt Trimming
][const_349_454 | SmartOpt Trimming
][const_34_23 | SmartOpt Trimming
][const_351_456 | SmartOpt Trimming
][const_352_457 | SmartOpt Trimming
][const_354_458 | SmartOpt Trimming
][const_355_459 | SmartOpt Trimming
][const_356_460 | SmartOpt Trimming
][const_357_461 | SmartOpt Trimming
][const_358_462 | SmartOpt Trimming
][const_359_463 | SmartOpt Trimming
][const_35_24 | SmartOpt Trimming
][const_360_464 | SmartOpt Trimming
][const_361_465 | SmartOpt Trimming
][const_362_466 | SmartOpt Trimming
][const_363_467 | SmartOpt Trimming
][const_364_468 | SmartOpt Trimming
][const_365_469 | SmartOpt Trimming
][const_366_470 | SmartOpt Trimming
][const_367_471 | SmartOpt Trimming
][const_368_472 | SmartOpt Trimming
][const_369_473 | SmartOpt Trimming
][const_36_28 | SmartOpt Trimming
][const_370_479 | SmartOpt Trimming
][const_371_480 | SmartOpt Trimming
][const_372_483 | SmartOpt Trimming
][const_373_484 | SmartOpt Trimming
][const_374_487 | SmartOpt Trimming
][const_375_488 | SmartOpt Trimming
][const_376_490 | SmartOpt Trimming
][const_377_491 | SmartOpt Trimming
][const_378_493 | SmartOpt Trimming
][const_379_494 | SmartOpt Trimming
][const_37_29 | SmartOpt Trimming
][const_380_497 | SmartOpt Trimming
][const_381_498 | SmartOpt Trimming
][const_382_499 | SmartOpt Trimming
][const_383_500 | SmartOpt Trimming
][const_384_503 | SmartOpt Trimming
][const_385_504 | SmartOpt Trimming
][const_386_506 | SmartOpt Trimming
][const_387_507 | SmartOpt Trimming
][const_389_508 | SmartOpt Trimming
][const_38_36 | SmartOpt Trimming
][const_390_509 | SmartOpt Trimming
][const_392_511 | SmartOpt Trimming
][const_393_512 | SmartOpt Trimming
][const_395_513 | SmartOpt Trimming
][const_396_514 | SmartOpt Trimming
][const_398_515 | SmartOpt Trimming
][const_399_516 | SmartOpt Trimming
][const_39_37 | SmartOpt Trimming
][const_401_517 | SmartOpt Trimming
][const_402_518 | SmartOpt Trimming
][const_404_519 | SmartOpt Trimming
][const_405_520 | SmartOpt Trimming
][const_407_522 | SmartOpt Trimming
][const_408_523 | SmartOpt Trimming
][const_40_41 | SmartOpt Trimming
][const_411_524 | SmartOpt Trimming
][const_413_527 | SmartOpt Trimming
][const_415_530 | SmartOpt Trimming
][const_417_532 | SmartOpt Trimming
][const_418_533 | SmartOpt Trimming
][const_419_534 | SmartOpt Trimming
][const_41_42 | SmartOpt Trimming
][const_421_535 | SmartOpt Trimming
][const_422_536 | SmartOpt Trimming
][const_424_537 | SmartOpt Trimming
][const_425_538 | SmartOpt Trimming
][const_427_539 | SmartOpt Trimming
][const_428_540 | SmartOpt Trimming
][const_42_46 | SmartOpt Trimming
][const_430_541 | SmartOpt Trimming
][const_431_542 | SmartOpt Trimming
][const_433_543 | SmartOpt Trimming
][const_434_544 | SmartOpt Trimming
][const_436_545 | SmartOpt Trimming
][const_437_546 | SmartOpt Trimming
][const_439_547 | SmartOpt Trimming
][const_43_47 | SmartOpt Trimming
][const_440_548 | SmartOpt Trimming
][const_442_549 | SmartOpt Trimming
][const_443_550 | SmartOpt Trimming
][const_445_553 | SmartOpt Trimming
][const_446_554 | SmartOpt Trimming
][const_448_557 | SmartOpt Trimming
][const_449_558 | SmartOpt Trimming
][const_44_51 | SmartOpt Trimming
][const_451_560 | SmartOpt Trimming
][const_452_561 | SmartOpt Trimming
][const_455_563 | SmartOpt Trimming
][const_456_565 | SmartOpt Trimming
][const_457_566 | SmartOpt Trimming
][const_459_568 | SmartOpt Trimming
][const_45_52 | SmartOpt Trimming
][const_460_569 | SmartOpt Trimming
][const_462_570 | SmartOpt Trimming
][const_463_571 | SmartOpt Trimming
][const_464_572 | SmartOpt Trimming
][const_465_573 | SmartOpt Trimming
][const_466_574 | SmartOpt Trimming
][const_467_575 | SmartOpt Trimming
][const_469_576 | SmartOpt Trimming
][const_46_56 | SmartOpt Trimming
][const_470_577 | SmartOpt Trimming
][const_472_579 | SmartOpt Trimming
][const_473_580 | SmartOpt Trimming
][const_475_582 | SmartOpt Trimming
][const_476_583 | SmartOpt Trimming
][const_478_586 | SmartOpt Trimming
][const_479_587 | SmartOpt Trimming
][const_47_57 | SmartOpt Trimming
][const_481_590 | SmartOpt Trimming
][const_482_591 | SmartOpt Trimming
][const_484_593 | SmartOpt Trimming
][const_485_594 | SmartOpt Trimming
][const_487_597 | SmartOpt Trimming
][const_488_598 | SmartOpt Trimming
][const_48_61 | SmartOpt Trimming
][const_490_601 | SmartOpt Trimming
][const_491_602 | SmartOpt Trimming
][const_493_608 | SmartOpt Trimming
][const_494_609 | SmartOpt Trimming
][const_496_611 | SmartOpt Trimming
][const_497_612 | SmartOpt Trimming
][const_499_614 | SmartOpt Trimming
][const_49_62 | SmartOpt Trimming
][const_500_615 | SmartOpt Trimming
][const_502_617 | SmartOpt Trimming
][const_503_618 | SmartOpt Trimming
][const_505_620 | SmartOpt Trimming
][const_506_621 | SmartOpt Trimming
][const_508_623 | SmartOpt Trimming
][const_509_624 | SmartOpt Trimming
][const_50_66 | SmartOpt Trimming
][const_511_626 | SmartOpt Trimming
][const_512_627 | SmartOpt Trimming
][const_514_629 | SmartOpt Trimming
][const_515_630 | SmartOpt Trimming
][const_517_635 | SmartOpt Trimming
][const_518_636 | SmartOpt Trimming
][const_51_67 | SmartOpt Trimming
][const_520_638 | SmartOpt Trimming
][const_521_639 | SmartOpt Trimming
][const_523_641 | SmartOpt Trimming
][const_524_642 | SmartOpt Trimming
][const_526_644 | SmartOpt Trimming
][const_527_645 | SmartOpt Trimming
][const_529_647 | SmartOpt Trimming
][const_52_71 | SmartOpt Trimming
][const_530_648 | SmartOpt Trimming
][const_532_650 | SmartOpt Trimming
][const_533_651 | SmartOpt Trimming
][const_535_653 | SmartOpt Trimming
][const_536_654 | SmartOpt Trimming
][const_538_656 | SmartOpt Trimming
][const_539_657 | SmartOpt Trimming
][const_53_72 | SmartOpt Trimming
][const_54_79 | SmartOpt Trimming
][const_55_80 | SmartOpt Trimming
][const_56_84 | SmartOpt Trimming
][const_57_85 | SmartOpt Trimming
][const_58_89 | SmartOpt Trimming
][const_59_90 | SmartOpt Trimming
][const_60_94 | SmartOpt Trimming
][const_61_95 | SmartOpt Trimming
][const_62_99 | SmartOpt Trimming
][const_63_100 | SmartOpt Trimming
][const_64_102 | SmartOpt Trimming
][const_65_103 | SmartOpt Trimming
][const_66_107 | SmartOpt Trimming
][const_67_108 | SmartOpt Trimming
][const_68_109 | SmartOpt Trimming
][const_69_110 | SmartOpt Trimming
][const_70_112 | SmartOpt Trimming
][const_71_113 | SmartOpt Trimming
][const_72_114 | SmartOpt Trimming
][const_73_115 | SmartOpt Trimming
][const_74_116 | SmartOpt Trimming
][const_75_117 | SmartOpt Trimming
][const_76_118 | SmartOpt Trimming
][const_77_119 | SmartOpt Trimming
][const_78_120 | SmartOpt Trimming
][const_79_121 | SmartOpt Trimming
][const_80_122 | SmartOpt Trimming
][const_81_123 | SmartOpt Trimming
][const_82_124 | SmartOpt Trimming
][const_83_125 | SmartOpt Trimming
][const_84_126 | SmartOpt Trimming
][const_85_127 | SmartOpt Trimming
][const_86_129 | SmartOpt Trimming
][const_87_130 | SmartOpt Trimming
][const_88_131 | SmartOpt Trimming
][const_89_132 | SmartOpt Trimming
][const_90_133 | SmartOpt Trimming
][const_91_134 | SmartOpt Trimming
][const_92_135 | SmartOpt Trimming
][const_93_136 | SmartOpt Trimming
][const_94_137 | SmartOpt Trimming
][const_95_138 | SmartOpt Trimming
][const_96_139 | SmartOpt Trimming
][const_97_140 | SmartOpt Trimming
][const_98_141 | SmartOpt Trimming
][const_99_142 | SmartOpt Trimming
 
 
Flops added for Enable Generation
/spi_test_ct.wcfg
3,7 → 3,7
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto">
<db_ref path="C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn/testbench_isim_par.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
16,7 → 16,7
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="21" />
<WVObjectSize size="22" />
<wvobject fp_name="/testbench/dbg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dbg[11:0]</obj_property>
<obj_property name="ObjectShortName">dbg[11:0]</obj_property>
26,6 → 26,10
<obj_property name="ElementShortName">sysclk</obj_property>
<obj_property name="ObjectShortName">sysclk</obj_property>
</wvobject>
<wvobject fp_name="/testbench/pclk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">pclk</obj_property>
<obj_property name="ObjectShortName">pclk</obj_property>
</wvobject>
<wvobject fp_name="/testbench/sw_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">sw_data[7:0]</obj_property>
<obj_property name="ObjectShortName">sw_data[7:0]</obj_property>
/spi_master_atlys_top.pcf
1,8 → 1,14
//! **************************************************************************
// Written by: Map O.40d on Mon Aug 29 00:08:35 2011
// Written by: Map O.40d on Thu Sep 01 13:07:27 2011
//! **************************************************************************
 
SCHEMATIC START;
COMP "dbg_o<10>" LOCATE = SITE "V13" LEVEL 1;
COMP "dbg_o<11>" LOCATE = SITE "U13" LEVEL 1;
COMP "spi_miso_o" LOCATE = SITE "V15" LEVEL 1;
COMP "spi_mosi_o" LOCATE = SITE "U15" LEVEL 1;
COMP "sw_i<0>" LOCATE = SITE "A10" LEVEL 1;
COMP "sw_i<1>" LOCATE = SITE "D14" LEVEL 1;
COMP "sw_i<2>" LOCATE = SITE "C14" LEVEL 1;
COMP "sw_i<3>" LOCATE = SITE "P15" LEVEL 1;
COMP "sw_i<4>" LOCATE = SITE "P12" LEVEL 1;
38,17 → 44,10
COMP "led_o<5>" LOCATE = SITE "D4" LEVEL 1;
COMP "led_o<6>" LOCATE = SITE "P16" LEVEL 1;
COMP "led_o<7>" LOCATE = SITE "N12" LEVEL 1;
COMP "gclk_i" LOCATE = SITE "L15" LEVEL 1;
COMP "spi_sck_o" LOCATE = SITE "V16" LEVEL 1;
COMP "s_state_o<0>" LOCATE = SITE "V9" LEVEL 1;
COMP "s_state_o<1>" LOCATE = SITE "T9" LEVEL 1;
COMP "s_state_o<2>" LOCATE = SITE "V4" LEVEL 1;
COMP "s_state_o<3>" LOCATE = SITE "T4" LEVEL 1;
COMP "dbg_o<10>" LOCATE = SITE "V13" LEVEL 1;
COMP "dbg_o<11>" LOCATE = SITE "U13" LEVEL 1;
COMP "spi_miso_o" LOCATE = SITE "V15" LEVEL 1;
COMP "spi_mosi_o" LOCATE = SITE "U15" LEVEL 1;
COMP "sw_i<0>" LOCATE = SITE "A10" LEVEL 1;
COMP "sw_i<1>" LOCATE = SITE "D14" LEVEL 1;
SCHEMATIC END;
 
/spi_ms_atlys.xise
35,7 → 35,7
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="0"/>
</file>
</files>
 
160,7 → 160,7
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spi_master_atlys_top|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="spi_master_atlys_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spi_master_atlys_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
363,7 → 363,7
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|spi_master_atlys_top|Structure" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-07T09:55:20" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C5BE631B69F48AB8C2F24035AF7A13B" xil_pn:valueState="non-default"/>
/par_usage_statistics.html
1,32 → 1,32
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>335</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>1055</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>1055</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>941</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>306</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>851</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>851</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>711</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>9.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>8.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>2.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>2.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>28.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>5.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>2.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>17.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0238</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0202</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
/spi_master_atlys_top.par
1,7 → 1,7
Release 13.1 par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
 
DEVELOP-W7:: Mon Aug 29 00:08:38 2011
DEVELOP-W7:: Thu Sep 01 13:07:30 2011
 
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd
spi_master_atlys_top.ncd spi_master_atlys_top.pcf
27,16 → 27,16
Device Utilization Summary:
 
Slice Logic Utilization:
Number of Slice Registers: 224 out of 54,576 1%
Number used as Flip Flops: 224
Number of Slice Registers: 210 out of 54,576 1%
Number used as Flip Flops: 210
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 167 out of 27,288 1%
Number using O6 output only: 112
Number using O5 output only: 28
Number using O5 and O6: 27
Number of Slice LUTs: 143 out of 27,288 1%
Number used as logic: 129 out of 27,288 1%
Number using O6 output only: 79
Number using O5 output only: 15
Number using O5 and O6: 35
Number used as ROM: 0
Number used as Memory: 4 out of 6,408 1%
Number used as Dual Port RAM: 0
45,17 → 45,17
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 6
Number with same-slice register load: 4
Number used exclusively as route-thrus: 10
Number with same-slice register load: 8
Number with same-slice carry load: 2
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 102 out of 6,822 1%
Number of LUT Flip Flop pairs used: 272
Number with an unused Flip Flop: 64 out of 272 23%
Number with an unused LUT: 95 out of 272 34%
Number of fully used LUT-FF pairs: 113 out of 272 41%
Number of occupied Slices: 91 out of 6,822 1%
Number of LUT Flip Flop pairs used: 231
Number with an unused Flip Flop: 46 out of 231 19%
Number with an unused LUT: 88 out of 231 38%
Number of fully used LUT-FF pairs: 97 out of 231 41%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
 
66,8 → 66,8
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 63 out of 218 28%
Number of LOCed IOBs: 47 out of 63 74%
Number of bonded IOBs: 64 out of 218 29%
Number of LOCed IOBs: 46 out of 64 71%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
74,8 → 74,8
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
106,13 → 106,13
Starting Router
 
 
Phase 1 : 1133 unrouted; REAL time: 5 secs
Phase 1 : 923 unrouted; REAL time: 5 secs
 
Phase 2 : 972 unrouted; REAL time: 6 secs
Phase 2 : 776 unrouted; REAL time: 6 secs
 
Phase 3 : 282 unrouted; REAL time: 7 secs
Phase 3 : 205 unrouted; REAL time: 7 secs
 
Phase 4 : 282 unrouted; (Par is working to improve performance) REAL time: 9 secs
Phase 4 : 205 unrouted; (Par is working to improve performance) REAL time: 8 secs
 
Updating file: spi_master_atlys_top.ncd with current fully routed design.
 
148,12 → 148,15
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net gcl | SETUP | N/A| 4.888ns| N/A| 0
k_i_BUFGP | HOLD | 0.378ns| | 0| 0
Autotimespec constraint for clock net pcl | SETUP | N/A| 5.916ns| N/A| 0
k_i_BUFGP | HOLD | 0.264ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Ins | SETUP | N/A| 3.948ns| N/A| 0
t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.459ns| | 0| 0
Autotimespec constraint for clock net Ins | SETUP | N/A| 3.959ns| N/A| 0
t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.439ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net scl | SETUP | N/A| 3.391ns| N/A| 0
k_i_BUFGP | HOLD | 0.513ns| | 0| 0
----------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
168,10 → 171,10
 
All signals are completely routed.
 
Total REAL time to PAR completion: 10 secs
Total CPU time to PAR completion: 10 secs
Total REAL time to PAR completion: 9 secs
Total CPU time to PAR completion: 9 secs
 
Peak Memory Usage: 264 MB
Peak Memory Usage: 268 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
/spi_ms_atlys.gise
47,8 → 47,8
<file xil_pn:branch="PostRouteSimulation" xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/par/spi_master_atlys_top_timesim.nlf"/>
<file xil_pn:branch="PostRouteSimulation" xil_pn:fileType="FILE_SDF" xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/>
<file xil_pn:branch="PostRouteSimulation" xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/>
<file xil_pn:branch="PostSynthSim" xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.nlf"/>
<file xil_pn:branch="PostSynthSim" xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.vhd"/>
<file xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.nlf"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.vhd"/>
<file xil_pn:branch="PostTranslateSimulation" xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/translate/spi_master_atlys_top_translate.nlf"/>
<file xil_pn:branch="PostTranslateSimulation" xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spi_master_atlys_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
122,7 → 122,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1314583834" xil_pn:in_ck="4343194839995565815" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1314583834">
<transform xil_pn:end_ts="1314889672" xil_pn:in_ck="4343194839995565815" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1314889672">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
159,6 → 159,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
172,6 → 173,7
<transform xil_pn:end_ts="1314545598" xil_pn:in_ck="7130759491340027311" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5414671575160791934" xil_pn:start_ts="1314545598">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
206,7 → 208,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1314587294" xil_pn:in_ck="-8247761554522826671" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8195216592062898977" xil_pn:start_ts="1314587285">
<transform xil_pn:end_ts="1314893227" xil_pn:in_ck="-8247761554522826671" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8195216592062898977" xil_pn:start_ts="1314893218">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
226,11 → 228,11
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1314587294" xil_pn:in_ck="-6344801126424831697" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4068456177828066131" xil_pn:start_ts="1314587294">
<transform xil_pn:end_ts="1314889842" xil_pn:in_ck="-6344801126424831697" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4068456177828066131" xil_pn:start_ts="1314889842">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1314587297" xil_pn:in_ck="-2449764723691034422" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-177710677611610831" xil_pn:start_ts="1314587294">
<transform xil_pn:end_ts="1314893230" xil_pn:in_ck="-2449764723691034422" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-177710677611610831" xil_pn:start_ts="1314893227">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
239,7 → 241,7
<outfile xil_pn:name="spi_master_atlys_top.ngd"/>
<outfile xil_pn:name="spi_master_atlys_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1314587317" xil_pn:in_ck="-2449764723691034421" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1314587297">
<transform xil_pn:end_ts="1314893249" xil_pn:in_ck="-2449764723691034421" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1314893230">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
253,7 → 255,7
<outfile xil_pn:name="spi_master_atlys_top_summary.xml"/>
<outfile xil_pn:name="spi_master_atlys_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1314587335" xil_pn:in_ck="5633518429974504804" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1314587317">
<transform xil_pn:end_ts="1314893267" xil_pn:in_ck="5633518429974504804" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1314893249">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
271,7 → 273,11
<transform xil_pn:end_ts="1314587493" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1314587477">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="spi_master_atlys_top.bgn"/>
<outfile xil_pn:name="spi_master_atlys_top.bit"/>
<outfile xil_pn:name="spi_master_atlys_top.drc"/>
280,35 → 286,25
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1314586528" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRAN_postParSimModel" xil_pn:prop_ck="5598892574118791338" xil_pn:start_ts="1314586521">
<transform xil_pn:end_ts="1314893294" xil_pn:in_ck="-5988982649231273448" xil_pn:name="TRAN_postParSimModel" xil_pn:prop_ck="5598892574118791338" xil_pn:start_ts="1314893286">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="netgen"/>
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.nlf"/>
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/>
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/>
</transform>
<transform xil_pn:end_ts="1314584667" xil_pn:in_ck="-7029858421675272663" xil_pn:name="TRAN_copyPost-ParAbstractToPreSimulation" xil_pn:start_ts="1314584667">
<transform xil_pn:end_ts="1314893938" xil_pn:in_ck="-7029858421675272663" xil_pn:name="TRAN_copyPost-ParAbstractToPreSimulation" xil_pn:start_ts="1314893938">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.sdf"/>
<outfile xil_pn:name="netgen/par/spi_master_atlys_top_timesim.vhd"/>
<outfile xil_pn:name="spi_master_atlys_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1314584674" xil_pn:in_ck="9156795390127265392" xil_pn:name="TRAN_ISimulatePostPlace&amp;RouteModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314584667">
<transform xil_pn:end_ts="1314893944" xil_pn:in_ck="9156795390127265392" xil_pn:name="TRAN_ISimulatePostPlace&amp;RouteModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314893938">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
317,10 → 313,9
<outfile xil_pn:name="testbench_par.prj"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1314584674" xil_pn:in_ck="7130759509275896515" xil_pn:name="TRAN_ISimulatePostPlace&amp;RouteModel" xil_pn:prop_ck="-3956543683666394319" xil_pn:start_ts="1314584674">
<transform xil_pn:end_ts="1314893945" xil_pn:in_ck="7130759509275896515" xil_pn:name="TRAN_ISimulatePostPlace&amp;RouteModel" xil_pn:prop_ck="-3956543683666394319" xil_pn:start_ts="1314893944">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
327,7 → 322,7
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testbench_isim_par.wdb"/>
</transform>
<transform xil_pn:end_ts="1314587335" xil_pn:in_ck="-2449764723691034553" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1314587329">
<transform xil_pn:end_ts="1314893267" xil_pn:in_ck="-2449764723691034553" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1314893261">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
339,22 → 334,22
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="netgen"/>
<outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.nlf"/>
<outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.sdf"/>
<outfile xil_pn:name="netgen/map/spi_master_atlys_top_map.vhd"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1314586512" xil_pn:in_ck="-5988982649231273316" xil_pn:name="TRAN_postXlateSimModel" xil_pn:prop_ck="4032524037721565697" xil_pn:start_ts="1314586510">
<transform xil_pn:end_ts="1314889848" xil_pn:in_ck="-5988982649231273316" xil_pn:name="TRAN_postXlateSimModel" xil_pn:prop_ck="4032524037721565697" xil_pn:start_ts="1314889846">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="netgen"/>
<outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.nlf"/>
<outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/>
</transform>
<transform xil_pn:end_ts="1314584431" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_copyPost-TranslateAbstractToPreSimulation" xil_pn:start_ts="1314584431">
<transform xil_pn:end_ts="1314889848" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_copyPost-TranslateAbstractToPreSimulation" xil_pn:start_ts="1314889848">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
365,10 → 360,11
<outfile xil_pn:name="netgen/translate/spi_master_atlys_top_translate.vhd"/>
<outfile xil_pn:name="spi_master_atlys_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1314584434" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_ISimulatePostTranslateModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314584431">
<transform xil_pn:end_ts="1314889853" xil_pn:in_ck="1721521412391114385" xil_pn:name="TRAN_ISimulatePostTranslateModelRunFuse" xil_pn:prop_ck="4831401045093024940" xil_pn:start_ts="1314889848">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
380,9 → 376,10
<outfile xil_pn:name="testbench_translate.prj"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1314584435" xil_pn:in_ck="-2373432107787769551" xil_pn:name="TRAN_ISimulatePostTranslateModel" xil_pn:prop_ck="-8441040086216995160" xil_pn:start_ts="1314584434">
<transform xil_pn:end_ts="1314889853" xil_pn:in_ck="-2373432107787769551" xil_pn:name="TRAN_ISimulatePostTranslateModel" xil_pn:prop_ck="-8441040086216995160" xil_pn:start_ts="1314889853">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
394,10 → 391,9
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="netgen"/>
<outfile xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.nlf"/>
<outfile xil_pn:name="netgen/synthesis/spi_master_atlys_top_synthesis.vhd"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
 
/spi_master_atlys.ucf
5,7 → 5,7
 
 
# clock pin for Atlys rev C board
NET "gclk_i" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
#### NET "gclk_i" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
 
# onBoard USB controller
# NET "EppAstb" LOC = "B9"; # Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = U1-FLAGA
/spi_master_atlys_top_map.mrp
12,7 → 12,7
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Aug 29 00:08:18 2011
Mapped Date : Thu Sep 01 13:07:11 2011
 
Design Summary
--------------
19,16 → 19,16
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 224 out of 54,576 1%
Number used as Flip Flops: 224
Number of Slice Registers: 210 out of 54,576 1%
Number used as Flip Flops: 210
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 167 out of 27,288 1%
Number using O6 output only: 112
Number using O5 output only: 28
Number using O5 and O6: 27
Number of Slice LUTs: 143 out of 27,288 1%
Number used as logic: 129 out of 27,288 1%
Number using O6 output only: 79
Number using O5 output only: 15
Number using O5 and O6: 35
Number used as ROM: 0
Number used as Memory: 4 out of 6,408 1%
Number used as Dual Port RAM: 0
37,20 → 37,20
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 6
Number with same-slice register load: 4
Number used exclusively as route-thrus: 10
Number with same-slice register load: 8
Number with same-slice carry load: 2
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 102 out of 6,822 1%
Number of LUT Flip Flop pairs used: 272
Number with an unused Flip Flop: 64 out of 272 23%
Number with an unused LUT: 95 out of 272 34%
Number of fully used LUT-FF pairs: 113 out of 272 41%
Number of unique control sets: 26
Number of occupied Slices: 91 out of 6,822 1%
Number of LUT Flip Flop pairs used: 231
Number with an unused Flip Flop: 46 out of 231 19%
Number with an unused LUT: 88 out of 231 38%
Number of fully used LUT-FF pairs: 97 out of 231 41%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 68 out of 54,576 1%
to control set restrictions: 74 out of 54,576 1%
 
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
59,8 → 59,8
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 63 out of 218 28%
Number of LOCed IOBs: 47 out of 63 74%
Number of bonded IOBs: 64 out of 218 29%
Number of LOCed IOBs: 46 out of 64 71%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
67,8 → 67,8
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
87,9 → 87,9
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
 
Average Fanout of Non-Clock Nets: 3.18
Average Fanout of Non-Clock Nets: 2.86
 
Peak Memory Usage: 298 MB
Peak Memory Usage: 301 MB
Total REAL time to MAP completion: 17 secs
Total CPU time to MAP completion (all processors): 17 secs
 
130,8 → 130,10
<spi_master_atlys_top> is equivalent to the following 2 FFs/Latches, which
will be removed : <Inst_spi_slave_port/state_reg_2_1>
<Inst_spi_slave_port/state_reg_2_2>
INFO:LIT:243 - Logical network gclk_i_BUFGP/N2 has no load.
INFO:LIT:243 - Logical network gclk_i_BUFGP/N3 has no load.
INFO:LIT:243 - Logical network pclk_i_BUFGP/N2 has no load.
INFO:LIT:243 - Logical network pclk_i_BUFGP/N3 has no load.
INFO:LIT:243 - Logical network sclk_i_BUFGP/N2 has no load.
INFO:LIT:243 - Logical network sclk_i_BUFGP/N3 has no load.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
142,17 → 144,17
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked
and 16 are not locked. If you would like to print the names of these IOs,
INFO:Place:834 - Only a subset of IOs are locked. Out of 64 IOs, 46 are locked
and 18 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design.
 
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) removed
4 block(s) removed
2 block(s) optimized away
2 signal(s) removed
87 Block(s) redundant
4 signal(s) removed
58 Block(s) redundant
 
Section 5 - Removed Logic
-------------------------
167,10 → 169,14
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
 
The signal "gclk_i_BUFGP/N2" is sourceless and has been removed.
The signal "gclk_i_BUFGP/N3" is sourceless and has been removed.
Unused block "gclk_i_BUFGP/XST_GND" (ZERO) removed.
Unused block "gclk_i_BUFGP/XST_VCC" (ONE) removed.
The signal "pclk_i_BUFGP/N2" is sourceless and has been removed.
The signal "pclk_i_BUFGP/N3" is sourceless and has been removed.
The signal "sclk_i_BUFGP/N2" is sourceless and has been removed.
The signal "sclk_i_BUFGP/N3" is sourceless and has been removed.
Unused block "pclk_i_BUFGP/XST_GND" (ZERO) removed.
Unused block "pclk_i_BUFGP/XST_VCC" (ONE) removed.
Unused block "sclk_i_BUFGP/XST_GND" (ZERO) removed.
Unused block "sclk_i_BUFGP/XST_VCC" (ONE) removed.
 
Optimized Block(s):
TYPE BLOCK
179,13 → 185,6
 
Redundant Block(s):
TYPE BLOCK
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<13>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<12>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<11>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<10>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<9>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<8>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<7>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
192,13 → 191,6
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<13>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<12>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<11>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<10>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<9>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<8>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<7>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
205,67 → 197,52
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<14>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_xor<14>_rt
INV ][1211_3_INV_0
INV ][1212_5_INV_0
INV ][335_42_INV_0
INV ][339_50_INV_0
INV ][343_55_INV_0
INV ][347_60_INV_0
INV ][351_65_INV_0
INV ][355_70_INV_0
INV ][359_75_INV_0
INV ][363_80_INV_0
INV ][395_115_INV_0
INV ][495_170_INV_0
INV ][496_174_INV_0
INV ][499_176_INV_0
INV ][515_193_INV_0
INV ][523_202_INV_0
INV ][527_207_INV_0
INV ][528_211_INV_0
INV ][531_213_INV_0
INV ][535_218_INV_0
INV ][539_223_INV_0
INV ][543_228_INV_0
INV ][547_233_INV_0
INV ][551_238_INV_0
INV ][555_243_INV_0
INV ][563_253_INV_0
INV ][567_257_INV_0
INV ][575_264_INV_0
INV ][579_268_INV_0
INV ][583_272_INV_0
INV ][587_276_INV_0
INV ][591_280_INV_0
INV ][595_284_INV_0
INV ][771_395_INV_0
INV ][775_400_INV_0
INV ][779_404_INV_0
INV ][783_408_INV_0
INV ][787_412_INV_0
INV ][791_416_INV_0
INV ][795_420_INV_0
INV ][799_424_INV_0
INV ][820_439_INV_0
INV ][825_443_INV_0
INV ][855_466_INV_0
INV ][859_471_INV_0
INV ][909_508_INV_0
INV ][917_517_INV_0
INV ][921_521_INV_0
INV ][925_527_INV_0
INV ][933_533_INV_0
INV ][966_562_INV_0
INV ][971_565_INV_0
INV ][1008_588_INV_0
INV ][1011_592_INV_0
INV ][1014_596_INV_0
INV ][1042_616_INV_0
INV ][1051_628_INV_0
INV ][1054_632_INV_0
INV ][1057_636_INV_0
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<7>_rt
LUT1 Inst_btn_debouncer/Mcount_cnt_reg_xor<7>_rt
INV ][241_70_INV_0
INV ][245_78_INV_0
INV ][249_83_INV_0
INV ][253_88_INV_0
INV ][257_93_INV_0
INV ][261_98_INV_0
INV ][269_106_INV_0
INV ][369_161_INV_0
INV ][373_166_INV_0
INV ][389_179_INV_0
INV ][397_186_INV_0
INV ][401_190_INV_0
INV ][402_194_INV_0
INV ][405_196_INV_0
INV ][409_201_INV_0
INV ][413_206_INV_0
INV ][417_211_INV_0
INV ][421_216_INV_0
INV ][425_221_INV_0
INV ][429_226_INV_0
INV ][453_249_INV_0
INV ][461_256_INV_0
INV ][465_260_INV_0
INV ][469_264_INV_0
INV ][645_373_INV_0
INV ][649_378_INV_0
INV ][653_382_INV_0
INV ][657_386_INV_0
INV ][661_390_INV_0
INV ][665_394_INV_0
INV ][669_398_INV_0
INV ][673_402_INV_0
INV ][694_417_INV_0
INV ][725_439_INV_0
INV ][729_444_INV_0
INV ][803_502_INV_0
INV ][836_526_INV_0
INV ][841_529_INV_0
INV ][878_552_INV_0
INV ][881_556_INV_0
INV ][918_585_INV_0
INV ][921_589_INV_0
INV ][927_596_INV_0
INV ][930_600_INV_0
 
Section 6 - IOB Properties
--------------------------
292,7 → 269,6
| dbg_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
| led_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
313,6 → 289,7
| m_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| m_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| m_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
| s_do_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| s_do_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| s_do_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
325,6 → 302,7
| s_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| s_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| s_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| sclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
| spi_miso_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| spi_mosi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
384,33 → 362,35
| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count |
+-----------------------------------------------------------------------------------------------------------------------------------+
| Inst_spi_master_port/spi_clk_reg_BUFG | | | | 6 | 11 |
| Inst_spi_master_port/spi_clk_reg_BUFG | | | lut1117_506 | 3 | 8 |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0 | | | 2 | 2 |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][IN_virtPIBox_574_736 | | | 1 | 2 |
| Inst_spi_master_port/spi_clk_reg_BUFG | | | lut1157_481 | 2 | 8 |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][1041_0 | | | 2 | 2 |
| Inst_spi_master_port/spi_clk_reg_BUFG | ][IN_virtPIBox_541_658 | | | 1 | 2 |
+-----------------------------------------------------------------------------------------------------------------------------------+
| gclk_i_BUFGP | | | | 36 | 85 |
| gclk_i_BUFGP | | | GLOBAL_LOGIC1 | 1 | 4 |
| gclk_i_BUFGP | | | ][336_48 | 2 | 8 |
| gclk_i_BUFGP | | | ][496_174 | 2 | 8 |
| gclk_i_BUFGP | | | ][528_211 | 2 | 8 |
| gclk_i_BUFGP | | | ][817_437 | 3 | 4 |
| gclk_i_BUFGP | | | lut263_47 | 2 | 6 |
| gclk_i_BUFGP | | | lut350_113 | 1 | 2 |
| gclk_i_BUFGP | | | lut362_120 | 2 | 8 |
| gclk_i_BUFGP | | | lut403_137 | 2 | 8 |
| gclk_i_BUFGP | | | lut444_154 | 2 | 8 |
| gclk_i_BUFGP | | | lut649_291 | 2 | 8 |
| gclk_i_BUFGP | | | lut772_342 | 2 | 6 |
| gclk_i_BUFGP | | | lut863_379 | 2 | 8 |
| gclk_i_BUFGP | | | lut905_398 | 3 | 8 |
| gclk_i_BUFGP | | | spi_wren_reg_m | 2 | 8 |
| gclk_i_BUFGP | | | spi_wren_reg_s | 1 | 2 |
| gclk_i_BUFGP | ][1209_0 | | | 2 | 6 |
| gclk_i_BUFGP | clear | | | 2 | 4 |
| gclk_i_BUFGP | spi_rst_reg | | ][817_437 | 1 | 4 |
| pclk_i_BUFGP | | | | 28 | 67 |
| pclk_i_BUFGP | | | GLOBAL_LOGIC1 | 1 | 4 |
| pclk_i_BUFGP | | | ][210_33 | 1 | 8 |
| pclk_i_BUFGP | | | ][242_76 | 2 | 6 |
| pclk_i_BUFGP | | | ][402_194 | 2 | 8 |
| pclk_i_BUFGP | | | lut410_104 | 1 | 2 |
| pclk_i_BUFGP | | | lut422_111 | 2 | 8 |
| pclk_i_BUFGP | | | lut463_128 | 2 | 8 |
| pclk_i_BUFGP | | | lut504_145 | 2 | 8 |
| pclk_i_BUFGP | | | lut546_164 | 2 | 8 |
| pclk_i_BUFGP | | | lut710_270 | 2 | 8 |
| pclk_i_BUFGP | | | lut832_320 | 2 | 6 |
| pclk_i_BUFGP | | | spi_wren_reg_m | 1 | 8 |
| pclk_i_BUFGP | | | spi_wren_reg_s | 1 | 2 |
| pclk_i_BUFGP | ][1041_0 | | | 2 | 6 |
| pclk_i_BUFGP | clear | | | 2 | 4 |
+-----------------------------------------------------------------------------------------------------------------------------------+
| sclk_i_BUFGP | | | | 3 | 4 |
| sclk_i_BUFGP | | | ][691_415 | 3 | 4 |
| sclk_i_BUFGP | | | lut923_357 | 2 | 8 |
| sclk_i_BUFGP | | | lut965_376 | 2 | 8 |
| sclk_i_BUFGP | spi_rst_reg | | ][691_415 | 1 | 4 |
+-----------------------------------------------------------------------------------------------------------------------------------+
| ~Inst_spi_master_port/spi_clk_reg_BUFG | | | | 1 | 1 |
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1209_0 | | | 1 | 1 |
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1041_0 | | | 1 | 1 |
+-----------------------------------------------------------------------------------------------------------------------------------+
 
Section 13 - Utilization by Hierarchy
418,11 → 398,11
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| spi_master_atlys_top/ | | 68/139 | 71/224 | 135/145 | 0/4 | 0/0 | 0/0 | 1/2 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top |
| +Inst_btn_debouncer | | 14/14 | 33/33 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_btn_debouncer |
| +Inst_spi_master_port | | 21/21 | 45/45 | 2/2 | 2/2 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_master_port |
| +Inst_spi_slave_port | | 23/23 | 36/36 | 6/6 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_slave_port |
| +Inst_sw_debouncer | | 13/13 | 39/39 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_sw_debouncer |
| spi_master_atlys_top/ | | 65/122 | 71/210 | 111/121 | 0/4 | 0/0 | 0/0 | 2/3 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top |
| +Inst_btn_debouncer | | 9/9 | 26/26 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_btn_debouncer |
| +Inst_spi_master_port | | 18/18 | 45/45 | 2/2 | 2/2 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_master_port |
| +Inst_spi_slave_port | | 20/20 | 36/36 | 6/6 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_slave_port |
| +Inst_sw_debouncer | | 10/10 | 32/32 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_sw_debouncer |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
* Slices can be packed with basic elements from multiple hierarchies.
/spi_master_atlys_test.vhd
13,7 → 13,8
-- Constants
--=============================================================================================
-- clock period
constant CLK_PERIOD : time := 10 ns;
constant SCLK_PERIOD : time := 11 ns; -- serial high speed clock
constant PCLK_PERIOD : time := 10 ns; -- parallel high-speed clock
 
-- button definitions
constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
28,7 → 29,8
--=============================================================================================
component spi_master_atlys_top
port(
gclk_i : in std_logic;
sclk_i : in std_logic;
pclk_i : in std_logic;
sw_i : in std_logic_vector(7 downto 0);
btn_i : in std_logic_vector(5 downto 0);
spi_ssel_o : out std_logic;
53,6 → 55,7
--=============================================================================================
--- clock signals ---
signal sysclk : std_logic := '0'; -- 100MHz clock
signal pclk : std_logic := '0'; -- 100MHz clock
--- switch debouncer signals ---
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
--- pushbutton debouncer signals ---
94,7 → 97,8
-- set debounce time to 2 us to save simulation time
Inst_spi_master_atlys_top: spi_master_atlys_top
port map(
gclk_i => sysclk,
sclk_i => sysclk,
pclk_i => pclk,
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
125,14 → 129,22
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
gclk_proc: process is
sysclk_proc: process is
begin
loop
sysclk <= not sysclk;
wait for CLK_PERIOD / 2;
wait for SCLK_PERIOD / 2;
end loop;
end process gclk_proc;
end process sysclk_proc;
 
pclk_proc: process is
begin
loop
pclk <= not pclk;
wait for PCLK_PERIOD / 2;
end loop;
end process pclk_proc;
 
--=============================================================================================
-- TEST BENCH STIMULI
--=============================================================================================
151,6 → 163,14
wait for 5 us;
sw_data <= X"55";
wait for 5 us;
sw_data <= X"AA";
wait for 5 us;
sw_data <= X"1e";
wait for 5 us;
sw_data <= X"79";
wait for 5 us;
sw_data <= X"40";
wait for 5 us;
assert false report "End Simulation" severity failure; -- stop simulation
end process tb;
-- End Test Bench
/spi_master_atlys_top_map.map
12,7 → 12,7
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Aug 29 00:08:18 2011
Mapped Date : Thu Sep 01 13:07:11 2011
 
Running global optimization...
Mapping design into LUTs...
22,55 → 22,55
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 9 secs
Total CPU time at the beginning of Placer: 9 secs
Total REAL time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 8 secs
 
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:7388cd6e) REAL time: 10 secs
Phase 1.1 Initial Placement Analysis (Checksum:41618496) REAL time: 9 secs
 
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 47 are locked
and 16 are not locked. If you would like to print the names of these IOs,
INFO:Place:834 - Only a subset of IOs are locked. Out of 64 IOs, 46 are locked
and 18 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:7388cd6e) REAL time: 10 secs
Phase 2.7 Design Feasibility Check (Checksum:41618496) REAL time: 9 secs
 
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:7388cd6e) REAL time: 10 secs
Phase 3.31 Local Placement Optimization (Checksum:41618496) REAL time: 9 secs
 
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:e9015cfe) REAL time: 14 secs
(Checksum:4fd9556b) REAL time: 14 secs
 
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:e9015cfe) REAL time: 14 secs
Phase 5.36 Local Placement Optimization (Checksum:4fd9556b) REAL time: 14 secs
 
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:e9015cfe) REAL time: 14 secs
Phase 6.30 Global Clock Region Assignment (Checksum:4fd9556b) REAL time: 14 secs
 
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:fcc976fb) REAL time: 15 secs
Phase 7.3 Local Placement Optimization (Checksum:7d1b7da) REAL time: 15 secs
 
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:fcc976fb) REAL time: 15 secs
Phase 8.5 Local Placement Optimization (Checksum:7d1b7da) REAL time: 15 secs
 
Phase 9.8 Global Placement
..
..
Phase 9.8 Global Placement (Checksum:4a08930d) REAL time: 15 secs
...
....
Phase 9.8 Global Placement (Checksum:9b697e6f) REAL time: 15 secs
 
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:4a08930d) REAL time: 15 secs
Phase 10.5 Local Placement Optimization (Checksum:9b697e6f) REAL time: 15 secs
 
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1a1797e0) REAL time: 16 secs
Phase 11.18 Placement Optimization (Checksum:fb37ccb) REAL time: 16 secs
 
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1a1797e0) REAL time: 16 secs
Phase 12.5 Local Placement Optimization (Checksum:fb37ccb) REAL time: 16 secs
 
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:bc560c6c) REAL time: 16 secs
Phase 13.34 Placement Validation (Checksum:ce7f4163) REAL time: 16 secs
 
Total REAL time to Placer completion: 16 secs
Total CPU time to Placer completion: 16 secs
84,16 → 84,16
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 224 out of 54,576 1%
Number used as Flip Flops: 224
Number of Slice Registers: 210 out of 54,576 1%
Number used as Flip Flops: 210
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 167 out of 27,288 1%
Number using O6 output only: 112
Number using O5 output only: 28
Number using O5 and O6: 27
Number of Slice LUTs: 143 out of 27,288 1%
Number used as logic: 129 out of 27,288 1%
Number using O6 output only: 79
Number using O5 output only: 15
Number using O5 and O6: 35
Number used as ROM: 0
Number used as Memory: 4 out of 6,408 1%
Number used as Dual Port RAM: 0
102,20 → 102,20
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 6
Number with same-slice register load: 4
Number used exclusively as route-thrus: 10
Number with same-slice register load: 8
Number with same-slice carry load: 2
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 102 out of 6,822 1%
Number of LUT Flip Flop pairs used: 272
Number with an unused Flip Flop: 64 out of 272 23%
Number with an unused LUT: 95 out of 272 34%
Number of fully used LUT-FF pairs: 113 out of 272 41%
Number of unique control sets: 26
Number of occupied Slices: 91 out of 6,822 1%
Number of LUT Flip Flop pairs used: 231
Number with an unused Flip Flop: 46 out of 231 19%
Number with an unused LUT: 88 out of 231 38%
Number of fully used LUT-FF pairs: 97 out of 231 41%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 68 out of 54,576 1%
to control set restrictions: 74 out of 54,576 1%
 
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
124,8 → 124,8
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 63 out of 218 28%
Number of LOCed IOBs: 47 out of 63 74%
Number of bonded IOBs: 64 out of 218 29%
Number of LOCed IOBs: 46 out of 64 71%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
132,8 → 132,8
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
152,9 → 152,9
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
 
Average Fanout of Non-Clock Nets: 3.18
Average Fanout of Non-Clock Nets: 2.86
 
Peak Memory Usage: 298 MB
Peak Memory Usage: 301 MB
Total REAL time to MAP completion: 17 secs
Total CPU time to MAP completion (all processors): 17 secs
 

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