OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

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    /spi_master_slave/trunk
    from Rev 10 to Rev 11
    Reverse comparison

Rev 10 → Rev 11

/rtl/spi_master.vhd
134,6 → 134,10
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
197,17 → 201,18
--================================================================================================================
architecture RTL of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic := '0'; -- output pipeline delay for spi sck
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic := '0'; -- output pipeline delay for spi sck
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal ena_sck_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
333,12 → 338,12
end process core_clock_gen_proc;
-----------------------------------------------------------------------------------------------
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
spi_sck_cpol_0_proc :
spi_sck_cpol_0_proc :
if CPOL = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate;
spi_sck_cpol_1_proc :
spi_sck_cpol_1_proc :
if CPOL = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
346,12 → 351,12
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
samp_ce_cpha_0_proc :
samp_ce_cpha_0_proc :
if CPHA = '0' generate
begin
samp_ce <= core_ce;
end generate;
samp_ce_cpha_1_proc :
samp_ce_cpha_1_proc :
if CPHA = '1' generate
begin
samp_ce <= core_n_ce;
358,17 → 363,19
end generate;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
fsm_ce_cpha_0_proc :
fsm_ce_cpha_0_proc :
if CPHA = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate;
fsm_ce_cpha_1_proc :
fsm_ce_cpha_1_proc :
if CPHA = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
 
ena_sck_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
379,11 → 386,11
--
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
-- if sclk_i'event and sclk_i = '1' then
-- if samp_ce = '1' then
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
-- end if;
-- end if;
end if;
end if;
end process rx_bit_proc;
 
--=============================================================================================
448,7 → 455,7
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked on rising edge
-- FF registers clocked synchronous to the fsm state
if sclk_i'event and sclk_i = '1' then
if fsm_ce = '1' then
sh_reg <= sh_next; -- shift register
460,6 → 467,12
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
-- if sclk_i'event and sclk_i = '1' then
-- if ena_sck_ce = '1' then
-- ena_sck_reg <= ena_sck_next; -- spi clock enable
-- end if;
-- end if;
end process core_reg_proc;
 
--=============================================================================================
539,12 → 552,19
-- enabling higher SCK frequency. The MOSI and SCK phase are compensated by the pipeline delay.
spi_sck_o_gen_proc : process (sclk_i, ena_sck_reg, spi_clk, spi_clk_reg) is
begin
if sclk_i'event and sclk_i = '1' then
if ena_sck_reg = '1' then
-- if sclk_i'event and sclk_i = '1' then
-- if ena_sck_reg = '1' then
-- spi_clk_reg <= spi_clk; -- copy the selected clock polarity
-- else
-- spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
-- end if;
-- end if;
if ena_sck_reg = '1' then
if sclk_i'event and sclk_i = '1' then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
spi_sck_o <= spi_clk_reg; -- connect register to output
end process spi_sck_o_gen_proc;
/syn/spi_master_envsettings.html
386,6 → 386,12
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-detail</td>
<td>Generate Detailed MAP Report</td>
<td>TRUE</td>
<td>TRUE</td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
/syn/spi_master_atlys_top_bit.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/syn/spi_master_atlys_top.vhd
15,8 → 15,6
-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
-- digital pod port.
-- The board switches are used to set the SPI_MASTER transmit data, and the SPI_SLAVE receive data drives the switch LEDs.
-- The pushbuttons drive the slave transmit data, and the master received data drives the parallel debug port.
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
29,17 → 27,17
-- external monitoring pins to the VHDCI ports.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
-- 6.25MHz, 1MHz and 500kHz
-- 2011/07/18 v1.12.0105 [JD] spi_master.vhd changed to fix CPHA='1' clock glitch.
--
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
 
entity spi_master_atlys_top is
Port (
gclk_i : in std_logic := 'X'; -- board clock input 100MHz
clear_i : in std_logic := '0'; -- btn used as clear signal
--- SPI interface ---
spi_ssel_o : out std_logic; -- spi port SSEL
spi_sck_o : out std_logic; -- spi port SCK
57,9 → 55,9
spi_rx_bit_m_o : out std_logic; -- master rx bit feedback
spi_rx_bit_s_o : out std_logic; -- slave rx bit feedback
spi_do_valid_o : out std_logic; -- spi data valid
spi_di_req_o : out std_logic; -- spi data request
spi_wren_o : out std_logic; -- spi write enable
spi_wren_ack_o : out std_logic -- spi write enable ack
spi_di_req_o : out std_logic -- spi data request
-- spi_wren_o : out std_logic; -- spi write enable
-- spi_wren_ack_o : out std_logic -- spi write enable ack
);
end spi_master_atlys_top;
 
74,7 → 72,9
constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
-- spi port generics
constant N : integer := 8; -- 8 bits
constant N : integer := 8; -- 8 bits
constant CPOL : std_logic := '0';
constant CPHA : std_logic := '0';
-- button definitions
constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
88,7 → 88,7
-- Type definitions
--=============================================================================================
type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch,
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish );
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish );
 
--=============================================================================================
-- Signals for state machine control
161,7 → 161,7
-- receives parallel data from the slide switches, transmits to slave port.
-- receives serial data from slave port, sends to 8bit parallel debug port.
Inst_spi_master_port: entity work.spi_master(rtl)
generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => gclk_i, -- system clock is used for serial and parallel ports
pclk_i => gclk_i,
176,7 → 176,7
do_o => spi_do_m,
rx_bit_reg_o => spi_rx_bit_m,
wren_i => spi_wren_reg_m,
wren_o => spi_wren_o,
-- wren_o => spi_wren_o,
wren_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port
);
 
187,7 → 187,7
-- receives parallel data from the pushbuttons, transmits to master port.
-- receives serial data from master port, sends to the 8 LEDs.
Inst_spi_slave_port: entity work.spi_slave(rtl)
generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => 3)
port map(
clk_i => gclk_i,
spi_ssel_i => spi_ssel, -- generated by the spi master
202,10 → 202,12
do_o => spi_do_s
);
 
spi_di_reg_s(7 downto 5) <= B"101"; -- get the slave transmit data from pushbuttons
spi_di_reg_s(4 downto 0) <= btn_data(5 downto 1);
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data
spi_rx_bit_s_o <= spi_rx_bit_s; -- connect rx_bit monitor for slave port
spi_di_reg_s(7) <= btn_data(btLEFT); -- get the slave transmit data from pushbuttons
spi_di_reg_s(6) <= btn_data(btCENTER);
spi_di_reg_s(5 downto 1) <= B"10101";
spi_di_reg_s(0) <= btn_data(btRIGHT);
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data
spi_rx_bit_s_o <= spi_rx_bit_s; -- connect rx_bit monitor for slave port
 
-- debounce for the input switches, with new data strobe output
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
231,16 → 233,16
-- CONSTANTS CONSTRAINTS CHECKING
--=============================================================================================
-- clock dividers shall not be zero
assert FSM_CE_DIV > 0
report "Constant 'FSM_CE_DIV' should not be zero"
assert FSM_CE_DIV > 0
report "Constant 'FSM_CE_DIV' should not be zero"
severity FAILURE;
-- minimum prefetch lookahead check
assert SPI_2X_CLK_DIV > 0
report "Constant 'SPI_2X_CLK_DIV' should not be zero"
assert SPI_2X_CLK_DIV > 0
report "Constant 'SPI_2X_CLK_DIV' should not be zero"
severity FAILURE;
-- maximum prefetch lookahead check
assert SAMP_CE_DIV > 0
report "Constant 'SAMP_CE_DIV' should not be zero"
assert SAMP_CE_DIV > 0
report "Constant 'SAMP_CE_DIV' should not be zero"
severity FAILURE;
 
--=============================================================================================
404,7 → 406,7
spi_miso_o_proc: spi_miso_o <= spi_miso;
spi_do_valid_o_proc: spi_do_valid_o <= spi_do_valid_m;
spi_di_req_o_proc: spi_di_req_o <= spi_di_req_m;
spi_wren_ack_o_proc: spi_wren_ack_o <= spi_wr_ack_m;
-- spi_wren_ack_o_proc: spi_wren_ack_o <= spi_wr_ack_m;
led_o_proc: led_o <= leds_reg; -- connect leds_reg signal to LED outputs
 
--=============================================================================================
/syn/spi_master.vhd
134,6 → 134,10
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
197,17 → 201,18
--================================================================================================================
architecture RTL of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic := '0'; -- output pipeline delay for spi sck
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic := '0'; -- output pipeline delay for spi sck
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal ena_sck_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
333,12 → 338,12
end process core_clock_gen_proc;
-----------------------------------------------------------------------------------------------
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
spi_sck_cpol_0_proc :
spi_sck_cpol_0_proc :
if CPOL = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate;
spi_sck_cpol_1_proc :
spi_sck_cpol_1_proc :
if CPOL = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
346,12 → 351,12
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
samp_ce_cpha_0_proc :
samp_ce_cpha_0_proc :
if CPHA = '0' generate
begin
samp_ce <= core_ce;
end generate;
samp_ce_cpha_1_proc :
samp_ce_cpha_1_proc :
if CPHA = '1' generate
begin
samp_ce <= core_n_ce;
358,17 → 363,19
end generate;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
fsm_ce_cpha_0_proc :
fsm_ce_cpha_0_proc :
if CPHA = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate;
fsm_ce_cpha_1_proc :
fsm_ce_cpha_1_proc :
if CPHA = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate;
 
ena_sck_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
379,11 → 386,11
--
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
-- if sclk_i'event and sclk_i = '1' then
-- if samp_ce = '1' then
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
-- end if;
-- end if;
end if;
end if;
end process rx_bit_proc;
 
--=============================================================================================
448,7 → 455,7
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked on rising edge
-- FF registers clocked synchronous to the fsm state
if sclk_i'event and sclk_i = '1' then
if fsm_ce = '1' then
sh_reg <= sh_next; -- shift register
460,6 → 467,12
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
-- if sclk_i'event and sclk_i = '1' then
-- if ena_sck_ce = '1' then
-- ena_sck_reg <= ena_sck_next; -- spi clock enable
-- end if;
-- end if;
end process core_reg_proc;
 
--=============================================================================================
539,12 → 552,19
-- enabling higher SCK frequency. The MOSI and SCK phase are compensated by the pipeline delay.
spi_sck_o_gen_proc : process (sclk_i, ena_sck_reg, spi_clk, spi_clk_reg) is
begin
if sclk_i'event and sclk_i = '1' then
if ena_sck_reg = '1' then
-- if sclk_i'event and sclk_i = '1' then
-- if ena_sck_reg = '1' then
-- spi_clk_reg <= spi_clk; -- copy the selected clock polarity
-- else
-- spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
-- end if;
-- end if;
if ena_sck_reg = '1' then
if sclk_i'event and sclk_i = '1' then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
spi_sck_o <= spi_clk_reg; -- connect register to output
end process spi_sck_o_gen_proc;
/syn/usage_statistics_webtalk.html
0,0 → 1,1096
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>&nbsp;<BR><HR>&nbsp;<BR>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD><xtag-property name="ProductVersion">ISE:13.1</xtag-property><xtag-property name="ProductConfiguration"> (WebPack)</xtag-property><xtag-property name="BuildVersion"> - O.40d</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
<TD><xtag-property name="TargetFamily">Spartan6</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
<TD><xtag-property name="OSPlatform">NT</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD><xtag-property name="TargetDevice">xc6slx45</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">d557c6c4bb5b4e4fa669c510e7b04848</xtag-property>.<xtag-property name="ProjectID">2C5BE631B69F48AB8C2F24035AF7A13B</xtag-property>.<xtag-property name="ProjectIteration">31</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Registration ID</B></TD>
<TD><xtag-property name="RegistrationID">205970357_0_0_751</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
<TD><xtag-property name="TargetSpeed">-2</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2011-07-18T02:50:20</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="UserEnvironment">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows 7 , 32-bit</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 1 (build 7601)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3066 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows 7 , 32-bit</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 1 (build 7601)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3066 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Device Usage Statistics</B></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="MacroStatistics">
<TD>
<xtag-group><xtag-group-name name="Adders/Subtractors=2">Adders/Subtractors=2</xtag-group-name>
<UL>
<LI><xtag-item1>4-bit subtractor=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Comparators=14">Comparators=14</xtag-group-name>
<UL>
<LI><xtag-item1>4-bit comparator greater=8</xtag-item1></LI>
<LI><xtag-item1>6-bit comparator equal=1</xtag-item1></LI>
<LI><xtag-item1>6-bit comparator not equal=2</xtag-item1></LI>
<LI><xtag-item1>8-bit comparator equal=1</xtag-item1></LI>
<LI><xtag-item1>8-bit comparator not equal=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Counters=5">Counters=5</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit up counter=3</xtag-item1></LI>
<LI><xtag-item1>14-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>16-bit up counter=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FSMs=1">FSMs=1</xtag-group-name>
</xtag-group>
<xtag-group><xtag-group-name name="Multiplexers=42">Multiplexers=42</xtag-group-name>
<UL>
<LI><xtag-item1>1-bit 2-to-1 multiplexer=21</xtag-item1></LI>
<LI><xtag-item1>4-bit 2-to-1 multiplexer=13</xtag-item1></LI>
<LI><xtag-item1>8-bit 2-to-1 multiplexer=8</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="Registers=171">Registers=171</xtag-group-name>
<UL>
<LI><xtag-item1>Flip-Flops=171</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DesignStatistics">
<TD>
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>AGG_BONDED_IO=39</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=39</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=39</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=70</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=39</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=76</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=41</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=78</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=195</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI>
<LI><xtag-item1>NUM_IOB_FF=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=39</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=32</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=27</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=48</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=6</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=6</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=26</xtag-item1></LI>
<LI><xtag-item1>NUM_OLOGIC2=9</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=8</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=1</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=61</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=8</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=20</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=177</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=171</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=12</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=2</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=51</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=311</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=23</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=11</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=67</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=35</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=253</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=53</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=78</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=38</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=38</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=417</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=268</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=257</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=24</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=178</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=530</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED2=9</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=423</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=90</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=350</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=22</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=62</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=62</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=20</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=19</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=17</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=8</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
<xtag-section name="DeviceUsage">
<TD>
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
<UL>
<LI><xtag-item2>BUFG=2</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI>
<LI><xtag-item2>CARRY4=8</xtag-item2></LI>
<LI><xtag-item2>FF_SR=30</xtag-item2></LI>
<LI><xtag-item2>HARD0=2</xtag-item2></LI>
<LI><xtag-item2>IOB=39</xtag-item2></LI>
<LI><xtag-item2>IOB_IMUX=15</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=15</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=24</xtag-item2></LI>
<LI><xtag-item2>LUT5=65</xtag-item2></LI>
<LI><xtag-item2>LUT6=108</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=2</xtag-item2></LI>
<LI><xtag-item2>OLOGIC2=9</xtag-item2></LI>
<LI><xtag-item2>OLOGIC2_OUTFF=9</xtag-item2></LI>
<LI><xtag-item2>PAD=39</xtag-item2></LI>
<LI><xtag-item2>REG_SR=141</xtag-item2></LI>
<LI><xtag-item2>SLICEL=8</xtag-item2></LI>
<LI><xtag-item2>SLICEM=1</xtag-item2></LI>
<LI><xtag-item2>SLICEX=61</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Configuration Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:26] [CK_INV:4]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:30]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:28] [SYNC:2]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item3>DRIVEATTRBOX=[12:24]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:24]</xtag-item3></LI>
<LI><xtag-item3>SUSPEND=[3STATE:24]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
<UL>
<LI><xtag-item3>LUT_OR_MEM=[LUT:1]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:2] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LUT_OR_MEM=[RAM:2]</xtag-item3></LI>
<LI><xtag-item3>RAMMODE=[SRL16:2]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name>
<UL>
<LI><xtag-item3>CLK0=[CLK0_INV:0] [CLK0:9]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name>
<UL>
<LI><xtag-item3>CK0=[CK0_INV:0] [CK0:9]</xtag-item3></LI>
<LI><xtag-item3>OUTFFTYPE=[FF:9]</xtag-item3></LI>
<LI><xtag-item3>SRINIT_OQ=[0:9]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:125] [CK_INV:16]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:141]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:139] [SRINIT1:2]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:121] [SYNC:20]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:5] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:1] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:46] [CLK_INV:6]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Pin Data</B></TD></TR><TR VALIGN=TOP>
<xtag-section name="ReportConfigData">
<TD>
<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
<UL>
<LI><xtag-item1>I0=2</xtag-item1></LI>
<LI><xtag-item1>O=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL>
<LI><xtag-item1>CIN=6</xtag-item1></LI>
<LI><xtag-item1>CO3=6</xtag-item1></LI>
<LI><xtag-item1>CYINIT=2</xtag-item1></LI>
<LI><xtag-item1>DI0=8</xtag-item1></LI>
<LI><xtag-item1>DI1=7</xtag-item1></LI>
<LI><xtag-item1>DI2=7</xtag-item1></LI>
<LI><xtag-item1>DI3=6</xtag-item1></LI>
<LI><xtag-item1>O0=8</xtag-item1></LI>
<LI><xtag-item1>O1=8</xtag-item1></LI>
<LI><xtag-item1>O2=7</xtag-item1></LI>
<LI><xtag-item1>O3=7</xtag-item1></LI>
<LI><xtag-item1>S0=8</xtag-item1></LI>
<LI><xtag-item1>S1=8</xtag-item1></LI>
<LI><xtag-item1>S2=7</xtag-item1></LI>
<LI><xtag-item1>S3=7</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=14</xtag-item1></LI>
<LI><xtag-item1>CK=30</xtag-item1></LI>
<LI><xtag-item1>D=30</xtag-item1></LI>
<LI><xtag-item1>Q=30</xtag-item1></LI>
<LI><xtag-item1>SR=4</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
<UL>
<LI><xtag-item1>0=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
<UL>
<LI><xtag-item1>I=15</xtag-item1></LI>
<LI><xtag-item1>O=24</xtag-item1></LI>
<LI><xtag-item1>PAD=39</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name>
<UL>
<LI><xtag-item1>I=15</xtag-item1></LI>
<LI><xtag-item1>OUT=15</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
<UL>
<LI><xtag-item1>OUT=15</xtag-item1></LI>
<LI><xtag-item1>PAD=15</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=24</xtag-item1></LI>
<LI><xtag-item1>OUT=24</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A1=15</xtag-item1></LI>
<LI><xtag-item1>A2=23</xtag-item1></LI>
<LI><xtag-item1>A3=14</xtag-item1></LI>
<LI><xtag-item1>A4=16</xtag-item1></LI>
<LI><xtag-item1>A5=19</xtag-item1></LI>
<LI><xtag-item1>O5=65</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=39</xtag-item1></LI>
<LI><xtag-item1>A2=58</xtag-item1></LI>
<LI><xtag-item1>A3=69</xtag-item1></LI>
<LI><xtag-item1>A4=90</xtag-item1></LI>
<LI><xtag-item1>A5=91</xtag-item1></LI>
<LI><xtag-item1>A6=107</xtag-item1></LI>
<LI><xtag-item1>O6=108</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
<UL>
<LI><xtag-item1>A3=1</xtag-item1></LI>
<LI><xtag-item1>A4=1</xtag-item1></LI>
<LI><xtag-item1>A5=1</xtag-item1></LI>
<LI><xtag-item1>O5=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=2</xtag-item1></LI>
<LI><xtag-item1>A2=2</xtag-item1></LI>
<LI><xtag-item1>A3=2</xtag-item1></LI>
<LI><xtag-item1>A4=2</xtag-item1></LI>
<LI><xtag-item1>A5=2</xtag-item1></LI>
<LI><xtag-item1>A6=2</xtag-item1></LI>
<LI><xtag-item1>CLK=2</xtag-item1></LI>
<LI><xtag-item1>DI2=2</xtag-item1></LI>
<LI><xtag-item1>O6=2</xtag-item1></LI>
<LI><xtag-item1>WE=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name>
<UL>
<LI><xtag-item1>CLK0=9</xtag-item1></LI>
<LI><xtag-item1>D1=9</xtag-item1></LI>
<LI><xtag-item1>OQ=9</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name>
<UL>
<LI><xtag-item1>CK0=9</xtag-item1></LI>
<LI><xtag-item1>D1=9</xtag-item1></LI>
<LI><xtag-item1>Q=9</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
<UL>
<LI><xtag-item1>PAD=39</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=69</xtag-item1></LI>
<LI><xtag-item1>CK=141</xtag-item1></LI>
<LI><xtag-item1>D=141</xtag-item1></LI>
<LI><xtag-item1>Q=141</xtag-item1></LI>
<LI><xtag-item1>SR=23</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
<UL>
<LI><xtag-item1>0=2</xtag-item1></LI>
<LI><xtag-item1>1=2</xtag-item1></LI>
<LI><xtag-item1>OUT=2</xtag-item1></LI>
<LI><xtag-item1>S0=2</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A4=3</xtag-item1></LI>
<LI><xtag-item1>A5=5</xtag-item1></LI>
<LI><xtag-item1>A6=8</xtag-item1></LI>
<LI><xtag-item1>AMUX=5</xtag-item1></LI>
<LI><xtag-item1>AQ=4</xtag-item1></LI>
<LI><xtag-item1>AX=1</xtag-item1></LI>
<LI><xtag-item1>B4=4</xtag-item1></LI>
<LI><xtag-item1>B5=3</xtag-item1></LI>
<LI><xtag-item1>B6=8</xtag-item1></LI>
<LI><xtag-item1>BMUX=4</xtag-item1></LI>
<LI><xtag-item1>BQ=5</xtag-item1></LI>
<LI><xtag-item1>BX=1</xtag-item1></LI>
<LI><xtag-item1>C4=4</xtag-item1></LI>
<LI><xtag-item1>C5=3</xtag-item1></LI>
<LI><xtag-item1>C6=7</xtag-item1></LI>
<LI><xtag-item1>CIN=6</xtag-item1></LI>
<LI><xtag-item1>CLK=5</xtag-item1></LI>
<LI><xtag-item1>CMUX=3</xtag-item1></LI>
<LI><xtag-item1>COUT=6</xtag-item1></LI>
<LI><xtag-item1>CQ=5</xtag-item1></LI>
<LI><xtag-item1>CX=1</xtag-item1></LI>
<LI><xtag-item1>D=1</xtag-item1></LI>
<LI><xtag-item1>D1=1</xtag-item1></LI>
<LI><xtag-item1>D2=1</xtag-item1></LI>
<LI><xtag-item1>D3=1</xtag-item1></LI>
<LI><xtag-item1>D4=5</xtag-item1></LI>
<LI><xtag-item1>D5=4</xtag-item1></LI>
<LI><xtag-item1>D6=7</xtag-item1></LI>
<LI><xtag-item1>DMUX=3</xtag-item1></LI>
<LI><xtag-item1>DQ=5</xtag-item1></LI>
<LI><xtag-item1>DX=1</xtag-item1></LI>
<LI><xtag-item1>SR=4</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
<UL>
<LI><xtag-item1>C1=1</xtag-item1></LI>
<LI><xtag-item1>C2=1</xtag-item1></LI>
<LI><xtag-item1>C3=1</xtag-item1></LI>
<LI><xtag-item1>C4=1</xtag-item1></LI>
<LI><xtag-item1>C5=1</xtag-item1></LI>
<LI><xtag-item1>C6=1</xtag-item1></LI>
<LI><xtag-item1>CE=1</xtag-item1></LI>
<LI><xtag-item1>CI=1</xtag-item1></LI>
<LI><xtag-item1>CLK=1</xtag-item1></LI>
<LI><xtag-item1>CQ=1</xtag-item1></LI>
<LI><xtag-item1>D1=1</xtag-item1></LI>
<LI><xtag-item1>D2=1</xtag-item1></LI>
<LI><xtag-item1>D3=1</xtag-item1></LI>
<LI><xtag-item1>D4=1</xtag-item1></LI>
<LI><xtag-item1>D5=1</xtag-item1></LI>
<LI><xtag-item1>D6=1</xtag-item1></LI>
<LI><xtag-item1>DI=1</xtag-item1></LI>
<LI><xtag-item1>DQ=1</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=20</xtag-item1></LI>
<LI><xtag-item1>A1=16</xtag-item1></LI>
<LI><xtag-item1>A2=19</xtag-item1></LI>
<LI><xtag-item1>A3=24</xtag-item1></LI>
<LI><xtag-item1>A4=26</xtag-item1></LI>
<LI><xtag-item1>A5=27</xtag-item1></LI>
<LI><xtag-item1>A6=27</xtag-item1></LI>
<LI><xtag-item1>AMUX=11</xtag-item1></LI>
<LI><xtag-item1>AQ=32</xtag-item1></LI>
<LI><xtag-item1>AX=24</xtag-item1></LI>
<LI><xtag-item1>B=7</xtag-item1></LI>
<LI><xtag-item1>B1=10</xtag-item1></LI>
<LI><xtag-item1>B2=17</xtag-item1></LI>
<LI><xtag-item1>B3=17</xtag-item1></LI>
<LI><xtag-item1>B4=18</xtag-item1></LI>
<LI><xtag-item1>B5=17</xtag-item1></LI>
<LI><xtag-item1>B6=17</xtag-item1></LI>
<LI><xtag-item1>BMUX=7</xtag-item1></LI>
<LI><xtag-item1>BQ=32</xtag-item1></LI>
<LI><xtag-item1>BX=22</xtag-item1></LI>
<LI><xtag-item1>C=8</xtag-item1></LI>
<LI><xtag-item1>C1=6</xtag-item1></LI>
<LI><xtag-item1>C2=12</xtag-item1></LI>
<LI><xtag-item1>C3=14</xtag-item1></LI>
<LI><xtag-item1>C4=15</xtag-item1></LI>
<LI><xtag-item1>C5=16</xtag-item1></LI>
<LI><xtag-item1>C6=15</xtag-item1></LI>
<LI><xtag-item1>CE=25</xtag-item1></LI>
<LI><xtag-item1>CLK=52</xtag-item1></LI>
<LI><xtag-item1>CMUX=9</xtag-item1></LI>
<LI><xtag-item1>CQ=27</xtag-item1></LI>
<LI><xtag-item1>CX=19</xtag-item1></LI>
<LI><xtag-item1>D=11</xtag-item1></LI>
<LI><xtag-item1>D1=11</xtag-item1></LI>
<LI><xtag-item1>D2=15</xtag-item1></LI>
<LI><xtag-item1>D3=16</xtag-item1></LI>
<LI><xtag-item1>D4=19</xtag-item1></LI>
<LI><xtag-item1>D5=19</xtag-item1></LI>
<LI><xtag-item1>D6=18</xtag-item1></LI>
<LI><xtag-item1>DMUX=10</xtag-item1></LI>
<LI><xtag-item1>DQ=29</xtag-item1></LI>
<LI><xtag-item1>DX=22</xtag-item1></LI>
<LI><xtag-item1>SR=6</xtag-item1></LI>
</UL>
</TD>
<TD>
</xtag-group>
</TD>
</xtag-section>
</TR></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD><B>Tool Usage</B></TD></TR>
<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>netgen -intstyle ise -ar Structure -tm &lt;design&gt; -w -dir netgen/synthesis -ofmt vhdl -sim &lt;fname&gt;.ngc &lt;fname&gt;.vhd</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm &lt;design&gt; -w -dir netgen/translate -ofmt vhdl -sim &lt;fname&gt;.ngd &lt;fname&gt;.vhd</xtag-cmdline></LI>
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf &lt;fname&gt;.pcf -rpw 100 -tpw 0 -ar Structure -tm &lt;design&gt; -w -dir netgen/map -ofmt vhdl -sim &lt;fname&gt;.ncd &lt;fname&gt;.vhd</xtag-cmdline></LI>
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf &lt;fname&gt;.pcf -rpw 100 -tpw 0 -ar Structure -tm &lt;design&gt; -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim &lt;fname&gt;.ncd &lt;fname&gt;.vhd</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx45-csg324-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>XSLTProcess</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>3</xtag-total-run-started></td>
<td><xtag-total-run-finished>3</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>137</xtag-total-run-started></td>
<td><xtag-total-run-finished>137</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>compxlib</xtag-program-name></td>
<td><xtag-total-run-started>2</xtag-total-run-started></td>
<td><xtag-total-run-finished>2</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>cpldfit</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>cse_server</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>hprep6</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ibiswriter</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>444</xtag-total-run-started></td>
<td><xtag-total-run-finished>429</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>netgen</xtag-program-name></td>
<td><xtag-total-run-started>459</xtag-total-run-started></td>
<td><xtag-total-run-finished>451</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngc2edif</xtag-program-name></td>
<td><xtag-total-run-started>10</xtag-total-run-started></td>
<td><xtag-total-run-finished>10</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>476</xtag-total-run-started></td>
<td><xtag-total-run-finished>476</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>462</xtag-total-run-started></td>
<td><xtag-total-run-finished>407</xtag-total-run-finished></td>
<td><xtag-total-error>14</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>taengine</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>433</xtag-total-run-started></td>
<td><xtag-total-run-finished>433</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>tsim</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>xpwr</xtag-program-name></td>
<td><xtag-total-run-started>2</xtag-total-run-started></td>
<td><xtag-total-run-finished>2</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>754</xtag-total-run-started></td>
<td><xtag-total-run-finished>749</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISEHelpViewerData">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Help Statistics</B></TD></TR>
<TR VALIGN=TOP><TD COLSPAN=2><xtag-group><B><xtag-group-name name="OpenedHelpFiles">
Help files</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_fpga_design_flow_overview.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_overview.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
 
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_simulation_test_bench.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_using_the_design_views.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
 
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_working_with_vhdl_libraries.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ise_p_using_smartguide.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
 
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/ism_r_p_printing.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pce_db_period-dialog.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
 
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pn_c_using_console_error_warning_tabs.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pn_db_adding_source_files.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
 
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pn_db_nsw_summary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pn_p_changing_source_properties.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
 
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pn_r_library_tab.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pp_p_process_generate_post_translate_simulation_model.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="Project Statistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
<TR>
<TD><xtag-process-property-name>PROPEXT_MapGlobalOptimization_spartan6</xtag-process-property-name>=<xtag-process-property-value>Area</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_Enable_Message_Filtering</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_FitterReportFormat</xtag-process-property-name>=<xtag-process-property-value>HTML</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_LastAppliedGoal</xtag-design-property-name>=<xtag-design-property-value>Balanced</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_LastAppliedStrategy</xtag-design-property-name>=<xtag-design-property-value>Xilinx Default (unlocked)</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_ManualCompileOrderImp</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_MapLUTCombining_spartan6</xtag-process-property-name>=<xtag-process-property-value>Area</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_Simulator</xtag-design-property-name>=<xtag-design-property-value>ISim (VHDL/Verilog)</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_SynthExtractRAM</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_SynthExtractROM</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_SynthFsmEncode</xtag-process-property-name>=<xtag-process-property-value>Gray</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_SynthOptEffort_spartan6</xtag-process-property-name>=<xtag-process-property-value>High</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_SynthShiftRegExtract</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_SynthTopFile</xtag-process-property-name>=<xtag-process-property-value>changed</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_Top_Level_Module_Type</xtag-design-property-name>=<xtag-design-property-value>HDL</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_UseSmartGuide</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_UserBrowsedStrategyFiles</xtag-process-property-name>=<xtag-process-property-value>C:/Xilinx/13.1/ISE_DS/ISE/data/default.xds</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_UserConstraintEditorPreference</xtag-process-property-name>=<xtag-process-property-value>Constraints Editor</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_VHDLSourceAnalysisStandard</xtag-process-property-name>=<xtag-process-property-value>VHDL-200X</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2011-07-07T09:55:20</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>2C5BE631B69F48AB8C2F24035AF7A13B</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>31</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_xilxBitgStart_Clk_DriveDone</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_xilxMapReportDetail</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_xstLUTCombining_spartan6</xtag-process-property-name>=<xtag-process-property-value>Area</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_AutoTop</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevFamily</xtag-design-property-name>=<xtag-design-property-value>Spartan6</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROP_MapExtraEffort_spartan6</xtag-process-property-name>=<xtag-process-property-value>Normal</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_xilxMapEnableMultiThreading</xtag-process-property-name>=<xtag-process-property-value>2</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-process-property-name>PROPEXT_xilxPARextraEffortLevel_spartan6</xtag-process-property-name>=<xtag-process-property-value>Normal</xtag-process-property-value></TD>
<TD><xtag-design-property-name>PROP_DevDevice</xtag-design-property-name>=<xtag-design-property-value>xc6slx45</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_DevFamilyPMName</xtag-design-property-name>=<xtag-design-property-value>spartan6</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>csg324</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_parEnableMultiThreading_spartan6</xtag-process-property-name>=<xtag-process-property-value>4</xtag-process-property-value></TD>
 
</TR><TR><TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-2</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>VHDL</xtag-design-property-value></TD>
 
</TR><TR><TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
<TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>4</xtag-source-property-value></TD>
</TR></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="UnisimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>65</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>74</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>16</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>18</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>25</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>12</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>19</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>46</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>30</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>65</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>74</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>16</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>18</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>25</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>12</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>19</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>46</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>30</xtag-postunisim-param-value></TD>
</xtag-section></TABLE>
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