URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/spi_master_slave
- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/trunk/rtl/spi_loopback_test.vhd
0,0 → 1,277
-------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Jonny Doin |
-- |
-- Create Date: 22:59:18 04/25/2011 |
-- Design Name: |
-- Module Name: C:/dropbox/Dropbox/VHDL_training/projects/SPI_interface/spi_loopback_test.vhd |
-- Project Name: SPI_interface |
-- Target Device: Spartan-6 |
-- Tool versions: ISE 13.1 |
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested |
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave' |
-- module, simulating the internal working of each design. |
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for |
-- both modules, and also a different clock domain for each parallel interface. |
-- Different values for PREFETCH for each interface can be tested, to model the best value |
-- for the pipelined memory / bus that is attached to the di/do ports. |
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with |
-- 8 words of data to be sent, synchronous to each clock and flow control signals. |
-- |
-- |
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave' |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 1.05 - Implemented FIFO simulation for each interface. |
-- Additional Comments: |
-- |
-- Notes: |
-- This testbench has been automatically generated using types std_logic and |
-- std_logic_vector for the ports of the unit under test. Xilinx recommends |
-- that these types always be used for the top-level I/O of a design in order |
-- to guarantee that the testbench will bind correctly to the post-implementation |
-- simulation model. |
-------------------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
|
--library WORK; |
--use WORK.DEBUG_PKG.ALL; |
|
ENTITY spi_loopback_test IS |
Generic ( N : positive := 32); -- 32bit serial word length is default |
END spi_loopback_test; |
|
ARCHITECTURE behavior OF spi_loopback_test IS |
|
--========================================================= |
-- Component Declarations for the Unit Under Test (UUT) |
--========================================================= |
|
COMPONENT spi_loopback |
PORT( |
----------------MASTER----------------------- |
m_spi_clk_i : IN std_logic := 'X'; |
m_par_clk_i : IN std_logic := 'X'; |
m_rst_i : IN std_logic := 'X'; |
m_spi_ssel_o : OUT std_logic; |
m_spi_sck_o : OUT std_logic; |
m_spi_mosi_o : OUT std_logic; |
m_spi_miso_i : IN std_logic := 'X'; |
m_di_i : IN std_logic_vector(31 downto 0) := (others => 'X'); |
m_do_o : OUT std_logic_vector(31 downto 0); |
m_di_rdy_o : OUT std_logic; |
m_wren_i : IN std_logic := 'X'; |
m_do_valid_o : OUT std_logic; |
-- m_state_dbg_o : OUT std_logic_vector(5 downto 0); |
-- m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0); |
----------------SLAVE----------------------- |
s_clk_i : IN std_logic := 'X'; |
s_rst_i : IN std_logic := 'X'; |
s_spi_ssel_i : IN std_logic := 'X'; |
s_spi_sck_i : IN std_logic := 'X'; |
s_spi_mosi_i : IN std_logic := 'X'; |
s_spi_miso_o : OUT std_logic; |
s_di_i : IN std_logic_vector(31 downto 0) := (others => 'X'); |
s_do_o : OUT std_logic_vector(31 downto 0); |
s_di_rdy_o : OUT std_logic; |
s_wren_i : IN std_logic := 'X'; |
s_do_valid_o : OUT std_logic |
-- s_state_dbg_o : OUT std_logic_vector(5 downto 0); |
-- s_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0) |
); |
END COMPONENT; |
|
|
--========================================================= |
-- constants |
--========================================================= |
constant fifo_memory_size : integer := 8; |
|
--========================================================= |
-- types |
--========================================================= |
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0); |
|
--========================================================= |
-- signals to connect the instances |
--========================================================= |
-- internal clk and rst |
signal spi_2x_clk : std_logic := '0'; -- This is the SPI_SCK clock source. Must be 2x spi sck. |
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck. |
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck. |
signal rst : std_logic := 'X'; |
-- spi bus wires |
signal spi_sck : std_logic; |
signal spi_ssel : std_logic; |
signal spi_miso : std_logic; |
signal spi_mosi : std_logic; |
-- master parallel interface |
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_m : std_logic_vector (N-1 downto 0); |
signal do_valid_m : std_logic; |
signal di_rdy_m : std_logic; |
signal wren_m : std_logic := '0'; |
-- signal sh_reg_m : integer; |
-- signal state_m : integer; |
-- slave parallel interface |
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_s : std_logic_vector (N-1 downto 0); |
signal do_valid_s : std_logic; |
signal di_rdy_s : std_logic; |
signal wren_s : std_logic := '0'; |
-- signal sh_reg_s : integer; |
-- signal state_s : integer; |
|
--========================================================= |
-- Clock period definitions |
--========================================================= |
constant spi_2x_clk_period : time := 20 ns; -- 33.3MHz SPI SCK clock |
constant m_clk_period : time := 8 ns; -- 125MHz master parallel clock |
constant s_clk_period : time := 8 ns; -- 125MHz slave parallel clock |
|
BEGIN |
|
--========================================================= |
-- instantiation of UUT |
--========================================================= |
|
Inst_spi_loopback: spi_loopback PORT MAP( |
----------------MASTER----------------------- |
m_spi_clk_i => spi_2x_clk, |
m_par_clk_i => m_clk, |
m_rst_i => rst, |
m_spi_ssel_o => spi_ssel, |
m_spi_sck_o => spi_sck, |
m_spi_mosi_o => spi_mosi, |
m_spi_miso_i => spi_miso, |
m_di_i => di_m, |
m_do_o => do_m, |
m_di_rdy_o => di_rdy_m, |
m_wren_i => wren_m, |
m_do_valid_o => do_valid_m, |
-- m_state_dbg_o => state_m, |
-- m_sh_reg_dbg_o => sh_reg_m, |
----------------SLAVE----------------------- |
s_clk_i => s_clk, |
s_rst_i => rst, |
s_spi_ssel_i => spi_ssel, |
s_spi_sck_i => spi_sck, |
s_spi_mosi_i => spi_mosi, |
s_spi_miso_o => spi_miso, |
s_di_i => di_s, |
s_do_o => do_s, |
s_di_rdy_o => di_rdy_s, |
s_wren_i => wren_s, |
s_do_valid_o => do_valid_s |
-- s_state_dbg_o => state_s, |
-- s_sh_reg_dbg_o => sh_reg_s |
); |
|
--========================================================= |
-- Clock generator processes |
--========================================================= |
spi_2x_clk_process : process |
begin |
spi_2x_clk <= '0'; |
wait for spi_2x_clk_period/2; |
spi_2x_clk <= '1'; |
wait for spi_2x_clk_period/2; |
end process spi_2x_clk_process; |
|
m_clk_process : process |
begin |
m_clk <= '0'; |
wait for m_clk_period/2; |
m_clk <= '1'; |
wait for m_clk_period/2; |
end process m_clk_process; |
|
s_clk_process : process |
begin |
s_clk <= '0'; |
wait for s_clk_period/2; |
s_clk <= '1'; |
wait for s_clk_period/2; |
end process s_clk_process; |
|
--========================================================= |
-- rst_i process |
--========================================================= |
rst <= '0', '1' after 100 ns, '0' after 200 ns; |
|
--========================================================= |
-- Master interface process |
--========================================================= |
master_tx_fifo_proc: process is |
variable fifo_memory : fifo_memory_type := |
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789"); |
variable fifo_head : integer range 0 to fifo_memory_size-1; |
begin |
-- synchronous rst_i |
wait until rst = '1'; |
wait until m_clk'event and m_clk = '1'; |
di_m <= (others => '0'); |
wren_m <= '0'; |
fifo_head := 0; |
wait until rst = '0'; |
-- load next fifo contents into shift register |
for cnt in 0 to fifo_memory_size-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until di_rdy_m = '1'; -- wait shift register request for data |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '1'; -- write data into spi master |
wait until di_rdy_m = '0'; -- wait data be accepted to compute next pointer |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '0'; -- remove write enable signal |
end loop; |
wait; |
end process master_tx_fifo_proc; |
|
|
--========================================================= |
-- Slave interface process |
--========================================================= |
slave_tx_fifo_proc: process is |
variable fifo_memory : fifo_memory_type := |
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394"); |
variable fifo_head : integer range 0 to fifo_memory_size-1; |
begin |
-- synchronous rst_i |
wait until rst = '1'; |
wait until s_clk'event and s_clk = '1'; |
di_s <= (others => '0'); |
wren_s <= '0'; |
fifo_head := 0; |
wait until rst = '0'; |
-- load next fifo contents into shift register |
for cnt in 0 to fifo_memory_size-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until di_rdy_s = '1'; -- wait shift register request for data |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wren_s <= '1'; -- write data into shift register |
wait until di_rdy_s = '0'; -- wait data be accepted to compute next pointer |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wren_s <= '0'; -- remove write enable signal |
end loop; |
wait; |
end process slave_tx_fifo_proc; |
|
--========================================================= |
-- Debug processes |
--========================================================= |
|
-- sh_reg_m <= dbg_shift_m; |
-- state_m <= dbg_state_m; |
-- sh_reg_s <= dbg_shift_s; |
-- state_s <= dbg_state_s; |
|
END ARCHITECTURE behavior; |
/trunk/rtl/spi_loopback.vhd
0,0 → 1,143
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 23:44:37 05/17/2011 |
-- Design Name: |
-- Module Name: spi_loopback - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--use IEEE.NUMERIC_STD.ALL; |
|
-- Uncomment the following library declaration if instantiating |
-- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity spi_loopback is |
port( |
----------------MASTER----------------------- |
m_spi_clk_i : IN std_logic; |
m_par_clk_i : IN std_logic; |
m_rst_i : IN std_logic; |
m_spi_ssel_o : OUT std_logic; |
m_spi_sck_o : OUT std_logic; |
m_spi_mosi_o : OUT std_logic; |
m_spi_miso_i : IN std_logic; |
m_di_i : IN std_logic_vector(31 downto 0); |
m_do_o : OUT std_logic_vector(31 downto 0); |
m_di_rdy_o : OUT std_logic; |
m_wren_i : IN std_logic; |
m_do_valid_o : OUT std_logic; |
-- m_state_dbg_o : OUT std_logic_vector(5 downto 0); |
-- m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0); |
----------------SLAVE----------------------- |
s_clk_i : IN std_logic; |
s_rst_i : IN std_logic; |
s_spi_ssel_i : IN std_logic; |
s_spi_sck_i : IN std_logic; |
s_spi_mosi_i : IN std_logic; |
s_spi_miso_o : OUT std_logic; |
s_di_i : IN std_logic_vector(31 downto 0); |
s_do_o : OUT std_logic_vector(31 downto 0); |
s_di_rdy_o : OUT std_logic; |
s_wren_i : IN std_logic; |
s_do_valid_o : OUT std_logic |
-- s_state_dbg_o : OUT std_logic_vector(5 downto 0); |
-- s_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0) |
); |
end spi_loopback; |
|
architecture Behavioral of spi_loopback is |
|
COMPONENT spi_master |
PORT( |
spi_2x_clk_i : IN std_logic; |
par_clk_i : IN std_logic; |
rst_i : IN std_logic; |
spi_miso_i : IN std_logic; |
di_i : IN std_logic_vector(31 downto 0); |
wren_i : IN std_logic; |
spi_ssel_o : OUT std_logic; |
spi_sck_o : OUT std_logic; |
spi_mosi_o : OUT std_logic; |
do_o : OUT std_logic_vector(31 downto 0); |
di_rdy_o : OUT std_logic; |
do_valid_o : OUT std_logic |
-- state_dbg_o : OUT std_logic_vector(5 downto 0); |
-- sh_reg_dbg_o : OUT std_logic_vector(31 downto 0) |
); |
END COMPONENT; |
|
COMPONENT spi_slave |
PORT( |
clk_i : IN std_logic; |
rst_i : IN std_logic; |
spi_ssel_i : IN std_logic; |
spi_sck_i : IN std_logic; |
spi_mosi_i : IN std_logic; |
di_i : IN std_logic_vector(31 downto 0); |
wren_i : IN std_logic; |
spi_miso_o : OUT std_logic; |
do_o : OUT std_logic_vector(31 downto 0); |
di_rdy_o : OUT std_logic; |
do_valid_o : OUT std_logic |
-- state_dbg_o : OUT std_logic_vector(5 downto 0); |
-- sh_reg_dbg_o : OUT std_logic_vector(31 downto 0) |
); |
END COMPONENT; |
|
begin |
|
Inst_spi_master: spi_master PORT MAP( |
spi_2x_clk_i => m_spi_clk_i, |
par_clk_i => m_par_clk_i, |
rst_i => m_rst_i, |
spi_ssel_o => m_spi_ssel_o, |
spi_sck_o => m_spi_sck_o, |
spi_mosi_o => m_spi_mosi_o, |
spi_miso_i => m_spi_miso_i, |
di_i => m_di_i, |
do_o => m_do_o, |
di_rdy_o => m_di_rdy_o, |
wren_i => m_wren_i, |
do_valid_o => m_do_valid_o |
-- state_dbg_o => m_state_dbg_o, |
-- sh_reg_dbg_o => m_sh_reg_dbg_o |
); |
|
Inst_spi_slave: spi_slave PORT MAP( |
clk_i => s_clk_i, |
rst_i => s_rst_i, |
spi_ssel_i => s_spi_ssel_i, |
spi_sck_i => s_spi_sck_i, |
spi_mosi_i => s_spi_mosi_i, |
spi_miso_o => s_spi_miso_o, |
di_i => s_di_i, |
do_o => s_do_o, |
di_rdy_o => s_di_rdy_o, |
wren_i => s_wren_i, |
do_valid_o => s_do_valid_o |
-- state_dbg_o => s_state_dbg_o, |
-- sh_reg_dbg_o => s_sh_reg_dbg_o |
); |
|
end Behavioral; |
|
|
|
/trunk/rtl/spi_slave.vhd
0,0 → 1,313
---------------------------------------------------------------------------------- |
-- Author: Jonny Doin, jdoin@opencores.org |
-- |
-- Create Date: 15:36:20 05/15/2011 |
-- Module Name: SPI_SLAVE - RTL |
-- Project Name: SPI INTERFACE |
-- Target Devices: Spartan-6 |
-- Tool versions: ISE 13.1 |
-- Description: |
-- |
-- This block is the SPI slave interface, implemented in one single entity. |
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard. |
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'. |
-- To avoid async glitches caused by setup violations between the core registers and the parallel i/o registers, |
-- access to the parallel ports 'di_i' and 'do_o' must be synchronized with the 'di_rdi_o' and 'do_valid_o' signals. |
-- |
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o. |
-- It is parameterizable for the data width ('N'), SPI mode via generics (CPHA and CPOL), and lookahead prefetch |
-- signaling ('PREFETCH'). |
-- |
-- PARALLEL WRITE INTERFACE |
-- The parallel interface has a input port 'di_i' and an output port 'do_o'. |
-- Parallel load is controlled using 3 signals: 'di_i', 'di_rdy_o' and 'wren_i'. 'di_rdy_o' is a look ahead data request line, |
-- that is set 'PREFETCH' 'spi_sck_i' cycles in advance to synchronize a pipelined memory or fifo to present the |
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load. |
-- The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid |
-- race conditions at the register transfer. |
-- For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one |
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer. |
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time. |
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle, |
-- if continuous transmission is intended. |
-- When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'. |
-- |
-- PARALLEL WRITE PIPELINED SEQUENCE |
-- ================================= |
-- __ __ __ __ __ __ __ __ __ __ __ |
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__... -- parallel interface clock |
-- ___________________________________ |
-- di_rdy_o ________/ \________________... -- 'di_rdy_o' asserted on rising edge of 'clk_par_i' |
-- ______________ ______________________________________________... |
-- di_i __old_data____X__________new_data____________________________... -- user circuit loads data on 'di_i' at next rising edge |
-- ________________________________ -- user circuit asserts 'wren_i' at next edge, and removes |
-- wren_i __________________/ \_______... -- 'wren_i' after 'di_rdy_o' is removed |
-- |
-- |
-- PARALLEL READ INTERFACE |
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received, |
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'. |
-- The signal 'do_valid_o' is set one 'spi_sck_i' clock after, to directly drive a synchronous memory or fifo write enable. |
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'. |
-- When the interface is idle, data at the 'do_o' port holds the last word received. |
-- |
-- PARALLEL READ PIPELINED SEQUENCE |
-- ================================ |
-- ______ ______ ______ ______ ______ ______ |
-- clk_spi_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\______/bitN-3\______/bitN-4\_____... -- spi base clock |
-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ |
-- clk_par_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__... -- parallel interface clock |
-- _________________ ____________________________________________________________________... -- 1) received data is transferred to 'do_buffer_reg' |
-- do_o __old_data_______X__________new_data__________________________________________________... -- after last bit received, at 'clk_spi_i' rising edge. |
-- _________________ -- 2) 'do_valid_o' asserted on rising edge of 'clk_par_i', |
-- do_valid_o ________________________________/ \___________________________________... -- at next bit (bit N-1) of the SPI transfer. |
-- _________________ |
-- RAM_we ______________________________________/ \_____________________________... -- 3) Generates a write enable, or uses 'do_valid_o' as 'we'. |
-- |
-- |
-- This module takes 85 FFs (47 slices in a Spartan-6 fabric), synthesized with XST and normal constraints. |
-- The design is tested in a Spartan-6 XC6SLX45t-2CSG324 device, in the Atlys board. |
-- |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
-- disclaimer. |
-- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser |
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
-- 2011/05/15 v0.10.0050 [JD] created the slave logic, with 2 clock domains, from SPI_MASTER module. |
-- 2011/05/15 v0.15.0055 [JD] fixed logic for starting state when CPHA='1'. |
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries. |
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
-- ==== |
-- |
-- - DEBUG_PACKAGE: |
-- - package to export signals to the verification testbench |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
--library WORK; |
--use WORK.DEBUG_PKG.ALL; |
|
entity spi_slave is |
Generic ( N : positive := 32; -- 32bit serial word length is default |
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) |
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase. |
PREFETCH : positive := 1); -- prefetch lookahead cycles |
Port ( clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers) |
rst_i : in std_logic := 'X'; -- synchronous rst_i: clear registers at clk_i rising edge |
spi_ssel_i : in std_logic; -- spi bus slave select line |
spi_sck_i : in std_logic; -- spi bus sck clock (clocks the shift register core) |
spi_mosi_i : in std_logic; -- spi bus mosi input |
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) |
di_rdy_o : out std_logic; -- preload lookahead: HIGH when ready for new input data |
wren_i : in std_logic := 'X'; -- write enable (write di_i data at next rising clk_i edge) |
-- wren_i starts transmission. must be valid 1 clk_i cycle before current transmission ends. |
do_valid_o : out std_logic -- do_o data valid signal, valid during one clk_i rising edge. |
-- state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
-- sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
); |
end spi_slave; |
|
--================================================================================================================ |
-- this architecture is a pipelined register-transfer description. |
-- the spi bus and core registers are synchronous to the 'spi_sck_i' clock. |
-- the parallel write/read interface is synchronous to the 'clk_i' clock. |
--================================================================================================================ |
architecture RTL of spi_slave is |
-- constants to control FlipFlop synthesis |
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA); |
constant SHIFT_EDGE : std_logic := (CPOL xor CPHA); |
-- internal state signals for register and combinational stages |
signal state_reg : natural range N+1 downto 0 := 0; |
signal state_next : natural range N+1 downto 0 := 0; |
-- shifter signals for register and combinational stages |
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- input bit sampled buffer |
signal rx_bit_reg : std_logic := '0'; |
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- buffered do_o data signals for register and combinational stages |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal signal to flag transfer to do_buffer_reg |
signal do_transfer_reg : std_logic := '0'; |
signal do_transfer_next : std_logic := '0'; |
-- internal registered do_valid_o |
signal do_valid_reg : std_logic := '0'; |
signal do_valid_next : std_logic := '0'; |
-- internal registered di_rdy_o |
signal di_ready_reg : std_logic := '0'; |
signal di_ready_next : std_logic := '0'; |
begin |
--============================================================================================= |
-- GENERICS CONSTRAINTS CHECKING |
--============================================================================================= |
-- minimum word width is 8 bits |
assert N >= 8 |
report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum" |
severity FAILURE; |
-- maximum prefetch lookahead check |
assert PREFETCH <= N-5 |
report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum" |
severity FAILURE; |
|
--============================================================================================= |
-- RTL REGISTER PROCESSES |
--============================================================================================= |
-- capture rx bit at SAMPLE edge of sck |
rx_bit_proc : process (spi_sck_i, spi_mosi_i) is |
begin |
if spi_sck_i'event and spi_sck_i = SAMPLE_EDGE then |
rx_bit_reg <= spi_mosi_i; |
end if; |
end process rx_bit_proc; |
-- state and data registers change on SHIFT edge of sck (ffd with async clear) |
core_reg_proc : process (spi_sck_i, rst_i, spi_ssel_i) is |
begin |
if rst_i = '1' then -- async rst for the parallel interface registers |
do_buffer_reg <= (others => '0'); |
do_transfer_reg <= '0'; |
elsif spi_ssel_i = '1' then -- async clear for core registers |
state_reg <= 0; |
sh_reg <= (others => '0'); |
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers |
state_reg <= state_next; |
sh_reg <= sh_next; |
do_buffer_reg <= do_buffer_next; |
do_transfer_reg <= do_transfer_next; |
end if; |
end process core_reg_proc; |
-- parallel load input registers (to elliminate async clock glitches) |
par_reg_proc: process (clk_i, rst_i, wren_i) is |
begin |
if rst_i = '1' then -- synchronous reset for the parallel interface |
di_reg <= (others => '0'); |
di_ready_reg <= '0'; |
do_valid_reg <= '0'; |
elsif clk_i'event and clk_i = '1' then |
di_ready_reg <= di_ready_next; |
do_valid_reg <= do_valid_next; |
if wren_i = '1' then -- wren_i is the clock enable for di_reg |
di_reg <= di_i; -- buffer for parallel data, to avoid 'clk_i' and 'spi_sck_i' async glitches |
end if; |
end if; |
end process par_reg_proc; |
|
--============================================================================================= |
-- RTL COMBINATIONAL LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinational logic |
core_combi_proc : process ( rst_i, sh_reg, state_reg, rx_bit_reg, do_buffer_reg, |
do_valid_reg, do_transfer_reg, di_reg, di_ready_reg, wren_i ) is |
begin |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
do_buffer_next <= do_buffer_reg; |
do_valid_next <= do_valid_reg; |
do_transfer_next <= do_transfer_reg; |
di_ready_next <= di_ready_reg; |
spi_miso_o <= '0'; -- will output '0' when shifter is empty |
state_next <= state_reg - 1; -- update next state at each sck pulse |
case state_reg is |
when (N) => |
di_ready_next <= '0'; -- deassert next-data request when start shifting |
spi_miso_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (N-1) downto (PREFETCH+3) => |
di_ready_next <= '0'; -- deassert next-data request when start shifting |
do_valid_next <= do_transfer_reg; -- assert valid rx data, with plenty of pipeline delay for 'do_buffer' |
do_transfer_next <= '0'; -- reset transfer signal |
spi_miso_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (PREFETCH+2) downto 2 => |
-- raise prefetch 'di_ready_next' signal and remove 'do_valid' |
di_ready_next <= '1'; -- request data in advance to allow for pipeline delays |
do_valid_next <= '0'; -- make do_valid_o HIGH for one cycle only |
spi_miso_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when 1 => |
-- restart from state 'N' if more sck pulses come |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer |
do_transfer_next <= '1'; -- signal transfer to do_buffer |
state_next <= N; -- next state is top bit of new data |
spi_miso_o <= sh_reg(N-1); -- shift out last tx bit from the MSb |
if wren_i = '1' then -- load tx register if valid data present at di_reg |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
else |
sh_next <= (others => '0'); -- load null data (output '0' if no load) |
end if; |
when 0 => |
do_transfer_next <= '0'; -- clear signal transfer to do_buffer |
do_valid_next <= do_transfer_reg; -- assert valid rx data after data received, when interface idle |
di_ready_next <= '1'; -- will request data if shifter empty |
spi_miso_o <= di_reg(N-1); -- shift out first tx bit from the MSb |
if CPHA = '0' then |
-- initial state for CPHA=0, when slave interface is first selected or idle |
state_next <= N-1; -- next state is top bit of new data |
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
else |
-- initial state for CPHA=1, when slave interface is first selected or idle |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
end if; |
when others => |
null; |
end case; |
end process core_combi_proc; |
|
--============================================================================================= |
-- RTL OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- data output processes |
do_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_proc: do_valid_o <= do_valid_reg; -- copy registered do_valid_o to output |
di_ready_proc: di_rdy_o <= di_ready_reg; -- copy registered di_rdy_o to output |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
--============================================================================================= |
-- The debug signals are declared in package debug_pkg |
-- These processes can be removed from the entity after verification |
-- sh_reg_dbg_proc: dbg_shift_s <= conv_integer(sh_reg); -- export sh_reg to debug |
-- state_dbg_proc: dbg_state_s <= state_reg; -- export internal state to debug |
|
-- sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
-- state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
end architecture RTL; |
|
/trunk/rtl/spi_master.vhd
0,0 → 1,416
----------------------------------------------------------------------------------------------------------------------- |
-- Author: Jonny Doin, jdoin@opencores.org |
-- |
-- Create Date: 12:18:12 04/25/2011 |
-- Module Name: SPI_MASTER - RTL |
-- Project Name: SPI MASTER / SLAVE INTERFACE |
-- Target Devices: Spartan-6 |
-- Tool versions: ISE 13.1 |
-- Description: |
-- |
-- This block is the SPI master interface, implemented in one single entity. |
-- All internal core operations are synchronous to a spi base clock, that generates the spi sck clock directly. |
-- All parallel i/o interface operations are synchronous to a system clock, that can be asynchronous to the spi base clock. |
-- Fully pipelined circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two clock domains. |
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o. |
-- It is parameterizable for the data width ('N'), SPI mode via generics (CPHA and CPOL), and lookahead prefetch |
-- signaling ('PREFETCH'). |
-- |
-- PARALLEL WRITE INTERFACE |
-- The parallel interface has a input port 'di_i' and an output port 'do_o'. |
-- Parallel load is controlled using 3 signals: 'di_i', 'di_rdy_o' and 'wren_i'. 'di_rdy_o' is a look ahead data request line, |
-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the |
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load. |
-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one |
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter. |
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time. |
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle, |
-- if continuous transmission is intended. If 'wren_i' is not valid 2 clock cycles after the last tranmitted bit, the interface |
-- enters idle state and deasserts SSEL. |
-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_rdy_o' is always asserted when idle. |
-- The interaction for data load is: |
-- |
-- PARALLEL WRITE PIPELINED SEQUENCE |
-- ================================= |
-- __ __ __ __ __ __ __ __ __ |
-- par_clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__... -- parallel interface clock |
-- ___________________________________ |
-- di_rdy_o ________/ \___________... -- 'di_rdy_o' asserted on rising edge of 'par_clk_i' |
-- ______________ _________________________________________ |
-- di_i __old_data____X__________new_data_______________________... -- user circuit loads data on 'di_i' at next rising edge |
-- ________________________________ -- user circuit asserts 'wren_i' at next edge, and removes |
-- wren_i __________________/ \____... -- 'wren_i' after 'di_rdy_o' is removed |
-- |
-- |
-- PARALLEL READ INTERFACE |
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received, |
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_2x_clk_i'. |
-- The signal 'do_valid_o' is set one 'spi_2x_clk_i' clock after, to directly drive a synchronous memory or fifo write enable. |
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'par_clk_i'. |
-- When the interface is idle, data at the 'do_o' port holds the last word received. |
-- |
-- PARALLEL READ PIPELINED SEQUENCE |
-- ================================ |
-- ______ ______ ______ ______ ______ |
-- spi_2x_clk_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\______/bitN-3\_... -- spi base clock |
-- __ __ __ __ __ __ __ __ __ __ __ |
-- par_clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__... -- parallel interface clock |
-- ________________ ___________________________________________________... -- 1) received data is transferred to 'do_buffer_reg' |
-- do_o __old_data______X__________new_data_________________________________... -- after last bit received, at 'spi_2x_clk_i' rising edge. |
-- _________________ -- 2) 'do_valid_o' asserted on rising edge of 'par_clk_i', |
-- do_valid_o ________________________________/ \_________________... -- at next bit (bit N-1) of the SPI transfer. |
-- _________________ |
-- RAM_we ______________________________________/ \___________... -- 3) User can use 'do_valid_o' as write enable of sync RAM. |
-- |
-- |
-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays, |
-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency |
-- of the interface, for full duplex operation. |
-- The synthesizable architecture is fully static, with a classic RTL pipelined architecture, and follows the KISS |
-- methodology (Keep It Synchronous, Stupid!). |
-- |
-- This module takes 76 FFs (25 slices on a Spartan-6 fabric), synthesized with XST and normal constraints. |
-- The design is tested in a Spartan-6 XC6SLX45t-2CSG324 device, in the Atlys board. |
-- |
------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- |
-- |
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave |
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org |
-- |
-- Copyright (C) 2011 Authors and OPENCORES.ORG |
-- -------------------------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
-- disclaimer. |
-- |
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser |
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or |
-- (at your option) any later version. |
-- |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis. |
-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues. |
-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store. |
-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA |
-- logic, based on generics, and do_valid_o signal. |
-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions. |
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries. |
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core. |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
-- TODO |
-- ==== |
-- |
-- - DEBUG_PACKAGE: |
-- - package to export signals to the verification testbench |
-- |
-- |
----------------------------------------------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
--library WORK; |
--use WORK.DEBUG_PKG.ALL; |
|
entity spi_master is |
Generic ( N : positive := 32; -- 32bit serial word length is default |
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) |
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase. |
PREFETCH : positive := 1); -- prefetch lookahead cycles |
Port ( spi_2x_clk_i : in std_logic := 'X'; -- spi base reference clock: 2x 'spi_sck_o' |
par_clk_i : in std_logic := 'X'; -- parallel interface clock |
rst_i : in std_logic := 'X'; -- async reset: clear all registers |
spi_ssel_o : out std_logic; -- spi bus slave select line |
spi_sck_o : out std_logic; -- spi bus sck |
spi_mosi_o : out std_logic; -- spi bus mosi output |
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input |
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising spi_2x_clk_i after last bit) |
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on rising spi_2x_clk_i after last bit) |
di_rdy_o : out std_logic; -- preload lookahead: HIGH for PREFETCH cycles before last bit |
wren_i : in std_logic := 'X'; -- write enable (write di_i data at next rising spi_2x_clk_i edge) |
-- wren_i starts transmission. must be valid 1 spi_2x_clk_i cycle before current transmission ends. |
do_valid_o : out std_logic -- do_o data valid signal, valid during one spi_2x_clk_i rising edge. |
-- state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register |
-- sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register |
); |
end spi_master; |
|
--================================================================================================================ |
-- this architecture is a pipelined register-transfer description. |
-- all signals are clocked at the rising edge of the system clock 'spi_2x_clk_i'. |
--================================================================================================================ |
architecture RTL of spi_master is |
-- core clocks, generated from 'spi_2x_clk_i' |
signal core_clk : std_logic; -- continuous fsm core clock, positive logic |
signal core_n_clk : std_logic; -- continuous fsm core clock, negative logic |
-- spi base clock, generated from 'spi_2x_clk_i' |
signal spi_clk : std_logic; -- spi bus output clock, positive polarity |
signal spi_n_clk : std_logic; -- spi bus output clock, negative polarity |
-- core fsm clock |
signal fsm_clk : std_logic; -- data change clock: fsm registers clocked at rising edge |
signal samp_clk : std_logic; -- data sampling clock: input serial data clocked at rising edge |
-- internal state signals for register and combinational stages |
signal state_reg : natural range N+1 downto 0 := 0; |
signal state_next : natural range N+1 downto 0 := 0; |
-- shifter signals for register and combinational stages |
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- input bit sampled buffer |
signal rx_bit_reg : std_logic := '0'; |
-- buffered di_i data signals for register and combinational stages |
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal SSEL enable control signals |
signal ena_ssel_reg : std_logic := '0'; |
signal ena_ssel_next : std_logic := '0'; |
-- internal SCK enable control signals |
signal ena_sck_reg : std_logic := '0'; |
signal ena_sck_next : std_logic := '0'; |
-- buffered do_o data signals for register and combinational stages |
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- internal signal to flag transfer to do_buffer_reg |
signal do_transfer_reg : std_logic := '0'; |
signal do_transfer_next : std_logic := '0'; |
-- internal registered do_valid_o |
signal do_valid_reg : std_logic := '0'; |
signal do_valid_next : std_logic := '0'; |
-- internal registered di_rdy_o |
signal di_ready_reg : std_logic := '0'; |
signal di_ready_next : std_logic := '0'; |
begin |
--============================================================================================= |
-- GENERICS CONSTRAINTS CHECKING |
--============================================================================================= |
-- minimum word width is 8 bits |
assert N >= 8 |
report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum" |
severity FAILURE; |
-- maximum prefetch lookahead check |
assert PREFETCH <= N-5 |
report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum" |
severity FAILURE; |
|
--============================================================================================= |
-- CLOCK GENERATION |
--============================================================================================= |
-- The clock generation block derive 2 sets of signals from the 2x spi base clock, with positive |
-- and negative phase. The core clock runs continuously and drives the core fsm, and the spi clock |
-- drives the spi bus 'spi_sck_o' output directly, and is controlled by 'ena_sck_reg', driven by the |
-- fsm logic. |
-- The 2 clocks are generated each with one FFD, with a selected phase to drive the core with rising |
-- edge clocks only. The 2 sets of clocks have similar logic delays, which is important for the data |
-- setup time of the serial input related to the data setup time of the serial output. |
----------------------------------------------------------------------------------------------- |
-- divide down 'spi_2x_clk_i' by 2 |
-- this should be synthesized as a single ffd |
core_clock_gen_proc : process (rst_i, spi_2x_clk_i) is |
begin |
if rst_i = '1' then |
core_clk <= '0'; -- positive logic clk: idle LOW |
core_n_clk <= '1'; -- negative logic clk: idle HIGH |
elsif spi_2x_clk_i'event and spi_2x_clk_i = '1' then |
core_clk <= core_n_clk; -- divided by 2 clock, differential |
core_n_clk <= not core_n_clk; |
end if; |
end process core_clock_gen_proc; |
----------------------------------------------------------------------------------------------- |
-- spi sck generator: divide input 2x clock by 2, with a CE controlled by the fsm |
-- this should be sinthesized as a single FFD with async reset and clock enable |
spi_clock_gen_proc : process (rst_i, spi_2x_clk_i, ena_sck_reg) is |
begin |
if rst_i = '1' then |
spi_clk <= '0'; -- positive logic clk: idle LOW |
spi_n_clk <= '1'; -- negative logic clk: idle HIGH |
elsif spi_2x_clk_i'event and spi_2x_clk_i = '1' then |
if ena_sck_reg = '1' then |
spi_clk <= spi_n_clk; -- divided by 2 clock, differential |
spi_n_clk <= not spi_n_clk; |
end if; |
end if; |
end process spi_clock_gen_proc; |
----------------------------------------------------------------------------------------------- |
-- SCK out logic: generate sck from spi_clk or spi_n_clk depending on CPOL |
spi_sck_cpol_0_proc : |
if CPOL = '0' generate |
begin |
spi_sck_o <= spi_clk; -- for CPOL=0, spi clk has idle LOW |
end generate; |
spi_sck_cpol_1_proc : |
if CPOL = '1' generate |
begin |
spi_sck_o <= spi_n_clk; -- for CPOL=1, spi clk has idle HIGH |
end generate; |
----------------------------------------------------------------------------------------------- |
-- Sampling clock generation: generate 'samp_clk' from core_clk or core_n_clk depending on CPHA |
smp_cpha_0_proc : |
if CPHA = '0' generate |
begin |
samp_clk <= core_clk; -- for CPHA=0, sample at rising edge of positive core clock |
end generate; |
smp_cpha_1_proc : |
if CPHA = '1' generate |
begin |
samp_clk <= core_n_clk; -- for CPHA=1, sample at rising edge of negative core clock |
end generate; |
----------------------------------------------------------------------------------------------- |
-- FSM clock generation: generate 'fsm_clock' from core_clk or core_n_clk depending on CPHA |
fsm_cpha_0_proc : |
if CPHA = '0' generate |
begin |
fsm_clk <= core_n_clk; -- for CPHA=0, latch registers at rising edge of negative core clock |
end generate; |
fsm_cpha_1_proc : |
if CPHA = '1' generate |
begin |
fsm_clk <= core_clk; -- for CPHA=1, latch registers at rising edge of positive core clock |
end generate; |
|
--============================================================================================= |
-- RTL REGISTER PROCESSES |
--============================================================================================= |
-- capture rx bit at SAMPLE edge of sck |
rx_bit_proc : process (samp_clk, spi_miso_i) is |
begin |
if samp_clk'event and samp_clk = '1' then |
rx_bit_reg <= spi_miso_i; |
end if; |
end process rx_bit_proc; |
-- state and data registers synchronous to the spi base reference clock |
core_reg_proc : process (fsm_clk, rst_i) is |
begin |
if rst_i = '1' then -- asynchronous reset |
sh_reg <= (others => '0'); |
state_reg <= 0; |
ena_ssel_reg <= '0'; |
ena_sck_reg <= '0'; |
do_buffer_reg <= (others => '0'); |
do_transfer_reg <= '0'; |
elsif fsm_clk'event and fsm_clk = '1' then |
sh_reg <= sh_next; |
state_reg <= state_next; |
ena_ssel_reg <= ena_ssel_next; |
ena_sck_reg <= ena_sck_next; |
do_buffer_reg <= do_buffer_next; |
do_transfer_reg <= do_transfer_next; |
end if; |
end process core_reg_proc; |
-- parallel i/o interface registers, synchronous to the parallel interface clock |
par_reg_proc : process (par_clk_i, rst_i) is |
begin |
if rst_i = '1' then -- asynchronous reset |
di_ready_reg <= '0'; |
do_valid_reg <= '0'; |
di_reg <= (others => '0'); |
elsif par_clk_i'event and par_clk_i = '1' then |
di_ready_reg <= di_ready_next; -- di_rdy is synchronous to parallel interface clock |
do_valid_reg <= do_valid_next; |
di_reg <= di_i; -- sample di_i at interface clock |
end if; |
end process par_reg_proc; |
|
--============================================================================================= |
-- RTL COMBINATIONAL LOGIC PROCESSES |
--============================================================================================= |
-- state and datapath combinational logic |
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ena_ssel_reg, ena_sck_reg, do_buffer_reg, |
do_valid_reg, do_transfer_reg, di_reg, di_ready_reg, wren_i ) is |
begin |
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches) |
ena_ssel_next <= ena_ssel_reg; |
ena_sck_next <= ena_sck_reg; |
do_buffer_next <= do_buffer_reg; |
do_valid_next <= do_valid_reg; |
do_transfer_next <= do_transfer_reg; |
di_ready_next <= di_ready_reg; |
spi_mosi_o <= '0'; -- will output '0' when shifter is empty |
state_next <= state_reg - 1; -- next state is next bit |
case state_reg is |
when (N+1) => -- this state is to enable SSEL before SCK |
ena_ssel_next <= '1'; -- tx in progress: will assert SSEL |
ena_sck_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle) |
di_ready_next <= '0'; -- deassert next-data request when shifting data |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
when (N) => |
di_ready_next <= '0'; -- deassert next-data request when shifting data |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (N-1) downto (PREFETCH+3) => |
di_ready_next <= '0'; -- deassert next-data request when start shifting |
do_valid_next <= do_transfer_reg; -- assert valid rx data, with plenty of pipeline delay for 'do_buffer' |
do_transfer_next <= '0'; -- reset transfer signal |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when (PREFETCH+2) downto 2 => |
-- raise prefetch 'di_ready_next' signal and remove 'do_valid' |
di_ready_next <= '1'; -- request data in advance to allow for pipeline delays |
do_valid_next <= '0'; -- make do_valid_o HIGH for one cycle only |
spi_mosi_o <= sh_reg(N-1); -- shift out tx bit from the MSb |
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits |
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb |
when 1 => |
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer |
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer |
do_transfer_next <= '1'; -- signal transfer to do_buffer |
spi_mosi_o <= sh_reg(N-1); -- shift out last tx bit from the MSb |
if wren_i = '1' then -- load tx register if valid data present at di_i |
state_next <= N; -- next state is top bit of new data |
sh_next <= di_reg; -- load parallel data from di_reg into shifter |
ena_sck_next <= '1'; -- SCK enabled |
else |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
end if; |
when 0 => |
ena_sck_next <= '0'; -- SCK disabled: tx empty, no data to send |
di_ready_next <= '1'; -- will request data if shifter empty |
do_valid_next <= do_transfer_reg; -- assert valid rx data after data received, when interface idle |
if wren_i = '1' then -- load tx register if valid data present at di_i |
ena_ssel_next <= '1'; -- enable interface SSEL |
state_next <= N+1; -- start from idle: let one cycle for SSEL settling |
do_valid_next <= '0'; -- start: clear rx data valid signal |
spi_mosi_o <= di_reg(N-1); -- shift out first tx bit from the MSb |
sh_next <= di_reg; -- load bits from di_reg into shifter |
else |
ena_ssel_next <= '0'; -- deassert SSEL: interface is idle |
state_next <= 0; -- when idle, keep this state |
end if; |
when others => |
null; |
end case; |
end process core_combi_proc; |
|
--============================================================================================= |
-- OUTPUT LOGIC PROCESSES |
--============================================================================================= |
-- output signal connections |
spi_ssel_proc: spi_ssel_o <= not ena_ssel_reg; -- drive active-low slave select line |
do_proc : do_o <= do_buffer_reg; -- do_o always available |
do_valid_proc: do_valid_o <= do_valid_reg; -- copy registered do_valid_o to output |
di_ready_proc: di_rdy_o <= di_ready_reg; -- copy registered di_rdy_o to output |
|
--============================================================================================= |
-- DEBUG LOGIC PROCESSES |
--============================================================================================= |
-- The debug signals are declared in package debug_pkg |
-- These processes can be removed from the entity after verification |
-- sh_reg_dbg_proc: dbg_shift_m <= conv_integer(sh_reg); -- export sh_reg to debug |
-- state_dbg_proc: dbg_state_m <= state_reg; -- export internal state to debug |
|
-- sh_reg_dbg_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug |
-- state_dbg_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug |
end architecture RTL; |
|
/trunk/rtl/readme.txt
0,0 → 1,18
SPI_MASTER_SLAVE |
---------------- |
|
VHDL files for spi master/slave project: |
|
spi_master.vhd spi master module, can be used independently |
spi_slave.vhd spi slave module, can be used independently |
spi_loopback.vhd wrapper module for the master and slave modules |
spi_loopback_test.vhd testbench for the loopback module, test master against slave |
|
|
The original development is done in Xilinx ISE 13.1, targeted to a Spartan-6 device. |
|
Verification was done in ISIM, after Place & Route, with default constraints, for the slowest |
Spartan-6 device, tested at 50MHz for the spi_2x_clk (25MHz spi SCK), and 125MHz for the parallel |
interfaces clocks. |
|
|
/trunk/doc/src/SPI_MODES.jpg
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/doc/src/SPI_MODES.jpg
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/src/spi_master_slave_Specifications.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/src/spi_master_slave_Specifications.doc
===================================================================
--- trunk/doc/src/spi_master_slave_Specifications.doc (nonexistent)
+++ trunk/doc/src/spi_master_slave_Specifications.doc (revision 2)
trunk/doc/src/spi_master_slave_Specifications.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/src/spi_slave_block.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/src/spi_slave_block.pdf
===================================================================
--- trunk/doc/src/spi_slave_block.pdf (nonexistent)
+++ trunk/doc/src/spi_slave_block.pdf (revision 2)
trunk/doc/src/spi_slave_block.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/src/spi_master_block.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/src/spi_master_block.pdf
===================================================================
--- trunk/doc/src/spi_master_block.pdf (nonexistent)
+++ trunk/doc/src/spi_master_block.pdf (revision 2)
trunk/doc/src/spi_master_block.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/src/spi_slave_block.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/src/spi_slave_block.bmp
===================================================================
--- trunk/doc/src/spi_slave_block.bmp (nonexistent)
+++ trunk/doc/src/spi_slave_block.bmp (revision 2)
trunk/doc/src/spi_slave_block.bmp
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/src/spi_master_block.bmp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/src/spi_master_block.bmp
===================================================================
--- trunk/doc/src/spi_master_block.bmp (nonexistent)
+++ trunk/doc/src/spi_master_block.bmp (revision 2)
trunk/doc/src/spi_master_block.bmp
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/spi_master_slave_Specifications.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/doc/spi_master_slave_Specifications.pdf
===================================================================
--- trunk/doc/spi_master_slave_Specifications.pdf (nonexistent)
+++ trunk/doc/spi_master_slave_Specifications.pdf (revision 2)
trunk/doc/spi_master_slave_Specifications.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/spi_master_slave_test_25MHz.pdf
===================================================================
--- trunk/doc/spi_master_slave_test_25MHz.pdf (nonexistent)
+++ trunk/doc/spi_master_slave_test_25MHz.pdf (revision 2)
@@ -0,0 +1,9805 @@
+%PDF-1.4
+%쏢
+5 0 obj
+<>
+stream
+x͝AqFa; ER6H"ʈoYGWd{30[DU>>{>Wχ?}Xqۺ}$>G玬#~=İm!_Y#/)>>}]cN>P#)m6
+Q?l19|}USjyGFZuHt#
+£ϾקFzۭ:rRMoo!HZxkX73u#f92p߅?2~8\>w8rsf ގKudō#(GqE}d϶,]^QѲ#la=UGgniĶ?u}?KoHP#.B#ϡO@H}pEEú>#rdX.8䶫gNC`Odm<>@xWETUnUq:8oy(rs05R<`OѴjCPQֆc6wM&*oؠ'Zxa*vJH]֊b*`w]Z
+AG[sy*lT7M՟hQIX#%Qkh^xX6*B+~bņ#x~Vq'xd)XXUq:>&B-hv88uCNXLhWc^=DS<7xQ\Q,.78بX[qw<;HXv*?ۺ_xXmkQ94ۿyEQ9eOqG@1R*9bdA䴰~n%ޚLT,Tw/ZTȰ# MHx\8bOiѾPtqȰPuS%ވCTTTȰÉg9bW"Sl4h_|(?_mHDMdbE֧{Ѣ(^;9ʼn[XuiŁN
+NLϋvZjSQQ"2Rs(wޯ)ʼng9 Xmn8VL(NTݜeZ`@DMdY9̰L(NT8̡L(@1S*U7TԽJhgexh2Q33)}F-̡L8P̍`OElE^=i_13=3=3=UhfXT'nEP&\QuSx} "Ul,2A珢_miQTMwTTScw⎏(wM؊z;ӊؙEZꏠ_()lT SMohQ/ȰR*'nEPNU7U7ҡiaU7Eska:6uAJDՍi1ATT+H(M-ꏺa(U7EO5ۿyEURq8Qu,"rZ\ n*tRpQ!({~dXF'n&Tw/Z+2,'!p[SmEţ}Rq)U7E QfPAN()LTTw/ZTȰÉզڊG6f~DJEXh_|(:͈@qY#nCq5"pYD崈"n*'T{EGk6#2,#U7EO5ۿyEQaYR*'nEPքCTT(DyNX^*?qbexhQO5ۿyEQaL(NT8̡d&\ S9/ʴ#nL3w;̭Ík33,)Mg˱̄C6s3icJEXLh_|(:͍mh2Q11q1pN6EDưvf/c}Tgrsl?g@DMdY9ETT;3,;S*U7"s(;.8P̔DyAX^*?@DMdbgggE1qL
+ΔDՍ΄"n*L;-ŇXm̰U7EY9;RDՍC6V}T'n2-by6~̰OTM6*9Cq~~M8}Ég9QuSq)U7ҡPd7≪;!/!n*bdX"+ CI\XH(_h_|(?=$.Ȱ/U7qAMx#r(QuSQ#>DՍJdsaWǗE2EGѯ6# [
+v8Z;qG;Soq&lE=ڝiluv7:)83=/#*A>&+_#-j݄݄D;Gvv8Qu,2QuS/M+-by){ OTM&*8_↪݄#;qCasa8P̔DyNX^*?1 OTM6*a`ǴQM8}Ég96h߃T(fJEq(Ӣ}PlvfX'n⎪* j7ޯg7'V"cl.ͽǴǗDx!l6MxM8ޚLTqd`;UٙEnnE3muvRQٙܙ(q({) OTM6*a`;ǴQM8}Ég9QuSqpEt((qb7f0;LFn3pb`U7"r(ͅb_1+_wZ/>EL& ?~Mxx&?Pu8_Ǎn=Wb&$\<DE3i/E珠_mfv(w&p/!n*bdXÉg9 U7MGJD)AQ!({=Hf7≪F>FBf7'nEP2;DMŁblNT䀪u((qؙOLs4L ͻ-bdX2;qCl.U7>XӢ}(ff7~7xk2QǙ=_K1N6EF*{jA''rETTMxxhQOf`xJpf`U7"r(ͅ@1R*'nN-by({>Mxxh2QǙꦢ*F%}b=~ͅ#n*#|izТ}(8Mv(w&p/!nrߌ&>DՍJfsa8PI"2EG^ܐls=;^벗z}ygx˷֏!_W.W}ӫ]u$W_֕x_>r-^h+\B9|mU[gH]KX8}%iז*϶(|y8_,>l`?Ѽ=| t//rG?GWQwFuo˫GķvD~k1I=bϗ
+kTOZ`HܜƯA6ڰJԆQ?xjZOF:0Bju^RȘKq~\
+̥|z&s)KaϢpQ>$jv}ԨGu]d)Z~ӯQ̥5\Zk:/si]1U1(si}.%_&Kk\Z<q~CyDmQdy^g7z]z`.y<
+T̥8\zjA\*+~W-ڂSgj=|\*Kys Kq(sCR<0
+Q- #jj
+eQ-?sTר^W\W̥8\*Kq>[O2^Z1
+'@$jӎMDm:QCK~Qg7zCR~`.̥๔Ky\ʋ̥?ռ\+R^ # 9J愨ͩFsߟ÷Z?_8ϗ=ҹK>W?z;Տy+x:i9_ӾGo1Ɔ3ؾ.EO[|sZ6zsW̓\}S
+avVs|:ga)x|&~'}k@ۇk=}89ևkX8|އ!V.Yƃd߾|lWܷ}ټ>,>}c@$z߿~\\\9j^Os1pgk}}?S?al'놿O]Va.?Ͻjߨ\Oendstream
+endobj
+6 0 obj
+7144
+endobj
+4 0 obj
+<>
+/Contents 5 0 R
+>>
+endobj
+3 0 obj
+<< /Type /Pages /Kids [
+4 0 R
+] /Count 1
+/Rotate 90>>
+endobj
+1 0 obj
+<>
+endobj
+7 0 obj
+<>endobj
+12 0 obj
+<>
+endobj
+13 0 obj
+<>
+endobj
+11 0 obj
+<>stream
+ Adobe d C
+
+
+
+
+ C
+
+ a\
+ } !1AQa"q2#BR$3br
+%&'()*456789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz
+ w !1AQaq"2B #3Rbr
+$4%&'()*56789:CDEFGHIJSTUVWXYZcdefghijstuvwxyz ? o~~&д+OVt>TcɳsY;|I9f'%Y]7v?|.<]&m~ $ 0 Uω( _c L/Q *Z
+B#(tUл8ֹpM
+oO 9 8
+o"() <| | y F; $ſ?"* W ڎ S lO>.) b W1иDX W HO߂G~'|5sQon~ros$iF@k,fOWz撽;mdنC(sU|WKE$@|$ K ' z?O >?i G 8_^<-MBЭ>˥ZPy&d1$嘞Oz{ G5x1VWowMݞ7
+poWcN0oVݾ
+~@ۿJ|? cMu_ "_?Db " /;bgE_ -kЩ(&
XQf(6V&
?& [ +v8NU7o&vNlpYdͅb_1+_VZRPQ