URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/spi_master_slave
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/trunk/rtl/spi_master.vhd
305,7 → 305,7
-- the spi clock generator and the input sampling clock. |
-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock |
-- for the core clocking. |
-- The 2 clock phases are generated by sepparate and synchronous FFs, and should have only |
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only |
-- differential interconnect delay skew. |
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock |
-- enables are used to control clocking of all internal synchronous circuitry. |
/trunk/doc/paralel_handshake.pdf
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/trunk/doc/spi_master_slave_mode_0_v0.97.0083.pdf
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trunk/doc/spi_master_slave_mode_0_v0.97.0083.pdf
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Index: trunk/doc/spi_master_slave_mode_1_v0.97.0083.pdf
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Index: trunk/doc/spi_master_slave_mode_1_v0.97.0083.pdf
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--- trunk/doc/spi_master_slave_mode_1_v0.97.0083.pdf (revision 13)
+++ trunk/doc/spi_master_slave_mode_1_v0.97.0083.pdf (nonexistent)
trunk/doc/spi_master_slave_mode_1_v0.97.0083.pdf
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Index: trunk/doc/spi_master_slave_mode_2_v0.97.0083.pdf
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Index: trunk/doc/spi_master_slave_mode_2_v0.97.0083.pdf
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--- trunk/doc/spi_master_slave_mode_2_v0.97.0083.pdf (revision 13)
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trunk/doc/spi_master_slave_mode_2_v0.97.0083.pdf
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Index: trunk/doc/spi_master_slave_mode_3_v0.97.0083.pdf
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Index: trunk/doc/spi_master_slave_mode_3_v0.97.0083.pdf
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--- trunk/doc/spi_master_slave_mode_3_v0.97.0083.pdf (revision 13)
+++ trunk/doc/spi_master_slave_mode_3_v0.97.0083.pdf (nonexistent)
trunk/doc/spi_master_slave_mode_3_v0.97.0083.pdf
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Index: trunk/doc/src/spi_master_block.bmp
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Index: trunk/doc/src/spi_master_block.bmp
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--- trunk/doc/src/spi_master_block.bmp (revision 13)
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trunk/doc/src/spi_master_block.bmp
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Index: trunk/doc/src/spi_slave_block.bmp
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Index: trunk/doc/src/spi_slave_block.bmp
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--- trunk/doc/src/spi_slave_block.bmp (revision 13)
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trunk/doc/src/spi_slave_block.bmp
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Index: trunk/doc/src/spi_master_block.pdf
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Index: trunk/doc/src/spi_master_block.pdf
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--- trunk/doc/src/spi_master_block.pdf (revision 13)
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trunk/doc/src/spi_master_block.pdf
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Index: trunk/doc/src/spi_slave_block.pdf
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Index: trunk/doc/src/spi_slave_block.pdf
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--- trunk/doc/src/spi_slave_block.pdf (revision 13)
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trunk/doc/src/spi_slave_block.pdf
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Index: trunk/doc/src/spi_master_slave_Specifications.doc
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Index: trunk/doc/spi_master_slave_Specifications.pdf
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Index: trunk/syn/spi_master.vhd
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--- trunk/syn/spi_master.vhd (revision 13)
+++ trunk/syn/spi_master.vhd (revision 14)
@@ -305,7 +305,7 @@
-- the spi clock generator and the input sampling clock.
-- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock
-- for the core clocking.
- -- The 2 clock phases are generated by sepparate and synchronous FFs, and should have only
+ -- The 2 clock phases are generated by separate and synchronous FFs, and should have only
-- differential interconnect delay skew.
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
-- enables are used to control clocking of all internal synchronous circuitry.