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Rev 9 → Rev 10

/trunk/rtl/spi_loopback.vhd
19,22 → 19,12
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
 
entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
/trunk/rtl/spi_slave.vhd
12,6 → 12,8
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
-- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
--
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch
104,6 → 106,8
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/06/17 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--
--
-----------------------------------------------------------------------------------------------------------------------
122,7 → 126,7
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2); -- prefetch lookahead cycles
PREFETCH : positive := 3); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
139,16 → 143,21
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
wren_ack_o : out std_logic; -- debug: wren ack from state machine
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (5 downto 0) -- debug: internal state register
-- sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
 
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- the spi bus and core registers are synchronous to the 'spi_sck_i' clock.
-- the parallel write/read interface is synchronous to the 'clk_i' clock.
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
--================================================================================================================
 
architecture RTL of spi_slave is
-- constants to control FlipFlop synthesis
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA);
371,6 → 380,6
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
wren_ack_o_proc: wren_ack_o <= wren_ack_reg;
-- sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture RTL;
 
/trunk/rtl/spi_master.vhd
133,11 → 133,11
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
-- > verify the receive interface in silicon, and determine the top usable frequency.
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
146,6 → 146,8
use ieee.std_logic_unsigned.all;
 
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
193,7 → 195,7
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
architecture RTL of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
375,13 → 377,13
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
-- REDUCED DEMAND ON MISO SETUP TIME.
--
rx_bit_proc : process (sclk_i) is
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
-- if sclk_i'event and sclk_i = '1' then
-- if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
end if;
end if;
-- end if;
-- end if;
end process rx_bit_proc;
 
--=============================================================================================
562,5 → 564,5
core_ce_o_proc: core_ce_o <= core_ce;
core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
 
end architecture rtl;
end architecture RTL;
 
/trunk/rtl/readme.txt
34,7 → 34,8
 
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer.
 
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at http://opencores.org/project,spi_master_slave,bugtracker.
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
http://opencores.org/project,spi_master_slave,bugtracker.
 
 
In any case, thank you for testing and using this core.
43,6 → 44,3
Jonny Doin
jdoin@opencores.org
 
 
 
 
/trunk/syn/spi_master_atlys_top_bit.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/syn/spi_master_atlys_top.vhd
8,13 → 8,15
-- Target Devices: Spartan-6 LX45
-- Tool versions: ISE 13.1
-- Description:
-- This is a test project for the Atlys board, to test the spi_master and grp_debounce cores.
-- This is a verification project for the Digilent Atlys board, to test the SPI_MASTER, SPI_SLAVE and GRP_DEBOUNCE cores.
-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
--
-- See the "spi_master_atlys.ucf" file for pin assignments.
-- See the "spi_master_atlys.ucf" file for pin assignments.
-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
-- digital pod port.
-- The board switches are used to set the SPI_MASTER transmit data, and the SPI_SLAVE receive data drives the switch LEDs.
-- The pushbuttons drive the slave transmit data, and the master received data drives the parallel debug port.
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
32,7 → 34,7
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
 
entity spi_master_atlys_top is
Port (
42,6 → 44,7
spi_ssel_o : out std_logic; -- spi port SSEL
spi_sck_o : out std_logic; -- spi port SCK
spi_mosi_o : out std_logic; -- spi port MOSI
spi_miso_o : out std_logic; -- spi port MISO
--- input slide switches ---
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches
--- input buttons ---
49,8 → 52,11
--- output LEDs ----
led_o : out std_logic_vector (7 downto 0); -- output leds
--- debug outputs ---
dbg_o : out std_logic_vector (9 downto 0); -- 10 generic debug pins
dbg_o : out std_logic_vector (7 downto 0); -- 10 generic debug pins
--- spi debug pins ---
spi_rx_bit_m_o : out std_logic; -- master rx bit feedback
spi_rx_bit_s_o : out std_logic; -- slave rx bit feedback
spi_do_valid_o : out std_logic; -- spi data valid
spi_di_req_o : out std_logic; -- spi data request
spi_wren_o : out std_logic; -- spi write enable
spi_wren_ack_o : out std_logic -- spi write enable ack
64,9 → 70,9
--=============================================================================================
-- clock divider count values from gclk_i (100MHz board clock)
-- these constants shall not be zero
constant FSM_CE_DIV : integer := 1;
constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
constant SAMP_CE_DIV : integer := 1;
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
-- spi port generics
constant N : integer := 8; -- 8 bits
82,86 → 88,133
-- Type definitions
--=============================================================================================
type fsm_state_type is (st_reset, st_wait_spi_idle, st_wait_new_switch,
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish );
st_send_spi_data, st_wait_spi_ack, st_wait_spi_finish );
 
--=============================================================================================
-- Signals for state machine control
--=============================================================================================
signal state_reg : fsm_state_type := st_reset;
signal state_next : fsm_state_type := st_reset;
signal state_reg : fsm_state_type := st_reset;
signal state_next : fsm_state_type := st_reset;
 
--=============================================================================================
-- Signals for internal operation
--=============================================================================================
-- clock signals
signal core_clk : std_logic := '0'; -- core clock, direct copy of board clock
signal spi_2x_clk : std_logic := '0'; -- spi_2x clock, 50% clock divided-down from board clock
-- clock enable signals
signal samp_ce : std_logic := '1'; -- clock enable for sample inputs
signal fsm_ce : std_logic := '1'; -- clock enable for fsm logic
-- switch debouncer signals
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
signal sw_next : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data
signal new_switch : std_logic := '0'; -- detector for new switch data
-- pushbutton debouncer signals
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons
signal btn_reg : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data
signal btn_next : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data
signal new_button : std_logic := '0'; -- detector for new button data
-- spi port signals
signal spi_ssel : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
signal spi_di_req : std_logic;
signal spi_ssel_reg : std_logic;
signal spi_wr_ack : std_logic;
signal spi_rst_reg : std_logic := '1';
signal spi_rst_next : std_logic := '1';
signal spi_di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_wren_reg : std_logic := '0';
signal spi_wren_next : std_logic := '0';
--- clock enable signals ---
signal samp_ce : std_logic := '1'; -- clock enable for sample inputs
signal fsm_ce : std_logic := '1'; -- clock enable for fsm logic
--- switch debouncer signals ---
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
signal sw_next : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data
signal new_switch : std_logic := '0'; -- detector for new switch data
--- pushbutton debouncer signals ---
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons
signal btn_reg : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data
signal btn_next : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data
signal new_button : std_logic := '0'; -- detector for new button data
--- spi port signals ---
-- spi bus wires
signal spi_ssel : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
-- spi master port control signals
signal spi_rst_reg : std_logic := '1';
signal spi_rst_next : std_logic := '1';
signal spi_ssel_reg : std_logic;
signal spi_wren_reg_m : std_logic := '0';
signal spi_wren_next_m : std_logic := '0';
-- spi master port flow control flags
signal spi_di_req_m : std_logic;
signal spi_do_valid_m : std_logic;
-- spi master port parallel data bus
signal spi_di_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_m : std_logic_vector (N-1 downto 0);
-- spi master port debug flags
signal spi_rx_bit_m : std_logic;
signal spi_wr_ack_m : std_logic;
-- spi slave port control signals
signal spi_wren_reg_s : std_logic := '1';
signal spi_wren_next_s : std_logic := '0';
-- spi slave port flow control flags
signal spi_di_req_s : std_logic;
signal spi_do_valid_s : std_logic;
-- spi slave port parallel data bus
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (7 => '1', 6 => '0', 5 => '1', others => '0');
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_s : std_logic_vector (N-1 downto 0);
-- spi slave port debug flags
signal spi_rx_bit_s : std_logic;
signal spi_wr_ack_s : std_logic;
-- other signals
signal clear : std_logic := '0';
-- output signals
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered led outputs
signal dbg : std_logic_vector (9 downto 0) := (others => '0'); -- we have 10 debug pins available
signal clear : std_logic := '0';
-- debug output signals
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (7 downto 0) := (others => '0');
begin
 
--=============================================================================================
-- Component instantiation for the SPI port
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
--=============================================================================================
-- spi_port is the spi output port
Inst_spi_port: entity work.spi_master(rtl)
-- spi master port:
-- receives parallel data from the slide switches, transmits to slave port.
-- receives serial data from slave port, sends to 8bit parallel debug port.
Inst_spi_master_port: entity work.spi_master(rtl)
generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => core_clk, -- system clock is used for serial and parallel ports
pclk_i => core_clk,
sclk_i => gclk_i, -- system clock is used for serial and parallel ports
pclk_i => gclk_i,
rst_i => spi_rst_reg,
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
di_req_o => spi_di_req,
di_i => spi_di_reg,
wren_i => spi_wren_reg,
spi_miso_i => spi_miso,
di_req_o => spi_di_req_m,
di_i => spi_di_reg_m,
do_valid_o => spi_do_valid_m,
do_o => spi_do_m,
rx_bit_reg_o => spi_rx_bit_m,
wren_i => spi_wren_reg_m,
wren_o => spi_wren_o,
wren_ack_o => spi_wr_ack, -- monitor wren ack from inside spi port
core_ce_o => dbg(8), -- monitor the internal core clock enable lines
core_n_ce_o => dbg(9)
wren_ack_o => spi_wr_ack_m -- monitor wren ack from inside spi port
);
 
spi_di_req_o <= spi_di_req; -- monitor data request
spi_wren_ack_o <= spi_wr_ack;
dbg(7 downto 0) <= spi_do_m(7 downto 0); -- connect master received data to 8bit debug port
spi_rx_bit_m_o <= spi_rx_bit_m; -- connect rx_bit monitor for master port
 
-- spi slave port
-- receives parallel data from the pushbuttons, transmits to master port.
-- receives serial data from master port, sends to the 8 LEDs.
Inst_spi_slave_port: entity work.spi_slave(rtl)
generic map (N => N, CPOL => '0', CPHA => '0', PREFETCH => 3)
port map(
clk_i => gclk_i,
spi_ssel_i => spi_ssel, -- generated by the spi master
spi_sck_i => spi_sck, -- generated by the spi master
spi_mosi_i => spi_mosi,
spi_miso_o => spi_miso,
di_req_o => spi_di_req_s,
di_i => spi_di_reg_s,
wren_i => spi_wren_reg_s,
rx_bit_reg_o => spi_rx_bit_s,
do_valid_o => spi_do_valid_s,
do_o => spi_do_s
);
 
spi_di_reg_s(7 downto 5) <= B"101"; -- get the slave transmit data from pushbuttons
spi_di_reg_s(4 downto 0) <= btn_data(5 downto 1);
spi_wren_reg_s <= '1'; -- fix wren to '1', for continuous load of transmit data
spi_rx_bit_s_o <= spi_rx_bit_s; -- connect rx_bit monitor for slave port
 
-- debounce for the input switches, with new data strobe output
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 8, CNT_VAL => 10000) -- debounce 8 inputs with 100 us settling time
port map(
clk_i => core_clk, -- system clock
clk_i => gclk_i, -- system clock
data_i => sw_i, -- noisy input data
data_o => sw_data, -- registered stable output data
strb_o => dbg(0) -- monitor the debounced data strobe
data_o => sw_data -- registered stable output data
-- strb_o => dbg(0) -- monitor the debounced data strobe
);
 
-- debounce for the input pushbuttons, with new data strobe output
168,31 → 221,26
Inst_btn_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 6, CNT_VAL => 50000) -- debounce 6 inputs with 500 us settling time
port map(
clk_i => core_clk, -- system clock
clk_i => gclk_i, -- system clock
data_i => btn_i, -- noisy input data
data_o => btn_data, -- registered stable output data
strb_o => dbg(3) -- monitor the debounced data strobe
data_o => btn_data -- registered stable output data
-- strb_o => dbg(3) -- monitor the debounced data strobe
);
 
dbg1_proc: dbg(1) <= new_switch; -- monitor new_switch signal
dbg2_proc: dbg(2) <= sw_i(0); -- monitor raw input (rightmost switch)
dbg4_proc: dbg(4) <= new_button; -- monitor new_button signal
dbg5_proc: dbg(5) <= btn_i(5); -- monitor raw input (center btn)
 
--=============================================================================================
-- CONSTANTS CONSTRAINTS CHECKING
--=============================================================================================
-- clock dividers shall not be zero
assert FSM_CE_DIV > 0
report "Constant 'FSM_CE_DIV' should not be zero"
assert FSM_CE_DIV > 0
report "Constant 'FSM_CE_DIV' should not be zero"
severity FAILURE;
-- minimum prefetch lookahead check
assert SPI_2X_CLK_DIV > 0
report "Constant 'SPI_2X_CLK_DIV' should not be zero"
assert SPI_2X_CLK_DIV > 0
report "Constant 'SPI_2X_CLK_DIV' should not be zero"
severity FAILURE;
-- maximum prefetch lookahead check
assert SAMP_CE_DIV > 0
report "Constant 'SAMP_CE_DIV' should not be zero"
assert SAMP_CE_DIV > 0
report "Constant 'SAMP_CE_DIV' should not be zero"
severity FAILURE;
 
--=============================================================================================
203,8 → 251,6
-- spi 2x base clock,
-- fsm clock,
-----------------------------------------------------------------------------------------------
-- generate the core clock from the 100MHz board input clock
core_clock_gen_proc: core_clk <= gclk_i;
-- generate the sampling clock enable from the 100MHz board input clock
samp_ce_gen_proc: process (gclk_i) is
variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
233,44 → 279,29
end if;
end if;
end process fsm_ce_gen_proc;
-- generate the spi base clock from the 100MHz board input clock
-- spi_2x_clk_div_proc: spi_2x_clk <= gclk_i; -- generate 50MHz SPI SCK
spi_2x_clk_div_proc: process (gclk_i) is
variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0:= 0;
begin
if gclk_i'event and gclk_i = '1' then
if clk_cnt = SPI_2X_CLK_DIV-1 then
spi_2x_clk <= not spi_2x_clk;
clk_cnt := 0;
else
clk_cnt := clk_cnt + 1;
end if;
end if;
end process spi_2x_clk_div_proc;
 
--=============================================================================================
-- INPUTS LOGIC
--=============================================================================================
-- registered inputs
samp_inputs_proc: process (core_clk) is
samp_inputs_proc: process (gclk_i) is
begin
if core_clk'event and core_clk = '1' then
if gclk_i'event and gclk_i = '1' then
if samp_ce = '1' then
-- clear <= btn_data(btRESET); -- sample reset input
leds_reg <= sw_data; -- update LEDs with debounced switches
clear <= btn_data(btUP); -- clear is button UP
leds_reg <= spi_do_s; -- update LEDs with spi_slave received data
end if;
end if;
end process samp_inputs_proc;
 
--=============================================================================================
-- FSM REGISTER PROCESSES
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
fsm_reg_proc : process (core_clk) is
fsm_reg_proc : process (gclk_i) is
begin
-- FFD registers clocked on rising edge and cleared on sync 'clear'
if core_clk'event and core_clk = '1' then
if gclk_i'event and gclk_i = '1' then
if clear = '1' then -- sync reset
state_reg <= st_reset; -- only provide local reset for the state register
else
280,10 → 311,12
end if;
end if;
-- FFD registers clocked on rising edge, with no reset
if core_clk'event and core_clk = '1' then
if gclk_i'event and gclk_i = '1' then
if fsm_ce = '1' then
spi_wren_reg <= spi_wren_next;
spi_di_reg <= spi_di_next;
spi_wren_reg_m <= spi_wren_next_m;
spi_di_reg_m <= spi_di_next_m;
-- spi_wren_reg_s <= spi_wren_next_s;
-- spi_di_reg_s <= spi_di_next_s;
spi_rst_reg <= spi_rst_next;
spi_ssel_reg <= spi_ssel;
sw_reg <= sw_next;
293,21 → 326,23
end process fsm_reg_proc;
 
--=============================================================================================
-- FSM COMBINATORIAL NEXT-STATE LOGIC PROCESSES
-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES
--=============================================================================================
-- edge detector for new switch data
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for difference
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for difference
-- edge detector for new button data
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for difference
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for difference
-- fsm state and combinatorial logic
-- the sequencer will wait for a new switch combination, and send the switch data to the spi port
fsm_combi_proc: process ( state_reg, spi_wren_reg, spi_di_reg, spi_di_req, spi_wr_ack,
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch,
btn_data, btn_reg, new_button) is
fsm_combi_proc: process ( state_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, -- spi_di_reg_s,
spi_wren_reg_s, spi_ssel_reg, spi_rst_reg, sw_data,
sw_reg, new_switch, btn_data, btn_reg, new_button) is
begin
spi_di_next <= spi_di_reg;
spi_rst_next <= spi_rst_reg;
spi_wren_next <= spi_wren_reg;
spi_di_next_m <= spi_di_reg_m;
spi_wren_next_m <= spi_wren_reg_m;
-- spi_di_next_s <= spi_di_reg_s;
-- spi_wren_next_s <= spi_wren_reg_s;
sw_next <= sw_reg;
btn_next <= btn_reg;
state_next <= state_reg;
314,8 → 349,10
case state_reg is
when st_reset =>
spi_rst_next <= '1'; -- place spi interface on reset
spi_di_next <= (others => '0'); -- clear spi data port
spi_wren_next <= '0'; -- deassert write enable
spi_di_next_m <= (others => '0'); -- clear spi data port
spi_di_next_s <= (others => '0'); -- clear spi data port
spi_wren_next_m <= '0'; -- deassert write enable
spi_wren_next_s <= '0'; -- deassert write enable
state_next <= st_wait_spi_idle;
when st_wait_spi_idle =>
330,20 → 367,20
state_next <= st_send_spi_data;
elsif new_button = '1' then
btn_next <= btn_data; -- load new button data (end the mismatch condition)
if btn_data /= (5 downto 0 => '0') then
if btn_data /= B"000001" then
state_next <= st_send_spi_data;
end if;
end if;
when st_send_spi_data =>
spi_di_next <= sw_reg; -- load switch register to the spi port
spi_wren_next <= '1'; -- write data on next clock
spi_di_next_m <= sw_reg; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
state_next <= st_wait_spi_ack;
 
when st_wait_spi_ack => -- the actual write happens on this state
spi_di_next <= sw_reg; -- load switch register to the spi port
if spi_wr_ack = '1' then -- wait acknowledge
spi_wren_next <= '0'; -- remove write strobe on next clock
spi_di_next_m <= sw_reg; -- load switch register to the spi port
if spi_wr_ack_m = '1' then -- wait acknowledge
spi_wren_next_m <= '0'; -- remove write strobe on next clock
state_next <= st_wait_spi_finish;
end if;
361,17 → 398,20
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- connect the spi output wires
spi_ssel_o_proc: spi_ssel_o <= spi_ssel;
spi_sck_o_proc: spi_sck_o <= spi_sck;
spi_mosi_o_proc: spi_mosi_o <= spi_mosi;
-- connect leds_reg signal to LED outputs
leds_out_proc: led_o <= leds_reg;
spi_ssel_o_proc: spi_ssel_o <= spi_ssel;
spi_sck_o_proc: spi_sck_o <= spi_sck;
spi_mosi_o_proc: spi_mosi_o <= spi_mosi;
spi_miso_o_proc: spi_miso_o <= spi_miso;
spi_do_valid_o_proc: spi_do_valid_o <= spi_do_valid_m;
spi_di_req_o_proc: spi_di_req_o <= spi_di_req_m;
spi_wren_ack_o_proc: spi_wren_ack_o <= spi_wr_ack_m;
led_o_proc: led_o <= leds_reg; -- connect leds_reg signal to LED outputs
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- connect the debug vector outputs
dbg_o_proc: dbg_o <= dbg;
dbg_o_proc: dbg_o <= dbg;
 
end behavioral;
 
/trunk/syn/spi_slave.vhd
0,0 → 1,385
----------------------------------------------------------------------------------
-- Author: Jonny Doin, jdoin@opencores.org
--
-- Create Date: 15:36:20 05/15/2011
-- Module Name: SPI_SLAVE - RTL
-- Project Name: SPI INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI slave interface, implemented in one single entity.
-- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
-- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
-- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
--
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch
-- signaling ('PREFETCH').
--
-- PARALLEL WRITE INTERFACE
-- The parallel interface has a input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'.
-- When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i'
-- cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i'
-- in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long.
-- The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid
-- race conditions at the register transfer.
-- The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'.
-- For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle,
-- if continuous transmission is intended.
-- When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'.
--
-- PARALLEL WRITE PIPELINED SEQUENCE
-- =================================
-- __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'clk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'clk_i' rising edge
-- ________
-- wren_i __________________________/ \______... -- 'wren_i' enables latch on rising edge of 'clk_i'
--
--
-- PARALLEL READ INTERFACE
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete
-- word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'.
-- The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ PIPELINED SEQUENCE
-- ================================
-- ______ ______ ______ ______
-- clk_spi_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi base clock
-- __ __ __ __ __ __ __ __ __
-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock
-- _________________ _____________________________________... -- 1) received data is transferred to 'do_buffer_reg'
-- do_o __old_data_______X__________new_data___________________... -- after last bit received, at next shift clock.
-- ____________
-- do_valid_o ________________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles
-- -- on the 3rd 'clk_i' rising edge.
--
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, jdoin@opencores.org
--
-- Copyright (C) 2011 Authors and OPENCORES.ORG
-- --------------------------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.opencores.org/lgpl.shtml
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/05/15 v0.10.0050 [JD] created the slave logic, with 2 clock domains, from SPI_MASTER module.
-- 2011/05/15 v0.15.0055 [JD] fixed logic for starting state when CPHA='1'.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/06/17 v0.97.0079 [JD] implemented wren_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
--
-----------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity spi_slave is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
wren_ack_o : out std_logic; -- debug: wren ack from state machine
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (5 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_slave;
 
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
--================================================================================================================
 
architecture RTL of spi_slave is
-- constants to control FlipFlop synthesis
constant SAMPLE_EDGE : std_logic := (CPOL xnor CPHA);
constant SAMPLE_LEVEL : std_logic := SAMPLE_EDGE;
constant SHIFT_EDGE : std_logic := (CPOL xor CPHA);
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a local reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
--
-- internal state signals for register and combinational stages
signal state_next : natural range N+1 downto 0 := 0;
signal state_reg : natural range N+1 downto 0 := 0;
-- shifter signals for register and combinational stages
signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinational stages
signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal wren_i stretcher for fsm combinational stage
signal wren : std_logic := '0';
signal wren_ack_next : std_logic := '0';
signal wren_ack_reg : std_logic := '0';
-- buffered do_o data signals for register and combinational stages
signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req : std_logic := '0';
-- cross-clock do_valid_o logic
signal do_valid_next : std_logic := '0';
signal do_valid_A : std_logic := '0';
signal do_valid_B : std_logic := '0';
signal do_valid_C : std_logic := '0';
signal do_valid_D : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_o logic
signal di_req_o_next : std_logic := '0';
signal di_req_o_A : std_logic := '0';
signal di_req_o_B : std_logic := '0';
signal di_req_o_C : std_logic := '0';
signal di_req_o_D : std_logic := '0';
signal di_req_o_reg : std_logic := '0';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N-5
report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum"
severity FAILURE;
 
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
rx_bit_proc : process (spi_sck_i, spi_mosi_i) is
begin
if spi_sck_i'event and spi_sck_i = SAMPLE_EDGE then
rx_bit_reg <= spi_mosi_i;
end if;
end process rx_bit_proc;
 
--=============================================================================================
-- RTL CORE REGISTER PROCESSES
--=============================================================================================
-- fsm state and data registers change on spi SHIFT clock
core_reg_proc : process (spi_sck_i, spi_ssel_i) is
begin
-- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
if spi_ssel_i = '1' then -- async clr
state_reg <= 0; -- state falls back to idle when slave not selected
elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update all core registers
state_reg <= state_next; -- core fsm changes state with spi SHIFT clock
end if;
-- FFD registers clocked on SHIFT edge
if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers
sh_reg <= sh_next; -- core shift register
do_buffer_reg <= do_buffer_next; -- registered data output
do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag
wren_ack_reg <= wren_ack_next; -- wren ack for data load synchronization
end if;
end process core_reg_proc;
 
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process ( clk_i, do_transfer_reg, di_req,
do_valid_A, do_valid_B, do_valid_D,
di_req_o_A, di_req_o_B, di_req_o_D) is
begin
if clk_i'event and clk_i = '1' then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs
do_valid_C <= do_valid_B;
do_valid_D <= do_valid_C;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req -> di_req_o_reg
di_req_o_A <= di_req; -- the input signal must be at least 2 clocks long
di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs
di_req_o_C <= di_req_o_B;
di_req_o_D <= di_req_o_C;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc: process (clk_i, wren_i, wren_ack_reg) is
begin
-- registered data input, input register with clock enable
if clk_i'event and clk_i = '1' then
if wren_i = '1' then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if clk_i'event and clk_i = '1' then
if wren_i = '1' then -- wren_i is the sync preset for wren
wren <= '1';
elsif wren_ack_reg = '1' then -- wren_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
 
--=============================================================================================
-- RTL COMBINATIONAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinational logic
core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, do_buffer_reg,
do_transfer_reg, di_reg, wren, wren_ack_reg) is
begin
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wren_ack_next <= '0'; -- remove data load ack for all but the load stages
di_req <= '0'; -- prefetch data request: deassert when shifting data
spi_miso_o <= sh_reg(N-1); -- output serial data from the MSb
state_next <= state_reg - 1; -- update next state at each sck pulse
case state_reg is
when (N) =>
do_transfer_next <= '0'; -- reset transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
when (N-1) downto (PREFETCH+3) =>
do_transfer_next <= '0'; -- reset transfer signal
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
when (PREFETCH+2) downto 2 =>
-- raise data prefetch request
di_req <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
when 1 =>
-- restart from state 'N' if more sck pulses come
di_req <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
do_transfer_next <= '1'; -- signal transfer to do_buffer
state_next <= N; -- next state is top bit of new data
if wren = '1' then -- load tx register if valid data present at di_reg
sh_next <= di_reg; -- load parallel data from di_reg into shifter
wren_ack_next <= '1'; -- acknowledge data in transfer
else
sh_next <= (others => '0'); -- load null data (output '0' if no load)
end if;
when 0 =>
di_req <= not wren_ack_reg; -- will request data if shifter empty
do_transfer_next <= '0'; -- clear signal transfer to do_buffer
spi_miso_o <= di_reg(N-1); -- shift out first tx bit from the MSb
if CPHA = '0' then
-- initial state for CPHA=0, when slave interface is first selected or idle
state_next <= N-1; -- next state is top bit of new data
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits
wren_ack_next <= '1'; -- acknowledge data in transfer
else
-- initial state for CPHA=1, when slave interface is first selected or idle
state_next <= N; -- next state is top bit of new data
sh_next <= di_reg; -- load parallel data from di_reg into shifter
end if;
when others =>
state_next <= 0; -- state 0 is safe state
end case;
end process core_combi_proc;
 
--=============================================================================================
-- RTL OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
do_o_proc : do_o <= do_buffer_reg; -- do_o always available
do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output
di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output
 
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted or commented-out after debug.
do_transfer_proc: do_transfer_o <= do_transfer_reg;
state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
rx_bit_reg_proc: rx_bit_reg_o <= rx_bit_reg;
wren_o_proc: wren_o <= wren;
wren_ack_o_proc: wren_ack_o <= wren_ack_reg;
sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug
end architecture RTL;
 
/trunk/syn/spi_master.vhd
133,11 → 133,11
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
-- > verify the receive interface in silicon, and determine the top usable frequency.
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
146,6 → 146,8
use ieee.std_logic_unsigned.all;
 
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
193,7 → 195,7
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
architecture RTL of spi_master is
-- core clocks, generated from 'sclk_i': initialized to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
375,13 → 377,13
-- ATTENTION: REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO
-- REDUCED DEMAND ON MISO SETUP TIME.
--
rx_bit_proc : process (sclk_i) is
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if sclk_i'event and sclk_i = '1' then
if samp_ce = '1' then
-- if sclk_i'event and sclk_i = '1' then
-- if samp_ce = '1' then
rx_bit_reg <= spi_miso_i;
end if;
end if;
-- end if;
-- end if;
end process rx_bit_proc;
 
--=============================================================================================
562,5 → 564,5
core_ce_o_proc: core_ce_o <= core_ce;
core_n_ce_o_proc: core_n_ce_o <= core_n_ce;
 
end architecture rtl;
end architecture RTL;
 
/trunk/syn/ATLYS_02.SET
0,0 → 1,772
:SELECT:DALL 0
:ACQUIRE:STOPAFTER RUNSTOP
:ACQUIRE:STATE 1
:ACQUIRE:MODE SAMPLE
:ACQUIRE:NUMENV INFINITE
:ACQUIRE:NUMAVG 128
:ACQUIRE:MAGNIVU 0
:HEADER 0
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:MESSAGE:SHOW ""
:MESSAGE:BOX 92,39,92,49
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:D2:THRESHOLD 1.2600
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:D9:THRESHOLD 1.2600
:D10:THRESHOLD 1.2600
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:D0:POSITION -3.9400
:D1:POSITION -3.4400
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:D0:LABEL ""
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:D3:LABEL ""
:D4:LABEL ""
:D5:LABEL ""
:D6:LABEL ""
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:D8:LABEL "DO_VALID"
:D9:LABEL "RX_BITs"
:D10:LABEL "RX_BITm"
:D11:LABEL "DI_REQ"
:D12:LABEL "MISO"
:D13:LABEL "MOSI"
:D14:LABEL "SCK"
:D15:LABEL "SSEL"
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:MATH:SPECTRAL:MAG DB
:MATH:SPECTRAL:WINDOW HANNING
:MATH:SPECTRAL:GATING:INDICATORS 0
:MATH:LABEL ""
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:TRIGGER:A:UPPERTHRESHOLD:CH4 1.4000
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:TRIGGER:A:LOGIC:THRESHOLD:D3 1.2600
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:TRIGGER:A:BUS:B1:CAN:DATA:QUALIFIER EQUAL
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:TRIGGER:A:BUS:B1:CAN:IDENTIFIER:MODE STANDARD
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:TRIGGER:A:BUS:B1:CAN:IDENTIFIER:VALUE "XXXXXXXXXXX"
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:TRIGGER:A:BUS:B1:LIN:CONDITION SYNCFIELD
:TRIGGER:A:BUS:B2:LIN:CONDITION SYNCFIELD
:TRIGGER:A:BUS:B1:LIN:DATA:SIZE 1
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:TRIGGER:A:BUS:B1:LIN:DATA:HIVALUE "XXXXXXXX"
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:TRIGGER:A:BUS:B2:RS232C:RX:DATA:SIZE 1
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:TRIGGER:A:BUS:B1:RS232C:TX:DATA:VALUE "XXXXXXXX"
:TRIGGER:A:BUS:B2:RS232C:TX:DATA:VALUE "XXXXXXXX"
:TRIGGER:A:BUS:B1:PARALLEL:VALUE "XXXXXXXXX0XXXXXX"
:TRIGGER:A:BUS:B2:PARALLEL:VALUE "XXXXXXXX"
:TRIGGER:EXTERNAL:PROBE 10.0000
:BUS:B1:I2C:DATA:SOURCE D15
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:BUS:B1:I2C:CLOCK:SOURCE D14
:BUS:B2:I2C:CLOCK:SOURCE CH1
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:BUS:B2:I2C:ADDRESS:RWINCLUDE 0
:BUS:B1:SPI:DATA:IN:SOURCE D12
:BUS:B2:SPI:DATA:IN:SOURCE OFF
:BUS:B1:SPI:DATA:IN:POLARITY HIGH
:BUS:B2:SPI:DATA:IN:POLARITY HIGH
:BUS:B1:SPI:DATA:OUT:SOURCE D13
:BUS:B2:SPI:DATA:OUT:SOURCE CH3
:BUS:B1:SPI:DATA:OUT:POLARITY HIGH
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:BUS:B1:SPI:DATA:SIZE 8
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:BUS:B2:SPI:FRAMING SS
:BUS:B1:SPI:BITORDER MSB
:BUS:B2:SPI:BITORDER MSB
:BUS:B1:SPI:IDLETIME 5.0000E-6
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:BUS:B1:CAN:SOURCE D14
:BUS:B2:CAN:SOURCE CH1
:BUS:B1:CAN:BITRATE 500000
:BUS:B2:CAN:BITRATE 500000
:BUS:B1:CAN:PROBE CANH
:BUS:B2:CAN:PROBE CANH
:BUS:B1:CAN:SAMPLEPOINT 50
:BUS:B2:CAN:SAMPLEPOINT 50
:BUS:B1:LIN:SOURCE D14
:BUS:B2:LIN:SOURCE CH1
:BUS:B1:LIN:POLARITY NORMAL
:BUS:B2:LIN:POLARITY NORMAL
:BUS:B1:LIN:BITRATE 19200
:BUS:B2:LIN:BITRATE 19200
:BUS:B1:LIN:SAMPLEPOINT 50
:BUS:B2:LIN:SAMPLEPOINT 50
:BUS:B1:LIN:STANDARD V2X
:BUS:B2:LIN:STANDARD V2X
:BUS:B1:LIN:IDFORMAT NOPARITY
:BUS:B2:LIN:IDFORMAT NOPARITY
:BUS:B1:RS232C:PARITY NONE
:BUS:B2:RS232C:PARITY NONE
:BUS:B1:RS232C:BITRATE 9600
:BUS:B2:RS232C:BITRATE 9600
:BUS:B1:RS232C:POLARITY NORMAL
:BUS:B2:RS232C:POLARITY NORMAL
:BUS:B1:RS232C:DATABITS 8
:BUS:B2:RS232C:DATABITS 8
:BUS:B1:RS232C:TX:SOURCE CH1
:BUS:B2:RS232C:TX:SOURCE CH1
:BUS:B1:RS232C:RX:SOURCE D12
:BUS:B2:RS232C:RX:SOURCE OFF
:BUS:B1:RS232C:DISPLAYMODE FRAME
:BUS:B2:RS232C:DISPLAYMODE FRAME
:BUS:B1:RS232C:DELIMITER LF
:BUS:B2:RS232C:DELIMITER LF
:BUS:B1:STATE 1
:BUS:B2:STATE 1
:BUS:B1:TYPE SPI
:BUS:B2:TYPE PARALLEL
:BUS:B1:POSITION 3.5800
:BUS:B2:POSITION -2.6200
:BUS:B1:DISPLAY:TYPE BUS
:BUS:B2:DISPLAY:TYPE BUS
:BUS:B1:DISPLAY:FORMAT HEXADECIMAL
:BUS:B2:DISPLAY:FORMAT HEXADECIMAL
:BUS:B1:LABEL "SPI"
:BUS:B2:LABEL "PAR_DATA"
:BUS:B1:PARALLEL:WIDTH 16
:BUS:B2:PARALLEL:WIDTH 8
:BUS:B1:PARALLEL:CLOCK:ISCLOCKED NO
:BUS:B2:PARALLEL:CLOCK:ISCLOCKED NO
:BUS:B1:PARALLEL:CLOCK:SOURCE CH1
:BUS:B2:PARALLEL:CLOCK:SOURCE CH1
:BUS:B1:PARALLEL:CLOCK:EDGE RISING
:BUS:B2:PARALLEL:CLOCK:EDGE RISING
:BUS:B1:PARALLEL:BIT0:SOURCE D0
:BUS:B1:PARALLEL:BIT1:SOURCE D1
:BUS:B1:PARALLEL:BIT2:SOURCE D2
:BUS:B1:PARALLEL:BIT3:SOURCE D3
:BUS:B1:PARALLEL:BIT4:SOURCE D4
:BUS:B1:PARALLEL:BIT5:SOURCE D5
:BUS:B1:PARALLEL:BIT6:SOURCE D6
:BUS:B1:PARALLEL:BIT7:SOURCE D7
:BUS:B1:PARALLEL:BIT8:SOURCE D8
:BUS:B1:PARALLEL:BIT9:SOURCE D9
:BUS:B1:PARALLEL:BIT10:SOURCE D10
:BUS:B1:PARALLEL:BIT11:SOURCE D11
:BUS:B1:PARALLEL:BIT12:SOURCE D12
:BUS:B1:PARALLEL:BIT13:SOURCE D13
:BUS:B1:PARALLEL:BIT14:SOURCE D14
:BUS:B1:PARALLEL:BIT15:SOURCE D15
:BUS:B1:PARALLEL:BIT16:SOURCE CH1
:BUS:B1:PARALLEL:BIT17:SOURCE CH2
:BUS:B1:PARALLEL:BIT18:SOURCE CH3
:BUS:B1:PARALLEL:BIT19:SOURCE CH4
:BUS:B2:PARALLEL:BIT0:SOURCE D0
:BUS:B2:PARALLEL:BIT1:SOURCE D1
:BUS:B2:PARALLEL:BIT2:SOURCE D2
:BUS:B2:PARALLEL:BIT3:SOURCE D3
:BUS:B2:PARALLEL:BIT4:SOURCE D4
:BUS:B2:PARALLEL:BIT5:SOURCE D5
:BUS:B2:PARALLEL:BIT6:SOURCE D6
:BUS:B2:PARALLEL:BIT7:SOURCE D7
:BUS:B2:PARALLEL:BIT8:SOURCE D8
:BUS:B2:PARALLEL:BIT9:SOURCE D9
:BUS:B2:PARALLEL:BIT10:SOURCE D10
:BUS:B2:PARALLEL:BIT11:SOURCE D11
:BUS:B2:PARALLEL:BIT12:SOURCE D12
:BUS:B2:PARALLEL:BIT13:SOURCE D13
:BUS:B2:PARALLEL:BIT14:SOURCE D14
:BUS:B2:PARALLEL:BIT15:SOURCE D15
:BUS:B2:PARALLEL:BIT16:SOURCE CH1
:BUS:B2:PARALLEL:BIT17:SOURCE CH2
:BUS:B2:PARALLEL:BIT18:SOURCE CH3
:BUS:B2:PARALLEL:BIT19:SOURCE CH4
:BUS:LOWERTHRESHOLD:CH1 172.0000E-3
:BUS:LOWERTHRESHOLD:CH2 0.0E+0
:BUS:LOWERTHRESHOLD:CH3 0.0E+0
:BUS:LOWERTHRESHOLD:CH4 0.0E+0
:BUS:UPPERTHRESHOLD:CH1 256.0000E-3
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:BUS:UPPERTHRESHOLD:CH3 1.4000
:BUS:UPPERTHRESHOLD:CH4 1.4000
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:SPI:CONDITION SS
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:SPI:CONDITION SS
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:SPI:DATA:MOSI:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:SPI:DATA:MOSI:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:SPI:DATA:MISO:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:SPI:DATA:MISO:VALUE "XXXXXXXX"
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:SPI:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:CONDITION TXSTART
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:CONDITION TXSTART
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:RX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:RX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:RX:DATA:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:RX:DATA:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:TX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:RS232C:TX:DATA:SIZE 1
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:RS232C:TX:DATA:VALUE "XXXXXXXX"
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:I2C:CONDITION START
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:I2C:DATA:VALUE "XXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:I2C:DATA:VALUE "XXXXXXXX"
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:I2C:DATA:SIZE 1
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:I2C:DATA:DIRECTION NOCARE
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:I2C:ADDRESS:MODE ADDR7
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:I2C:ADDRESS:MODE ADDR7
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:I2C:ADDRESS:TYPE USER
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:I2C:ADDRESS:TYPE USER
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:I2C:ADDRESS:VALUE "XXXXXXX"
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:CAN:CONDITION SOF
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:CAN:FRAMETYPE DATA
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:CAN:FRAMETYPE DATA
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:CAN:DATA:QUALIFIER EQUAL
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:CAN:IDENTIFIER:MODE STANDARD
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:CAN:IDENTIFIER:VALUE "XXXXXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:CAN:IDENTIFIER:VALUE "XXXXXXXXXXX"
:SEARCH:SEARCH1:TRIGGER:A:BUS:B1:LIN:CONDITION SYNCFIELD
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:SEARCH:SEARCH1:TRIGGER:A:BUS:B2:LIN:ERRTYPE SYNC
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:SEARCH:SEARCH1:TRIGGER:A:UPPERTHRESHOLD:CH4 1.4000
:SEARCH:SEARCH1:TRIGGER:A:UPPERTHRESHOLD:MATH 492.0000E-3
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:SEARCH:SEARCH1:TRIGGER:A:LOWERTHRESHOLD:CH1 0.0E+0
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:SEARCH:SEARCH1:TRIGGER:A:LOWERTHRESHOLD:CH4 0.0E+0
:SEARCH:SEARCH1:TRIGGER:A:LOWERTHRESHOLD:MATH 0.0E+0
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:SEARCH:SEARCH1:TRIGGER:A:EDGE:SOURCE D8
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:FUNCTION AND
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:THRESHOLD:CH1 0.0E+0
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:INPUT:CH1 X
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D5 X
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D9 X
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:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D14 X
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:INPUT:D15 X
:SEARCH:SEARCH1:TRIGGER:A:LOGIC:PATTERN:WHEN TRUE
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:ZOOM:ZOOM1:HORIZONTAL:POSITION 50.1172
:ZOOM:ZOOM1:HORIZONTAL:SCALE 40.0000E-9
:CURSOR:FUNCTION WAVEFORM
:CURSOR:MODE INDEPENDENT
:CURSOR:VBARS:POSITION1 84.0E-9
:CURSOR:VBARS:POSITION2 78.40E-9
:CURSOR:VBARS:UNITS SECONDS
:CURSOR:HBARS:POSITION1 0.0E+0
:CURSOR:HBARS:POSITION2 0.0E+0
:CURSOR:HBARS:UNITS BASE
:CURSOR:XY:READOUT RECTANGULAR
:CURSOR:XY:RECTANGULAR:X:POSITION1 0.0E+0
:CURSOR:XY:RECTANGULAR:X:POSITION2 0.0E+0
:CURSOR:XY:RECTANGULAR:Y:POSITION1 0.0E+0
:CURSOR:XY:RECTANGULAR:Y:POSITION2 0.0E+0
:MEASUREMENT:IMMED:DELAY:DIRECTION FORWARDS
:MEASUREMENT:IMMED:DELAY:EDGE1 RISE
:MEASUREMENT:IMMED:DELAY:EDGE2 RISE
:MEASUREMENT:IMMED:TYPE PERIOD
:MEASUREMENT:IMMED:SOURCE1 CH1
:MEASUREMENT:IMMED:SOURCE2 CH2
:MEASUREMENT:MEAS1:DELAY:DIRECTION FORWARDS
:MEASUREMENT:MEAS2:DELAY:DIRECTION FORWARDS
:MEASUREMENT:MEAS3:DELAY:DIRECTION FORWARDS
:MEASUREMENT:MEAS4:DELAY:DIRECTION FORWARDS
1425 .text rt_heap_descriptor_intlibspace.o(c_t__un.l)
0x00018cd8 0x0000009c Code RO 1431 .text init_alloc.o(c_t__un.l)
0x00018d74 0x00000004 Code RO 1433 .text hguard.o(c_t__un.l)
0x00018d78 0x000000aa Code RO 1447 .text _printf_intcommon.o(c_t__un.l)
0x00018e22 0x00000002 PAD
0x00018e24 0x00000034 Code RO 1449 .text _printf_char_common.o(c_t__un.l)
0x00018e58 0x0000000a Code RO 1451 .text _sputc.o(c_t__un.l)
0x00018e62 0x00000002 PAD
0x00018e64 0x0000007c Code RO 1453 .text strtol.o(c_t__un.l)
0x00018ee0 0x00000080 Code RO 1455 .text rt_memmove_w.o(c_t__un.l)
0x00018f60 0x00000004 Ven RO 1457 .text rtudiv10.o(c_t__un.l)
0x00018f64 0x0000002c Code RO 1457 .text rtudiv10.o(c_t__un.l)
0x00018f90 0x000000b0 Code RO 1459 .text stkheap1.o(c_t__un.l)
0x00019040 0x00000008 Ven RO 1472 .text lib_init.o(c_t__un.l)
0x00019048 0x000000d6 Code RO 1472 .text lib_init.o(c_t__un.l)
0x0001911e 0x00000002 PAD
0x00019120 0x0000000c Code RO 1477 .text
/trunk/syn/spi_master_atlys.xise
17,19 → 17,23
<files>
<file xil_pn:name="spi_master_atlys_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="grp_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="spi_master_atlys.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
</files>
 
<properties>
/trunk/syn/readme.txt
1,11 → 1,10
SPI_MASTER_ATLYS
================
 
This is a ISE 13.1 project to test the spi_master.vhd model in silicon.
 
This is a ISE 13.1 project to test the spi_master.vhd, spi_slave.vhd and grp_debouncer.vhd models in silicon.
The target board is a Digilent Atlys FPGA board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies.
 
See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested.
The circuit verifies both master and slave cores, with transmit and receive streams operating full-duplex at 50MHz of SPI clock.
 
This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license.
 
26,7 → 25,8
 
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer.
 
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at http://opencores.org/project,spi_master_slave,bugtracker.
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at
http://opencores.org/project,spi_master_slave,bugtracker
 
In any case, thank you very much for testing this core.
 
/trunk/syn/spi_master_scope_photos.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/syn/grp_debouncer.vhd
3,7 → 3,7
--
-- Create Date: 09:56:30 07/06/2011
-- Module Name: grp_debouncer - RTL
-- Project Name: generic functions
-- Project Name: basic functions
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
84,26 → 84,26
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
--
--
-- Author(s): Jonny Doin, jdoin@opencores.org
--
--
-- Copyright (C) 2011 Authors
-- --------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- --------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.opencores.org/lgpl.shtml
-- it from http://www.opencores.org/lgpl.shtml
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
/trunk/syn/spi_master_atlys.ucf
219,8 → 219,8
# Channnel 1 connects to P signals, Channel 2 to N signals
NET "spi_ssel_o" LOC = "U16"; # Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = EXP-IO1_P, MSO D15
NET "spi_mosi_o" LOC = "U15"; # Bank = 2, Pin name = *IO_L5P, Sch name = EXP-IO2_P, MSO D13
NET "spi_wren_o" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P, MSO D11
NET "dbg_o<9>" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P, MSO D9
NET "spi_di_req_o" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P, MSO D11
NET "spi_rx_bit_s_o" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P, MSO D9
NET "dbg_o<7>" LOC = "R11"; # Bank = 2, Pin name = IO_L16P, Sch name = EXP-IO5_P, MSO D7
NET "dbg_o<5>" LOC = "T12"; # Bank = 2, Pin name = *IO_L19P, Sch name = EXP-IO6_P, MSO D5
NET "dbg_o<3>" LOC = "N10"; # Bank = 2, Pin name = *IO_L20P, Sch name = EXP-IO7_P, MSO D3
239,9 → 239,9
# NET "VHDCIIO1<19>" LOC = "U5"; # Bank = 2, Pin name = IO_49P_D3, Sch name = EXP-IO20_P
NET "spi_sck_o" LOC = "V16"; # Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = EXP-IO1_N, MSO D14
NET "spi_di_req_o" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N, MSO D12
NET "spi_wren_ack_o" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N, MSO D10
NET "dbg_o<8>" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N, MSO D8
NET "spi_miso_o" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N, MSO D12
NET "spi_rx_bit_m_o" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N, MSO D10
NET "spi_do_valid_o" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N, MSO D8
NET "dbg_o<6>" LOC = "T11"; # Bank = 2, Pin name = IO_L16N_VREF, Sch name = EXP-IO5_N, MSO D6
NET "dbg_o<4>" LOC = "V12"; # Bank = 2, Pin name = *IO_L19N, Sch name = EXP-IO6_N, MSO D4
NET "dbg_o<2>" LOC = "P11"; # Bank = 2, Pin name = *IO_L20N, Sch name = EXP-IO7_N, MSO D2

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