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steelcore/docs/images/dwrite_wave.png Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: steelcore/docs/overview.md =================================================================== --- steelcore/docs/overview.md (revision 11) +++ steelcore/docs/overview.md (nonexistent) @@ -1,31 +0,0 @@ -# Overview - -## About Steel Core - -Steel is a 3-stage single-issue in-order RISC-V microprocessor core designed to be simple and easy to use. It is intended for use in FPGAs as the processing unit in embedded systems projects. - -**Key features:** - -* Easy to use -* Targeted for use in FPGAs -* Implements the RV32I base instruction set + Zicsr extension -* M-mode privilege level support -* Hardware described in Verilog -* 3 pipeline stages -* Single-issue -* Fully documented - -## Licensing - -Steel is distributed under the [MIT License](https://en.wikipedia.org/wiki/MIT_License). The license text is reproduced in the `LICENCE.md` file. Read it carefully and make sure you understand its terms before using Steel in your own projects. - -## Specifications version - -Steel aims to be compliant with the following RISC-V specifications: - -* Version **20191213** of RISC-V Unprivileged ISA -* Version **20190608-Priv-MSU-Ratified** of RISC-V Privileged Architecture - -## Online repository - -Steel files and documentation are available at GitHub ([github.com/rafaelcalcada/steel-core](https://github.com/rafaelcalcada/steel-core)). Index: steelcore/docs/timing.md =================================================================== --- steelcore/docs/timing.md (revision 11) +++ steelcore/docs/timing.md (nonexistent) @@ -1,46 +0,0 @@ -# Timing Diagrams - -## Instruction fetch - -To fetch an instruction, the core places the instruction address on the `I_ADDR` bus. The memory must place the instruction on the `INSTR` bus at the next clock rising edge. The figure below shows the timing diagram of this process. In the figure, **mem[addrX]** denotes the instruction stored at the memory position **addrX**. - -![Instruction fetch timing diagram](images/ifetch_wave.png) - -## Data fetch - -To fetch data from memory, the core puts the data address on the `D_ADDR` bus. The memory must place the data on the `DATA_IN` bus at the next clock rising edge. The figure below shows the timing diagram of this process. In the figure, **mem[addrX]** denotes the data stored at the memory position **addrX**. - -![Data fetch timing diagram](images/dfetch_wave.png) - -## Data writing - -To write data to memory, the core drives `D_ADDR`, `DATA_OUT`, `WR_REQ` and `WR_MASK` signals as follows: - -* `D_ADDR` receives the address of the memory position where the data must be written; -* `DATA_OUT` receives the data to be written; -* `WR_REQ` is set high; -* `WR_MASK` receives a byte-write enable mask that indicates which bytes of `DATA_OUT` must be written. - -The memory must perform the write operation at the next clock rising edge. The core can request to write bytes, halfwords and words. - -The figure below shows the process of writing data to memory. `DATA_IN` is not used in the process and appears only to show the memory contents after writing. The figure shows five clock cycles, in which the core requests to write in the second, third and fourth cycles. In the second clock cycle, the core requests to write the word **0x12345678** at the address **addr2**. In the third, requests to write the halfword **0xABCD** at the upper half of **addr2**, and in the fourth requests to write the byte **0xEF** at the second least significant byte of **addr2**. The content of **addr2** after each of these operations appears on the `DATA_IN` bus and are highlighted in blue. - -![Data writing timing diagram](images/dwrite_wave.png) - -## Interrupt request - -An external device (or an interrupt controller managing several devices) can request interrupts by setting high the appropriate IRQ signal, which is `E_IRQ` for external interrupts, `T_IRQ` for timer interrupts and `S_IRQ` for software interrupts. The IRQ signal of the requested interrupt must be set high for one clock cycle and set low for the next. - -The figure below shows the timing diagram of the interrupt request process. Since the process is the same for all types of interrupt, **X_IRQ** is used to denote `E_IRQ`, `T_IRQ` or `S_IRQ`. **TRAP_ADDR** denotes the address of the trap handler first instruction. - -

- -

- -## *time* CSR update - -When connected to a real-time counter, the core updates the `time` CSR with the value placed on `REAL_TIME` at each clock rising edge, as shown in the figure below. **timeX** denotes arbitrary time values. - -

- -

Index: steelcore/docs/index.md =================================================================== --- steelcore/docs/index.md (revision 11) +++ steelcore/docs/index.md (nonexistent) @@ -1,31 +0,0 @@ -# Overview - -## About Steel Core - -Steel is a 3-stage single-issue in-order RISC-V microprocessor core designed to be simple and easy to use. It is intended for use in FPGAs as the processing unit in embedded systems projects. - -**Key features:** - -* Easy to use -* Targeted for use in FPGAs -* Implements the RV32I base instruction set + Zicsr extension -* M-mode privilege level support -* Hardware described in Verilog -* 3 pipeline stages -* Single-issue -* Fully documented - -## Licensing - -Steel is distributed under the [MIT License](https://en.wikipedia.org/wiki/MIT_License). The license text is reproduced in the `LICENCE.md` file. Read it carefully and make sure you understand its terms before using Steel in your own projects. - -## Specifications version - -Steel aims to be compliant with the following RISC-V specifications: - -* Version **20191213** of RISC-V Unprivileged ISA -* Version **20190608-Priv-MSU-Ratified** of RISC-V Privileged Architecture - -## Online repository - -Steel files and documentation are available at GitHub ([github.com/rafaelcalcada/steel-core](https://github.com/rafaelcalcada/steel-core)). Index: steelcore/docs/traps.md =================================================================== --- steelcore/docs/traps.md (revision 11) +++ steelcore/docs/traps.md (nonexistent) @@ -1,39 +0,0 @@ -# Exceptions and Interrupts - -## Supported exceptions and interrupts - -Steel supports the exceptions and interrupts shown in the table below. They are listed in descending priority order (the highest priority is at the top of the table). If two or more exceptions/interrupts occur at the same time, the one with the highest priority is taken. - -Exceptions always cause a trap to be taken. An interrupt will cause a trap only if enabled. Each type of interrupt has an interrupt-enable bit in the `mie` register. Interrupts are globally enable/disabled by setting the MIE bit of `mstatus` register. - -| **Exception / Interrupt** | `mcause` **interrupt bit** | `mcause` **exception code** | -| :--------------------------------------- | ----------------: | ------------------: | -| Machine external interrupt | 1 | 11 | -| Machine software interrupt | 1 | 3 | -| Machine timer interrupt | 1 | 7 | -| Illegal instruction exception | 0 | 2 | -| Instruction address-misaligned exception | 0 | 0 | -| Environment call from M-mode exception | 0 | 11 | -| Environment break exception | 0 | 3 | -| Store address-misaligned exception | 0 | 6 | -| Load address-misaligned exception | 0 | 4 | - -## Trap handling in Steel - -Exceptions and interrupts are handled by a trap handler routine stored in memory (your software must provide one). The address of the trap handler first instruction is configured using the `mtvec` register. Steel supports both direct and vectorized interrupt modes. More information on interrupt modes and configuration of the `mtvec` register can be found in [RISC-V specifications](https://riscv.org/specifications/). - -When a trap is taken, the core proceeds as follows: - -* the address of the interrupted instruction (or the instruction that encountered the exception) is saved in the `mepc` register; -* the value of the `mtval` register is set to zero; -* the value of the `mstatus` MIE bit is saved in the MPIE field and then set to zero; -* the program counter is set to the address of the trap handler first instruction. - -The **mret** instruction is used to return from traps. When executed, the core proceeds as follows: - -* the value of the `mstatus` MPIE bit is saved in the MIE field and then set to one; -* the program counter is set to the value of `mepc` register. - -## Nested interrupts capability - -The core globally disables new interrupts when takes into a trap. The trap handler can re-enable interrupts by setting the `mstatus` MIE bit to one, thus enabling nested interrupts. To return from nested traps, the trap handler must stack and manage the values of the `mepc` register in memory. Index: steelcore/docs/extra.css =================================================================== --- steelcore/docs/extra.css (revision 11) +++ steelcore/docs/extra.css (nonexistent) @@ -1,7 +0,0 @@ -th, td { - padding: 10px; -} - -table { - margin-bottom: 20px; -}

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