URL
https://opencores.org/ocsvn/suslik/suslik/trunk
Subversion Repositories suslik
Compare Revisions
- This comparison shows the changes necessary to convert path
/suslik/trunk
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/rtl/cpu.v
1,5 → 1,5
|
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr,wrspec); |
module aluplus(instr, val1, val2, valres, wrtval, cjmpinstr,cjmp,const1,retaddr,wrspec,irq_bits); |
|
input [31:0] instr, val1, val2; |
output [31:0] valres; |
8,6 → 8,7
input [31:0] const1; |
input [31:0] retaddr; |
output wrspec; |
input [15:0] irq_bits; |
|
wire [5:0] code; |
wire [31:0] valcmp; |
35,6 → 36,7
assign valres=(code==10)? val1 - val2 : 32'bz; |
assign valres=(code==11)? val1 - const1 : 32'bz; |
assign valres=wrspec ? val1 : 32'bz; |
assign valres=(code==12 && instr[15:11]==5'd2 && instr[31:24]=8'hff) ? irq_bits : 32'bz; |
assign valres=(code==13)? val1 & {16'b1111111111111111, const1[15:0]} : 32'bz; |
assign valres=(code==46) ? retaddr : 32'bz; |
assign valres=(code==14)? val1 << val2[5:0] : 32'bz; |
46,8 → 48,8
|
assign valres=wrtval | wrspec ? 32'bz : 32'b0; |
|
assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46)); |
assign wrspec=(code==12) && (instr[15:6]=10'd1); |
assign wrtval=((code<=11) || (code>=13 && code<=19) || (code==46)) || (code==12 && instr[15:11]==5'd2 && instr[31:24]=8'hff); |
assign wrspec=(code==12) && (instr[15:11]=5'd1); |
|
//flags for compare &jump |
assign {CF,valcmp}=val1 - val2; |
386,11 → 388,13
reg [31:0] irq_handler=32'hffff_fff0; |
|
wire wrspec; |
reg [31:0] sys_flags=32'b0; |
reg [15:0] irq_mask; |
|
//dataunit data0(clk,stall,stginhibit,readaddr,readdata,agureadsz,agureaden,aguwriteen,opB); |
datacache datacache0(clk,stall,stginhibit,codeMiss,dcAddr,dcDataA,busInput,opB,dcHit,dcReadEn,dcWriteEn,dcInsert,dcInitEntry,agureadsz,dcOldAddr); |
regfileint0 regf0(clk,intregwe,rA,rB,rC,rF,intregdataA,intregdataB,intregdataC,intregdataF); |
aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr,wrspec); |
aluplus alu0(instr4,opA,opB,opF,aluwrtval,alucjmpinstr,alucjmp,constBits4,retAddr,wrspec,irq_bits); |
ioinstr ioinstr0(clk,stall,stginhibit,instr4,opA,opB,ioInstrResult,wasGlobalStall,ioInstrWrtVal,ioInstrDoStall,ioInstrKeepStalling, |
ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd); |
subagu agu0(clk,stall,stginhibit,opC,instr0,instr,instr4,aguaddr,aguwrtval,agustall,agureadsz,agureaden,aguwriteen,constBits); |
545,7 → 549,7
IP2<=fetchaddr; |
multiCycleStall[1]<=multiCycleStall[0]; |
multiCycleStall[0]<=0; |
if (irq) |
if (irq&irq_mask) |
begin |
stginhibit<=5'b11110; |
codeMiss<=0; |
668,8 → 672,10
end |
else if (wrspec) |
begin |
case (instr4[31:16]) |
16'd0: irq_handler<=opF; |
case (instr4[31:24]) |
8'd0: irq_handler<=opF; |
8'd1: sys_flags<=opF; |
8'd2: irq_mask<=opF; |
endcase |
end |
end |