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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

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  • This comparison shows the changes necessary to convert path 
    /uart2bus/trunk/vhdl/rtl
    from Rev 10 to Rev 11
    ↔ Reverse comparison
  •

Rev 10 → Rev 11

/baudGen.vhd
9,9 → 9,9
-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity baudGen is
port ( clr : in std_logic; -- global reset input
/uartRx.vhd
2,9 → 2,9
-- uart receive module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
 
entity uartRx is
port ( clr : in std_logic; -- global reset input
60,7 → 60,7
elsif (rising_edge(clk)) then
if ((rxBusy = '0') and (ce1Mid = '1')) then
rxBusy <= '1';
elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1 = '1')) then
elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1Mid = '1')) then
rxBusy <= '0';
end if;
end if;
/uartTx.vhd
2,9 → 2,9
-- uart transmit module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity uartTx is
port ( clr : in std_logic; -- global reset input
/uartParser.vhd
2,9 → 2,9
-- uart parser module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
 
entity uartParser is
generic ( -- parameters
19,6 → 19,8
txData : out std_logic_vector(7 downto 0); -- data byte to transmit
newTxData : out std_logic; -- asserted to indicate that there is a new data byte for transmission
-- internal bus to register file
intReq : out std_logic; --
intGnt : in std_logic; --
intRdData : in std_logic_vector(7 downto 0); -- data read from register file
intAddress : out std_logic_vector(AW - 1 downto 0); -- address bus to register file
intWrData : out std_logic_vector(7 downto 0); -- write data to register file
105,10 → 107,12
signal addrNibble : std_logic_vector(3 downto 0); -- data nibble from received character
signal binByteCount : std_logic_vector(7 downto 0); -- binary mode byte counter
signal iIntAddress : std_logic_vector(intAddress'range); --
signal iWriteReq : std_logic; --
signal iIntWrite : std_logic; --
signal readDone : std_logic; -- internally generated read done flag
signal readDoneS : std_logic; -- sampled read done
signal readDataS : std_logic_vector(7 downto 0); -- sampled read data
signal iReadReq : std_logic; --
signal iIntRead : std_logic; --
signal txChar : std_logic_vector(7 downto 0); -- transmit byte from nibble to character conversion
signal sTxBusy : std_logic; -- sampled tx_busy for falling edge detection
356,29 → 360,37
process (clr, clk)
begin
if (clr = '1') then
iReadReq <= '0';
iIntRead <= '0';
iWriteReq <= '0';
iIntWrite <= '0';
intWrData <= (others => '0');
elsif (rising_edge(clk)) then
if ((mainSm = mainAddr) and (writeOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
iIntWrite <= '1';
iWriteReq <= '1';
intWrData <= dataParam;
-- binary extension mode
elsif ((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) then
iWriteReq <= '1';
intWrData <= rxData;
elsif ((intGnt = '1') and (iWriteReq = '1')) then
iWriteReq <= '0';
iIntWrite <= '1';
intWrData <= rxData;
else
iIntWrite <= '0';
end if;
if ((mainSm = mainAddr) and (readOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
iIntRead <= '1';
iReadReq <= '1';
-- binary extension
elsif ((mainSm = mainBinLen) and (binReadOp = '1') and (newRxData = '1')) then
-- the first read request is issued on reception of the length byte
iIntRead <= '1';
iReadReq <= '1';
elsif ((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) then
-- the next read requests are issued after the previous read value was transmitted and
-- this is not the last byte to be read.
iReadReq <= '1';
elsif ((intGnt = '1') and (iReadReq = '1')) then
iReadReq <= '0';
iIntRead <= '1';
else
iIntRead <= '0';
559,4 → 571,6
intAddress <= iIntAddress;
intWrite <= iIntWrite;
intRead <= iIntRead;
intReq <= '1' when (iReadReq = '1') else
'1' when (iWriteReq = '1') else '0';
end Behavioral;
/uart2BusTop.vhd
2,67 → 2,41
-- uart to internal bus top module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.uart2BusTop_pkg.all;
 
entity uart2BusTop is
generic ( AW : integer := 8);
port ( -- global signals
clr : in STD_LOGIC; -- global reset input
clk : in STD_LOGIC; -- global clock input
clr : in STD_LOGIC; -- global reset input
clk : in STD_LOGIC; -- global clock input
-- uart serial signals
serIn : in STD_LOGIC; -- serial data input
serOut : out STD_LOGIC; -- serial data output
serIn : in STD_LOGIC; -- serial data input
serOut : out STD_LOGIC; -- serial data output
-- internal bus to register file
intRdData : in STD_LOGIC_VECTOR (7 downto 0); -- data read from register file
intAddress : out STD_LOGIC_VECTOR (AW - 1 downto 0); -- address bus to register file
intWrData : out STD_LOGIC_VECTOR (7 downto 0); -- write data to register file
intWrite : out STD_LOGIC; -- write control to register file
intRead : out STD_LOGIC); -- read control to register file
intAccessReq : out std_logic; --
intAccessGnt : in std_logic; --
intRdData : in STD_LOGIC_VECTOR (7 downto 0); -- data read from register file
intAddress : out STD_LOGIC_VECTOR (AW - 1 downto 0); -- address bus to register file
intWrData : out STD_LOGIC_VECTOR (7 downto 0); -- write data to register file
intWrite : out STD_LOGIC; -- write control to register file
intRead : out STD_LOGIC); -- read control to register file
end uart2BusTop;
 
architecture Behavioral of uart2BusTop is
 
component uartTop
port ( clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
serOut : out std_logic;
txBusy : out std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic;
baudClk : out std_logic);
end component;
 
component uartParser
generic ( AW : integer := 8);
port ( clr : in std_logic;
clk : in std_logic;
txBusy : in std_logic;
rxData : in std_logic_vector(7 downto 0);
newRxData : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
txData : out std_logic_vector(7 downto 0);
newTxData : out std_logic;
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic);
end component;
 
-- baud rate configuration, see baudGen.vhd for more details.
-- baud rate generator parameters for 115200 baud on 25MHz clock
constant baudFreq : std_logic_vector(11 downto 0) := x"480";
constant baudLimit : std_logic_vector(15 downto 0) := x"3889";
signal txData : std_logic_vector(7 downto 0); -- data byte to transmit
signal newTxData : std_logic; -- asserted to indicate that there is a new data byte for transmission
signal txBusy : std_logic; -- signs that transmitter is busy
signal rxData : std_logic_vector(7 downto 0); -- data byte received
signal newRxData : std_logic; -- signs that a new byte was received
constant baudFreq : std_logic_vector(11 downto 0) := x"480";
constant baudLimit : std_logic_vector(15 downto 0) := x"3889";
signal txData : std_logic_vector(7 downto 0); -- data byte to transmit
signal newTxData : std_logic; -- asserted to indicate that there is a new data byte for transmission
signal txBusy : std_logic; -- signs that transmitter is busy
signal rxData : std_logic_vector(7 downto 0); -- data byte received
signal newRxData : std_logic; -- signs that a new byte was received
begin
-- uart top module instance
93,8 → 67,11
intRdData => intRdData,
txData => txData,
newTxData => newTxData,
intReq => intAccessReq,
intGnt => intAccessGnt,
intAddress => intAddress,
intWrData => intWrData,
intWrite => intWrite,
intRead => intRead);
 
end Behavioral;
/uart2BusTop_pkg.vhd
0,0 → 1,90
library ieee;
use ieee.std_logic_1164.all;
 
package uart2BusTop_pkg is
 
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
end component;
 
component uartTx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
serOut : out std_logic;
txBusy : out std_logic);
end component;
 
component uartRx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
serIn : in std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic);
end component;
 
component uartTop
port ( clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
serOut : out std_logic;
txBusy : out std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic;
baudClk : out std_logic);
end component;
 
component uartParser
generic ( AW : integer := 8);
port ( clr : in std_logic;
clk : in std_logic;
txBusy : in std_logic;
rxData : in std_logic_vector(7 downto 0);
newRxData : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
txData : out std_logic_vector(7 downto 0);
newTxData : out std_logic;
intReq : out std_logic;
intGnt : in std_logic;
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic);
end component;
 
component uart2BusTop
generic
(
AW : integer := 8
);
port
(
clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
serOut : out std_logic;
intAccessReq : out std_logic;
intAccessGnt : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic
);
end component;
 
end uart2BusTop_pkg;
/uartTop.vhd
2,9 → 2,12
-- uart top level module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.uart2BusTop_pkg.all;
 
entity uartTop is
port ( -- global signals
clr : in std_logic; -- global reset input
26,36 → 29,6
 
architecture Behavioral of uartTop is
 
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
end component;
 
component uartTx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
serOut : out std_logic;
txBusy : out std_logic);
end component;
 
component uartRx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
serIn : in std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic);
end component;
 
signal ce16 : std_logic; -- clock enable at bit rate
 
begin

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