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Rev 10 → Rev 11

/vhdl/test.txt File deleted \ No newline at end of file
/vhdl/test.bin Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/vhdl/test.bin
vhdl/test.bin Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: vhdl/bench/regFileModel.vhd =================================================================== --- vhdl/bench/regFileModel.vhd (revision 10) +++ vhdl/bench/regFileModel.vhd (nonexistent) @@ -1,51 +0,0 @@ ------------------------------------------------------------------------------------------ --- register file model as a simple memory --- ------------------------------------------------------------------------------------------ -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.std_logic_unsigned.all; - -entity regFileModel is - port ( -- global signals - clr : in std_logic; -- global reset input - clk : in std_logic; -- global clock input - -- internal bus to register file - intAddress : in std_logic_vector(7 downto 0); -- address bus to register file - intWrData : in std_logic_vector(7 downto 0); -- write data to register file - intWrite : in std_logic; -- write control to register file - intRead : in std_logic; -- read control to register file - intRdData : out std_logic_vector(7 downto 0)); -- data read from register file -end regFileModel; - -architecture Behavioral of regFileModel is - - type RAM is array (integer range <>)of std_logic_vector (7 downto 0); - signal regFile : RAM (0 to 255); - - begin - -- register file write - process (clr, clk) - begin - if (clr = '1') then - for index in 0 to 255 loop - regFile(index) <= (others => '0'); - end loop; - elsif (rising_edge(clk)) then - if (intWrite = '1') then - regFile(conv_integer(intAddress)) <= intWrData; - end if; - end if; - end process; - -- register file read - process (clr, clk) - begin - if (clr = '1') then - intRdData <= (others => '0'); - elsif (rising_edge(clk)) then - if (intRead = '1') then - intRdData <= regFile(conv_integer(intAddress)); - end if; - end if; - end process; - end Behavioral; Index: vhdl/bench/helpers/helpers_pkg.vhd =================================================================== --- vhdl/bench/helpers/helpers_pkg.vhd (nonexistent) +++ vhdl/bench/helpers/helpers_pkg.vhd (revision 11) @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +package helpers_pkg is + + component regFileModel + port + ( + clr : in std_logic; + clk : in std_logic; + intAddress : in std_logic_vector(7 downto 0); + intWrData : in std_logic_vector(7 downto 0); + intWrite : in std_logic; + intRead : in std_logic; + intRdData : out std_logic_vector(7 downto 0)); + end component; + +end helpers_pkg; Index: vhdl/bench/helpers/regFileModel.vhd =================================================================== --- vhdl/bench/helpers/regFileModel.vhd (nonexistent) +++ vhdl/bench/helpers/regFileModel.vhd (revision 11) @@ -0,0 +1,51 @@ +----------------------------------------------------------------------------------------- +-- register file model as a simple memory +-- +----------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; + +entity regFileModel is + port ( -- global signals + clr : in std_logic; -- global reset input + clk : in std_logic; -- global clock input + -- internal bus to register file + intAddress : in std_logic_vector(7 downto 0); -- address bus to register file + intWrData : in std_logic_vector(7 downto 0); -- write data to register file + intWrite : in std_logic; -- write control to register file + intRead : in std_logic; -- read control to register file + intRdData : out std_logic_vector(7 downto 0)); -- data read from register file +end regFileModel; + +architecture Behavioral of regFileModel is + + type RAM is array (integer range <>)of std_logic_vector (7 downto 0); + signal regFile : RAM (0 to 255); + + begin + -- register file write + process (clr, clk) + begin + if (clr = '1') then + for index in 0 to 255 loop + regFile(index) <= (others => '0'); + end loop; + elsif (rising_edge(clk)) then + if (intWrite = '1') then + regFile(conv_integer(intAddress)) <= intWrData; + end if; + end if; + end process; + -- register file read + process (clr, clk) + begin + if (clr = '1') then + intRdData <= (others => '0'); + elsif (rising_edge(clk)) then + if (intRead = '1') then + intRdData <= regFile(conv_integer(intAddress)); + end if; + end if; + end process; + end Behavioral; Index: vhdl/bench/uart2BusTop_bin_tb.vhd =================================================================== --- vhdl/bench/uart2BusTop_bin_tb.vhd (revision 10) +++ vhdl/bench/uart2BusTop_bin_tb.vhd (revision 11) @@ -3,6 +3,7 @@ -- ----------------------------------------------------------------------------------------- use std.textio.all; + library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; @@ -9,6 +10,10 @@ use ieee.numeric_std.all; use ieee.std_logic_textio.all; +library work; +use work.uart2BusTop_pkg.all; +use work.helpers_pkg.all; + ----------------------------------------------------------------------------------------- -- test bench implementation entity uart2BusTop_bin_tb is @@ -50,37 +55,6 @@ wait for stopbit * bitTime; end procedure; - component uart2BusTop - generic - ( - AW : integer := 8 - ); - port - ( - clr : in std_logic; - clk : in std_logic; - serIn : in std_logic; - serOut : out std_logic; - intRdData : in std_logic_vector(7 downto 0); - intAddress : out std_logic_vector(AW - 1 downto 0); - intWrData : out std_logic_vector(7 downto 0); - intWrite : out std_logic; - intRead : out std_logic - ); - end component; - - component regFileModel - port - ( - clr : in std_logic; - clk : in std_logic; - intAddress : in std_logic_vector(7 downto 0); - intWrData : in std_logic_vector(7 downto 0); - intWrite : in std_logic; - intRead : in std_logic; - intRdData : out std_logic_vector(7 downto 0)); - end component; - -- Inputs signal clr : std_logic := '0'; signal clk : std_logic := '0'; @@ -95,6 +69,9 @@ signal intRead : std_logic; signal recvData : std_logic_vector(7 downto 0); signal newRxData : std_logic; + signal intAccessReq : std_logic; + signal intAccessGnt : std_logic; + signal counter : integer; constant BAUD_115200 : real := 115200.0; constant BAUD_38400 : real := 38400.0; @@ -127,6 +104,8 @@ clk => clk, serIn => serIn, serOut => serOut, + intAccessReq => intAccessReq, + intAccessGnt => intAccessGnt, intRdData => intRdData, intAddress => intAddress, intWrData => intWrData, @@ -145,6 +124,27 @@ intWrite => intWrite, intRead => intRead); + -- just to create a delay similar to simulate a bus arbitrer + process (clr, clk) + begin + if (clr = '1') then + intAccessGnt <= '0'; + counter <= 0; + elsif (rising_edge(clk)) then + if (counter = 0) then + if ((intAccessReq = '1') and (intAccessGnt = '0')) then + counter <= 500; + end if; + intAccessGnt <= '0'; + elsif (counter = 1) then + counter <= counter - 1; + intAccessGnt <= '1'; + else + counter <= counter - 1; + end if; + end if; + end process; + -- clock generator - 25MHz clock process begin @@ -184,7 +184,7 @@ process type dataFile is file of character; - file testBinaryFile : dataFile open READ_MODE is "test.bin"; + file testBinaryFile : dataFile open READ_MODE is "../test.bin"; variable charBuf : character; variable fileLength : integer; variable byteIndex : integer;
/vhdl/bench/uart2BusTop_txt_tb.vhd
1,211 → 1,212
-----------------------------------------------------------------------------------------
-- uart test bench
--
-----------------------------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
 
-----------------------------------------------------------------------------------------
-- test bench implementation
entity uart2BusTop_txt_tb is
end uart2BusTop_txt_tb;
 
architecture behavior of uart2BusTop_txt_tb is
 
procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is
 
variable shiftreg : std_logic_vector(7 downto 0);
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length));
txd <= '0';
wait for bitTime;
for index in 0 to bitnumber loop
txd <= shiftreg(index);
wait for bitTime;
end loop;
txd <= '1';
wait for stopbit * bitTime;
end procedure;
 
procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is
 
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
wait until (rxd = '0');
wait for bitTime / 2;
wait for bitTime;
for index in 0 to bitnumber loop
data <= rxd & data(7 downto 1);
wait for bitTime;
end loop;
wait for stopbit * bitTime;
end procedure;
 
component uart2BusTop
generic
(
AW : integer := 8
);
port
(
clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
serOut : out std_logic;
intRdData : in std_logic_vector(7 downto 0);
intAddress : out std_logic_vector(7 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic
);
end component;
 
component regFileModel
port
(
clr : in std_logic;
clk : in std_logic;
intAddress : in std_logic_vector(7 downto 0);
intWrData : in std_logic_vector(7 downto 0);
intWrite : in std_logic;
intRead : in std_logic;
intRdData : out std_logic_vector(7 downto 0));
end component;
 
-- Inputs
signal clr : std_logic := '0';
signal clk : std_logic := '0';
signal serIn : std_logic := '0';
signal intRdData : std_logic_vector(7 downto 0) := (others => '0');
 
-- Outputs
signal serOut : std_logic;
signal intAddress : std_logic_vector(7 downto 0);
signal intWrData : std_logic_vector(7 downto 0);
signal intWrite : std_logic;
signal intRead : std_logic;
signal recvData : std_logic_vector(7 downto 0);
signal newRxData : std_logic;
constant BAUD_115200 : real := 115200.0;
constant BAUD_38400 : real := 38400.0;
constant BAUD_28800 : real := 28800.0;
constant BAUD_19200 : real := 19200.0;
constant BAUD_9600 : real := 9600.0;
constant BAUD_4800 : real := 4800.0;
constant BAUD_2400 : real := 2400.0;
constant BAUD_1200 : real := 1200.0;
constant NSTOPS_1 : real := 1.0;
constant NSTOPS_1_5 : real := 1.5;
constant NSTOPS_2 : real := 2.0;
constant PARITY_NONE : integer := 0;
constant PARITY_EVEN : integer := 1;
constant PARITY_ODD : integer := 2;
constant PARITY_MARK : integer := 3;
constant PARITY_SPACE : integer := 4;
constant NBITS_7 : integer := 6;
constant NBITS_8 : integer := 7;
begin
-- Instantiate the Unit Under Test (UUT)
uut : uart2BusTop
port map
(
clr => clr,
clk => clk,
serIn => serIn,
serOut => serOut,
intRdData => intRdData,
intAddress => intAddress,
intWrData => intWrData,
intWrite => intWrite,
intRead => intRead
);
 
rfm : regFileModel
port map
(
clr => clr,
clk => clk,
intRdData => intRdData,
intAddress => intAddress,
intWrData => intWrData,
intWrite => intWrite,
intRead => intRead);
 
-- clock generator - 25MHz clock
process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
 
-- reset process definitions
process
begin
clr <= '1';
wait for 40 ns;
clr <= '0';
wait;
end process;
 
--------------------------------------------------------------------
-- test bench receiver
process
 
begin
newRxData <= '0';
recvData <= (others => '0');
wait until (clr = '0');
loop
recvSerial(serOut, BAUD_115200, PARITY_NONE, NSTOPS_1, NBITS_8, 0.0, recvData);
newRxData <= '1';
wait for 25 ns;
newRxData <= '0';
end loop;
end process;
 
--------------------------------------------------------------------
-- uart transmit - test bench control
process
 
type dataFile is file of character;
file testTextFile : dataFile open READ_MODE is "test.txt";
variable charBuf : character;
variable data : integer;
 
begin
-- default value of serial output
serIn <= '1';
-- text mode simulation
write(tempLine, string'("Starting text mode simulation"));
writeline(output, tempLine);
wait until (clr = '0');
wait until (rising_edge(clk));
for index in 0 to 99 loop
wait until (rising_edge(clk));
end loop;
while not endfile(testTextFile) loop
-- transmit the byte in the command file one by one
read(testTextFile, charBuf);
data := character'pos(charBuf);
sendSerial(data, BAUD_115200, PARITY_NONE, NSTOPS_1, NBITS_8, 0.0, serIn);
wait for 800 us;
end loop;
wait;
end process;
end;
-----------------------------------------------------------------------------------------
-- uart test bench
--
-----------------------------------------------------------------------------------------
use std.textio.all;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
 
library work;
use work.uart2BusTop_pkg.all;
use work.helpers_pkg.all;
 
-----------------------------------------------------------------------------------------
-- test bench implementation
entity uart2BusTop_txt_tb is
end uart2BusTop_txt_tb;
 
architecture behavior of uart2BusTop_txt_tb is
 
procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is
 
variable shiftreg : std_logic_vector(7 downto 0);
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length));
txd <= '0';
wait for bitTime;
for index in 0 to bitnumber loop
txd <= shiftreg(index);
wait for bitTime;
end loop;
txd <= '1';
wait for stopbit * bitTime;
end procedure;
 
procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is
 
variable bitTime : time;
 
begin
bitTime := 1000 ms / (baud + baud * baudError / 100.0);
wait until (rxd = '0');
wait for bitTime / 2;
wait for bitTime;
for index in 0 to bitnumber loop
data <= rxd & data(7 downto 1);
wait for bitTime;
end loop;
wait for stopbit * bitTime;
end procedure;
 
-- Inputs
signal clr : std_logic := '0';
signal clk : std_logic := '0';
signal serIn : std_logic := '0';
signal intRdData : std_logic_vector(7 downto 0) := (others => '0');
 
-- Outputs
signal serOut : std_logic;
signal intAddress : std_logic_vector(7 downto 0);
signal intWrData : std_logic_vector(7 downto 0);
signal intWrite : std_logic;
signal intRead : std_logic;
signal recvData : std_logic_vector(7 downto 0);
signal newRxData : std_logic;
signal intAccessReq : std_logic;
signal intAccessGnt : std_logic;
signal counter : integer;
constant BAUD_115200 : real := 115200.0;
constant BAUD_38400 : real := 38400.0;
constant BAUD_28800 : real := 28800.0;
constant BAUD_19200 : real := 19200.0;
constant BAUD_9600 : real := 9600.0;
constant BAUD_4800 : real := 4800.0;
constant BAUD_2400 : real := 2400.0;
constant BAUD_1200 : real := 1200.0;
constant NSTOPS_1 : real := 1.0;
constant NSTOPS_1_5 : real := 1.5;
constant NSTOPS_2 : real := 2.0;
constant PARITY_NONE : integer := 0;
constant PARITY_EVEN : integer := 1;
constant PARITY_ODD : integer := 2;
constant PARITY_MARK : integer := 3;
constant PARITY_SPACE : integer := 4;
constant NBITS_7 : integer := 6;
constant NBITS_8 : integer := 7;
begin
-- Instantiate the Unit Under Test (UUT)
uut : uart2BusTop
port map
(
clr => clr,
clk => clk,
serIn => serIn,
serOut => serOut,
intAccessReq => intAccessReq,
intAccessGnt => intAccessGnt,
intRdData => intRdData,
intAddress => intAddress,
intWrData => intWrData,
intWrite => intWrite,
intRead => intRead
);
 
rfm : regFileModel
port map
(
clr => clr,
clk => clk,
intRdData => intRdData,
intAddress => intAddress,
intWrData => intWrData,
intWrite => intWrite,
intRead => intRead);
 
-- just to create a delay similar to simulate a bus arbitrer
process (clr, clk)
begin
if (clr = '1') then
intAccessGnt <= '0';
counter <= 0;
elsif (rising_edge(clk)) then
if (counter = 0) then
if ((intAccessReq = '1') and (intAccessGnt = '0')) then
counter <= 500;
end if;
intAccessGnt <= '0';
elsif (counter = 1) then
counter <= counter - 1;
intAccessGnt <= '1';
else
counter <= counter - 1;
end if;
end if;
end process;
 
-- clock generator - 25MHz clock
process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
 
-- reset process definitions
process
begin
clr <= '1';
wait for 40 ns;
clr <= '0';
wait;
end process;
 
--------------------------------------------------------------------
-- test bench receiver
process
 
begin
newRxData <= '0';
recvData <= (others => '0');
wait until (clr = '0');
loop
recvSerial(serOut, BAUD_115200, PARITY_NONE, NSTOPS_1, NBITS_8, 0.0, recvData);
newRxData <= '1';
wait for 25 ns;
newRxData <= '0';
end loop;
end process;
 
--------------------------------------------------------------------
-- uart transmit - test bench control
process
 
type dataFile is file of character;
file testTextFile : dataFile open READ_MODE is "../test.txt";
variable charBuf : character;
variable data : integer;
variable tempLine : line;
 
begin
-- default value of serial output
serIn <= '1';
-- text mode simulation
write(tempLine, string'("Starting text mode simulation"));
writeline(output, tempLine);
wait until (clr = '0');
wait until (rising_edge(clk));
for index in 0 to 99 loop
wait until (rising_edge(clk));
end loop;
while not endfile(testTextFile) loop
-- transmit the byte in the command file one by one
read(testTextFile, charBuf);
data := character'pos(charBuf);
sendSerial(data, BAUD_115200, PARITY_NONE, NSTOPS_1, NBITS_8, 0.0, serIn);
wait for 800 us;
end loop;
wait;
end process;
end;
/vhdl/bench
vhdl/bench Property changes : Added: svn:ignore ## -0,0 +1 ## +*.bak Index: vhdl/rtl/baudGen.vhd =================================================================== --- vhdl/rtl/baudGen.vhd (revision 10) +++ vhdl/rtl/baudGen.vhd (revision 11) @@ -9,9 +9,9 @@ -- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq -- ----------------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; entity baudGen is port ( clr : in std_logic; -- global reset input
/vhdl/rtl/uartRx.vhd
2,9 → 2,9
-- uart receive module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
 
entity uartRx is
port ( clr : in std_logic; -- global reset input
60,7 → 60,7
elsif (rising_edge(clk)) then
if ((rxBusy = '0') and (ce1Mid = '1')) then
rxBusy <= '1';
elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1 = '1')) then
elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1Mid = '1')) then
rxBusy <= '0';
end if;
end if;
/vhdl/rtl/uartTx.vhd
2,9 → 2,9
-- uart transmit module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity uartTx is
port ( clr : in std_logic; -- global reset input
/vhdl/rtl/uartParser.vhd
2,9 → 2,9
-- uart parser module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
 
entity uartParser is
generic ( -- parameters
19,6 → 19,8
txData : out std_logic_vector(7 downto 0); -- data byte to transmit
newTxData : out std_logic; -- asserted to indicate that there is a new data byte for transmission
-- internal bus to register file
intReq : out std_logic; --
intGnt : in std_logic; --
intRdData : in std_logic_vector(7 downto 0); -- data read from register file
intAddress : out std_logic_vector(AW - 1 downto 0); -- address bus to register file
intWrData : out std_logic_vector(7 downto 0); -- write data to register file
105,10 → 107,12
signal addrNibble : std_logic_vector(3 downto 0); -- data nibble from received character
signal binByteCount : std_logic_vector(7 downto 0); -- binary mode byte counter
signal iIntAddress : std_logic_vector(intAddress'range); --
signal iWriteReq : std_logic; --
signal iIntWrite : std_logic; --
signal readDone : std_logic; -- internally generated read done flag
signal readDoneS : std_logic; -- sampled read done
signal readDataS : std_logic_vector(7 downto 0); -- sampled read data
signal iReadReq : std_logic; --
signal iIntRead : std_logic; --
signal txChar : std_logic_vector(7 downto 0); -- transmit byte from nibble to character conversion
signal sTxBusy : std_logic; -- sampled tx_busy for falling edge detection
356,29 → 360,37
process (clr, clk)
begin
if (clr = '1') then
iReadReq <= '0';
iIntRead <= '0';
iWriteReq <= '0';
iIntWrite <= '0';
intWrData <= (others => '0');
elsif (rising_edge(clk)) then
if ((mainSm = mainAddr) and (writeOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
iIntWrite <= '1';
iWriteReq <= '1';
intWrData <= dataParam;
-- binary extension mode
elsif ((mainSm = mainBinData) and (binWriteOp = '1') and (newRxData = '1')) then
iWriteReq <= '1';
intWrData <= rxData;
elsif ((intGnt = '1') and (iWriteReq = '1')) then
iWriteReq <= '0';
iIntWrite <= '1';
intWrData <= rxData;
else
iIntWrite <= '0';
end if;
if ((mainSm = mainAddr) and (readOp = '1') and (newRxData = '1') and (dataInHexRange = '0')) then
iIntRead <= '1';
iReadReq <= '1';
-- binary extension
elsif ((mainSm = mainBinLen) and (binReadOp = '1') and (newRxData = '1')) then
-- the first read request is issued on reception of the length byte
iIntRead <= '1';
iReadReq <= '1';
elsif ((binReadOp = '1') and (txEndP = '1') and (binLastByte = '0')) then
-- the next read requests are issued after the previous read value was transmitted and
-- this is not the last byte to be read.
iReadReq <= '1';
elsif ((intGnt = '1') and (iReadReq = '1')) then
iReadReq <= '0';
iIntRead <= '1';
else
iIntRead <= '0';
559,4 → 571,6
intAddress <= iIntAddress;
intWrite <= iIntWrite;
intRead <= iIntRead;
intReq <= '1' when (iReadReq = '1') else
'1' when (iWriteReq = '1') else '0';
end Behavioral;
/vhdl/rtl/uart2BusTop.vhd
2,67 → 2,41
-- uart to internal bus top module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.uart2BusTop_pkg.all;
 
entity uart2BusTop is
generic ( AW : integer := 8);
port ( -- global signals
clr : in STD_LOGIC; -- global reset input
clk : in STD_LOGIC; -- global clock input
clr : in STD_LOGIC; -- global reset input
clk : in STD_LOGIC; -- global clock input
-- uart serial signals
serIn : in STD_LOGIC; -- serial data input
serOut : out STD_LOGIC; -- serial data output
serIn : in STD_LOGIC; -- serial data input
serOut : out STD_LOGIC; -- serial data output
-- internal bus to register file
intRdData : in STD_LOGIC_VECTOR (7 downto 0); -- data read from register file
intAddress : out STD_LOGIC_VECTOR (AW - 1 downto 0); -- address bus to register file
intWrData : out STD_LOGIC_VECTOR (7 downto 0); -- write data to register file
intWrite : out STD_LOGIC; -- write control to register file
intRead : out STD_LOGIC); -- read control to register file
intAccessReq : out std_logic; --
intAccessGnt : in std_logic; --
intRdData : in STD_LOGIC_VECTOR (7 downto 0); -- data read from register file
intAddress : out STD_LOGIC_VECTOR (AW - 1 downto 0); -- address bus to register file
intWrData : out STD_LOGIC_VECTOR (7 downto 0); -- write data to register file
intWrite : out STD_LOGIC; -- write control to register file
intRead : out STD_LOGIC); -- read control to register file
end uart2BusTop;
 
architecture Behavioral of uart2BusTop is
 
component uartTop
port ( clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
serOut : out std_logic;
txBusy : out std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic;
baudClk : out std_logic);
end component;
 
component uartParser
generic ( AW : integer := 8);
port ( clr : in std_logic;
clk : in std_logic;
txBusy : in std_logic;
rxData : in std_logic_vector(7 downto 0);
newRxData : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
txData : out std_logic_vector(7 downto 0);
newTxData : out std_logic;
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic);
end component;
 
-- baud rate configuration, see baudGen.vhd for more details.
-- baud rate generator parameters for 115200 baud on 25MHz clock
constant baudFreq : std_logic_vector(11 downto 0) := x"480";
constant baudLimit : std_logic_vector(15 downto 0) := x"3889";
signal txData : std_logic_vector(7 downto 0); -- data byte to transmit
signal newTxData : std_logic; -- asserted to indicate that there is a new data byte for transmission
signal txBusy : std_logic; -- signs that transmitter is busy
signal rxData : std_logic_vector(7 downto 0); -- data byte received
signal newRxData : std_logic; -- signs that a new byte was received
constant baudFreq : std_logic_vector(11 downto 0) := x"480";
constant baudLimit : std_logic_vector(15 downto 0) := x"3889";
signal txData : std_logic_vector(7 downto 0); -- data byte to transmit
signal newTxData : std_logic; -- asserted to indicate that there is a new data byte for transmission
signal txBusy : std_logic; -- signs that transmitter is busy
signal rxData : std_logic_vector(7 downto 0); -- data byte received
signal newRxData : std_logic; -- signs that a new byte was received
begin
-- uart top module instance
93,8 → 67,11
intRdData => intRdData,
txData => txData,
newTxData => newTxData,
intReq => intAccessReq,
intGnt => intAccessGnt,
intAddress => intAddress,
intWrData => intWrData,
intWrite => intWrite,
intRead => intRead);
 
end Behavioral;
/vhdl/rtl/uart2BusTop_pkg.vhd
0,0 → 1,90
library ieee;
use ieee.std_logic_1164.all;
 
package uart2BusTop_pkg is
 
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
end component;
 
component uartTx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
serOut : out std_logic;
txBusy : out std_logic);
end component;
 
component uartRx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
serIn : in std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic);
end component;
 
component uartTop
port ( clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
serOut : out std_logic;
txBusy : out std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic;
baudClk : out std_logic);
end component;
 
component uartParser
generic ( AW : integer := 8);
port ( clr : in std_logic;
clk : in std_logic;
txBusy : in std_logic;
rxData : in std_logic_vector(7 downto 0);
newRxData : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
txData : out std_logic_vector(7 downto 0);
newTxData : out std_logic;
intReq : out std_logic;
intGnt : in std_logic;
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic);
end component;
 
component uart2BusTop
generic
(
AW : integer := 8
);
port
(
clr : in std_logic;
clk : in std_logic;
serIn : in std_logic;
serOut : out std_logic;
intAccessReq : out std_logic;
intAccessGnt : in std_logic;
intRdData : in std_logic_vector(7 downto 0);
intAddress : out std_logic_vector(AW - 1 downto 0);
intWrData : out std_logic_vector(7 downto 0);
intWrite : out std_logic;
intRead : out std_logic
);
end component;
 
end uart2BusTop_pkg;
/vhdl/rtl/uartTop.vhd
2,9 → 2,12
-- uart top level module
--
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.uart2BusTop_pkg.all;
 
entity uartTop is
port ( -- global signals
clr : in std_logic; -- global reset input
26,36 → 29,6
 
architecture Behavioral of uartTop is
 
component baudGen
port (
clr : in std_logic;
clk : in std_logic;
baudFreq : in std_logic_vector(11 downto 0);
baudLimit : in std_logic_vector(15 downto 0);
ce16 : out std_logic);
end component;
 
component uartTx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
txData : in std_logic_vector(7 downto 0);
newTxData : in std_logic;
serOut : out std_logic;
txBusy : out std_logic);
end component;
 
component uartRx
port (
clr : in std_logic;
clk : in std_logic;
ce16 : in std_logic;
serIn : in std_logic;
rxData : out std_logic_vector(7 downto 0);
newRxData : out std_logic);
end component;
 
signal ce16 : std_logic; -- clock enable at bit rate
 
begin
/vhdl/sim/test.bin Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/vhdl/sim/test.bin
vhdl/sim/test.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: vhdl/sim/modelsim/uart2bus_txt_sim.tcl =================================================================== --- vhdl/sim/modelsim/uart2bus_txt_sim.tcl (nonexistent) +++ vhdl/sim/modelsim/uart2bus_txt_sim.tcl (revision 11) @@ -0,0 +1,37 @@ +set prj_home "../.." +set tb_home "$prj_home/bench" +set src_home "$prj_home/rtl" +set sim_home "$prj_home/sim/modelsim" +set wave_file "wave_uart2bus_txt.do" +set time "50 ms" + +transcript file "" +transcript file $sim_home/transcript.log + +if {[file exists $sim_home/work]} { + file delete -force $sim_home/work +} +vlib $sim_home/work +vmap work $sim_home/work + +vcom -work work $src_home/uart2BusTop_pkg.vhd +vcom -work work $src_home/uartTx.vhd +vcom -work work $src_home/uartRx.vhd +vcom -work work $src_home/baudGen.vhd +vcom -work work $src_home/uartTop.vhd +vcom -work work $src_home/uartParser.vhd +vcom -work work $src_home/uart2BusTop.vhd + +vcom -work work $tb_home/helpers/helpers_pkg.vhd +vcom -work work $tb_home/helpers/regFileModel.vhd +vcom -work work $tb_home/uart2BusTop_txt_tb.vhd + +onbreak {resume} + +vsim -voptargs=+acc work.uart2BusTop_txt_tb(behavior) + +do $sim_home/$wave_file + +run $time + +transcript file "" \ No newline at end of file Index: vhdl/sim/modelsim/wave_uart2bus_bin.do =================================================================== --- vhdl/sim/modelsim/wave_uart2bus_bin.do (nonexistent) +++ vhdl/sim/modelsim/wave_uart2bus_bin.do (revision 11) @@ -0,0 +1,63 @@ +onerror {resume} +virtual type { \ +Idle\ +HiNib\ +{0x4 LoNib}\ +{0x5 CharCR}\ +{0x6 CharLF}\ +{default undefined_state}\ +} vt_tx +virtual type { \ +Idle\ +White1\ +Data\ +White2\ +Addr\ +Eol\ +{0x8 BinCmd}\ +{0x9 BinAdrh}\ +{0xa BinAdrl}\ +{0xb BinLen}\ +{0xc BinData}\ +{default undefined_state}\ +} vt_main +quietly virtual signal -install /uart2bustop_bin_tb/uut/up {/uart2bustop_bin_tb/uut/up/mainsm } vs_main +quietly virtual signal -install /uart2bustop_bin_tb/uut/up {/uart2bustop_bin_tb/uut/up/txsm } vs_tx +quietly virtual function -install /uart2bustop_bin_tb/uut/up -env /uart2bustop_bin_tb { (vt_main) /uart2bustop_bin_tb/uut/up/vs_main} vf_main +quietly virtual function -install /uart2bustop_bin_tb/uut/up -env /uart2bustop_bin_tb { (vt_tx) /uart2bustop_bin_tb/uut/up/vs_tx} vf_tx +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {global signals} +add wave -noupdate -format Logic /uart2bustop_bin_tb/clr +add wave -noupdate -format Logic /uart2bustop_bin_tb/clk +add wave -noupdate -divider {UART serial signals} +add wave -noupdate -format Logic /uart2bustop_bin_tb/serin +add wave -noupdate -format Logic /uart2bustop_bin_tb/serout +add wave -noupdate -divider {Internal bus to register file} +add wave -noupdate -format Logic /uart2bustop_bin_tb/intaccessreq +add wave -noupdate -format Logic /uart2bustop_bin_tb/intaccessgnt +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_bin_tb/intrddata +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_bin_tb/intaddress +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_bin_tb/intwrdata +add wave -noupdate -format Logic /uart2bustop_bin_tb/intwrite +add wave -noupdate -format Logic /uart2bustop_bin_tb/intread +add wave -noupdate -divider Debug +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_bin_tb/recvdata +add wave -noupdate -format Logic /uart2bustop_bin_tb/newrxdata +add wave -noupdate -format Literal /uart2bustop_bin_tb/uut/up/vf_main +add wave -noupdate -format Literal /uart2bustop_bin_tb/uut/up/vf_tx +TreeUpdate [SetDefaultTree] +configure wave -namecolwidth 200 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {2625 us} Index: vhdl/sim/modelsim/uart2bus_txt_sim.bat =================================================================== --- vhdl/sim/modelsim/uart2bus_txt_sim.bat (nonexistent) +++ vhdl/sim/modelsim/uart2bus_txt_sim.bat (revision 11) @@ -0,0 +1,3 @@ +@Echo Off +Rem Modify the below vsim.exe path to run the test bench +C:\Modeltech_xe_starter\win32xoem\vsim.exe -do uart2bus_txt_sim.tcl Index: vhdl/sim/modelsim/uart2bus_bin_sim.tcl =================================================================== --- vhdl/sim/modelsim/uart2bus_bin_sim.tcl (nonexistent) +++ vhdl/sim/modelsim/uart2bus_bin_sim.tcl (revision 11) @@ -0,0 +1,37 @@ +set prj_home "../.." +set tb_home "$prj_home/bench" +set src_home "$prj_home/rtl" +set sim_home "$prj_home/sim/modelsim" +set wave_file "wave_uart2bus_bin.do" +set time "2500 us" + +transcript file "" +transcript file $sim_home/transcript.log + +if {[file exists $sim_home/work]} { + file delete -force $sim_home/work +} +vlib $sim_home/work +vmap work $sim_home/work + +vcom -work work $src_home/uart2BusTop_pkg.vhd +vcom -work work $src_home/uartTx.vhd +vcom -work work $src_home/uartRx.vhd +vcom -work work $src_home/baudGen.vhd +vcom -work work $src_home/uartTop.vhd +vcom -work work $src_home/uartParser.vhd +vcom -work work $src_home/uart2BusTop.vhd + +vcom -work work $tb_home/helpers/helpers_pkg.vhd +vcom -work work $tb_home/helpers/regFileModel.vhd +vcom -work work $tb_home/uart2BusTop_bin_tb.vhd + +onbreak {resume} + +vsim -voptargs=+acc work.uart2BusTop_bin_tb(behavior) + +do $sim_home/$wave_file + +run $time + +transcript file "" \ No newline at end of file Index: vhdl/sim/modelsim/wave_uart2bus_txt.do =================================================================== --- vhdl/sim/modelsim/wave_uart2bus_txt.do (nonexistent) +++ vhdl/sim/modelsim/wave_uart2bus_txt.do (revision 11) @@ -0,0 +1,63 @@ +onerror {resume} +virtual type { \ +Idle\ +HiNib\ +{0x4 LoNib}\ +{0x5 CharCR}\ +{0x6 CharLF}\ +{default undefined_state}\ +} vt_tx +virtual type { \ +Idle\ +White1\ +Data\ +White2\ +Addr\ +Eol\ +{0x8 BinCmd}\ +{0x9 BinAdrh}\ +{0xa BinAdrl}\ +{0xb BinLen}\ +{0xc BinData}\ +{default undefined_state}\ +} vt_main +quietly virtual signal -install /uart2bustop_txt_tb/uut/up {/uart2bustop_txt_tb/uut/up/mainsm } vs_main +quietly virtual signal -install /uart2bustop_txt_tb/uut/up {/uart2bustop_txt_tb/uut/up/txsm } vs_tx +quietly virtual function -install /uart2bustop_txt_tb/uut/up -env /uart2bustop_txt_tb { (vt_main) /uart2bustop_txt_tb/uut/up/vs_main} vf_main +quietly virtual function -install /uart2bustop_txt_tb/uut/up -env /uart2bustop_txt_tb { (vt_tx) /uart2bustop_txt_tb/uut/up/vs_tx} vf_tx +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {global signals} +add wave -noupdate -format Logic /uart2bustop_txt_tb/clr +add wave -noupdate -format Logic /uart2bustop_txt_tb/clk +add wave -noupdate -divider {UART serial signals} +add wave -noupdate -format Logic /uart2bustop_txt_tb/serin +add wave -noupdate -format Logic /uart2bustop_txt_tb/serout +add wave -noupdate -divider {Internal bus to register file} +add wave -noupdate -format Logic /uart2bustop_txt_tb/intaccessreq +add wave -noupdate -format Logic /uart2bustop_txt_tb/intaccessgnt +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_txt_tb/intrddata +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_txt_tb/intaddress +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_txt_tb/intwrdata +add wave -noupdate -format Logic /uart2bustop_txt_tb/intwrite +add wave -noupdate -format Logic /uart2bustop_txt_tb/intread +add wave -noupdate -divider Debug +add wave -noupdate -format Literal -radix hexadecimal /uart2bustop_txt_tb/recvdata +add wave -noupdate -format Logic /uart2bustop_txt_tb/newrxdata +add wave -noupdate -format Literal /uart2bustop_txt_tb/uut/up/vf_main +add wave -noupdate -format Literal /uart2bustop_txt_tb/uut/up/vf_tx +TreeUpdate [SetDefaultTree] +configure wave -namecolwidth 200 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {52500 us} Index: vhdl/sim/modelsim/uart2bus_bin_sim.bat =================================================================== --- vhdl/sim/modelsim/uart2bus_bin_sim.bat (nonexistent) +++ vhdl/sim/modelsim/uart2bus_bin_sim.bat (revision 11) @@ -0,0 +1,3 @@ +@Echo Off +Rem Modify the below vsim.exe path to run the test bench +C:\Modeltech_xe_starter\win32xoem\vsim.exe -do uart2bus_bin_sim.tcl Index: vhdl/sim/modelsim =================================================================== --- vhdl/sim/modelsim (revision 10) +++ vhdl/sim/modelsim (revision 11)
vhdl/sim/modelsim Property changes : Added: svn:ignore ## -0,0 +1,5 ## +*.ini +*.log +*.wlf +transcript +work Index: vhdl/sim/test.txt =================================================================== --- vhdl/sim/test.txt (nonexistent) +++ vhdl/sim/test.txt (revision 11) @@ -0,0 +1,6 @@ +w de 1a; +r 1a; +r 0a; +w 12 0a; +r 1a; +r 0a; \ No newline at end of file Index: vhdl/syn/xilinx/uart2bus.xise =================================================================== --- vhdl/syn/xilinx/uart2bus.xise (revision 10) +++ vhdl/syn/xilinx/uart2bus.xise (revision 11) @@ -27,6 +27,10 @@ + + + + @@ -35,28 +39,10 @@ - + - - - - - - - - - - - - - - - - - - @@ -80,8 +66,8 @@ - - + + @@ -123,7 +109,7 @@ - + @@ -142,7 +128,7 @@ - + @@ -241,7 +227,7 @@ - + @@ -298,7 +284,6 @@ - @@ -314,7 +299,7 @@ - + @@ -356,7 +341,7 @@ - + @@ -363,7 +348,7 @@ - + @@ -374,8 +359,8 @@ - - + +
/vhdl/syn/xilinx
vhdl/syn/xilinx Property changes : Added: svn:ignore ## -0,0 +1,16 ## +*.cmd_log +*.gise +*.html +*.ise +*.lso +*.ngc +*.ngr +*.ntrc_log +*.prj +*.stx +*.syr +*.xrpt +*.xst +_xmsgs +uart2bus_xdb +xst Index: vhdl =================================================================== --- vhdl (revision 10) +++ vhdl (revision 11)
vhdl Property changes : Added: svn:ignore ## -0,0 +1,16 ## +*.cmd_log +*.gise +*.html +*.ise +*.lso +*.ngc +*.ngr +*.ntrc_log +*.prj +*.stx +*.syr +*.xrpt +*.xst +_xmsgs +uart2bus_xdb +xst

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