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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

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  • This comparison shows the changes necessary to convert path 
    /uart2bus/trunk
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/doc/UART to Bus Core Specifications.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/verilog/bench/tb_txt_uart2bus_top.v
55,10 → 55,6
#100;
send_serial (8'h20, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
#100;
send_serial (8'h34, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
#100;
send_serial (8'h63, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
#100;
send_serial (8'h64, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
#100;
send_serial (8'h39, `BAUD_115200, `PARITY_EVEN, `PARITY_OFF, `NSTOPS_1, `NBITS_8, 0);
136,6 → 132,8
wire int_write; // write control to register file
wire int_read; // read control to register file
wire [7:0] int_rd_data; // data read from register file
wire int_req; // bus access request signal
wire int_gnt; // bus access grant signal
wire ser_in; // DUT serial input
wire ser_out; // DUT serial output
 
150,8 → 148,12
.int_wr_data(int_wr_data),
.int_write(int_write),
.int_rd_data(int_rd_data),
.int_read(int_read)
.int_read(int_read),
.int_req(int_req),
.int_gnt(int_gnt)
);
// bus grant is always active
assign int_gnt = 1'b1;
 
// serial interface to test bench
assign ser_in = serial_out;
/verilog/bench/tb_uart2bus_top.v
137,6 → 137,8
wire int_write; // write control to register file
wire int_read; // read control to register file
wire [7:0] int_rd_data; // data read from register file
wire int_req; // bus access request signal
wire int_gnt; // bus access grant signal
wire ser_in; // DUT serial input
wire ser_out; // DUT serial output
 
146,8 → 148,11
.clock(clock), .reset(reset),
.ser_in(ser_in), .ser_out(ser_out),
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
.int_rd_data(int_rd_data), .int_read(int_read)
.int_rd_data(int_rd_data), .int_read(int_read),
.int_req(int_req), .int_gnt(int_gnt)
);
// bus grant is always active
assign int_gnt = 1'b1;
 
// serial interface to test bench
assign ser_in = serial_out;
/verilog/bench/uart_tasks.v
238,7 → 238,6
if (serial_in != 1)
get_serial_status = get_serial_status | `RECEIVE_RESULT_BADSTOP;
end
#(bit_time/2);
end
end
end
/verilog/bench/tb_bin_uart2bus_top.v
191,6 → 191,8
wire int_write; // write control to register file
wire int_read; // read control to register file
wire [7:0] int_rd_data; // data read from register file
wire int_req; // bus access request signal
wire int_gnt; // bus access grant signal
wire ser_in; // DUT serial input
wire ser_out; // DUT serial output
 
205,8 → 207,12
.int_wr_data(int_wr_data),
.int_write(int_write),
.int_rd_data(int_rd_data),
.int_read(int_read)
.int_read(int_read),
.int_req(int_req),
.int_gnt(int_gnt)
);
// bus grant is always active
assign int_gnt = 1'b1;
 
// serial interface to test bench
assign ser_in = serial_out;
/verilog/rtl/uart_parser.v
12,7 → 12,8
tx_data, new_tx_data, tx_busy,
// internal bus to register file
int_address, int_wr_data, int_write,
int_rd_data, int_read
int_rd_data, int_read,
int_req, int_gnt
);
//---------------------------------------------------------------------------------------
// parameters
32,6 → 33,8
output int_write; // write control to register file
output int_read; // read control to register file
input [7:0] int_rd_data; // data read from register file
output int_req; // bus access request signal
input int_gnt; // bus access grant signal
 
// registered outputs
reg [7:0] tx_data;
38,7 → 41,7
reg new_tx_data;
reg [AW-1:0] int_address;
reg [7:0] int_wr_data;
reg int_write, int_read;
reg write_req, read_req, int_write, int_read;
 
// internal constants
// define characters used by the parser
403,20 → 406,27
begin
if (reset)
begin
write_req <= 1'b0;
int_write <= 1'b0;
int_wr_data <= 0;
end
else if (write_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
begin
int_write <= 1'b1;
write_req <= 1'b1;
int_wr_data <= data_param;
end
// binary extension mode
else if (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)
begin
int_write <= 1'b1;
write_req <= 1'b1;
int_wr_data <= rx_data;
end
else if (int_gnt && write_req)
begin
// set internal bus write and clear the write request flag
int_write <= 1'b1;
write_req <= 1'b0;
end
else
int_write <= 1'b0;
end
425,21 → 435,33
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
int_read <= 1'b0;
read_req <= 1'b0;
end
else if (read_op && (main_sm == `MAIN_ADDR) && new_rx_data && !data_in_hex_range)
int_read <= 1'b1;
read_req <= 1'b1;
// binary extension
else if (bin_read_op && (main_sm == `MAIN_BIN_LEN) && new_rx_data)
// the first read request is issued on reception of the length byte
int_read <= 1'b1;
read_req <= 1'b1;
else if (bin_read_op && tx_end_p && !bin_last_byte)
// the next read requests are issued after the previous read value was transmitted and
// this is not the last byte to be read.
read_req <= 1'b1;
else if (int_gnt && read_req)
begin
// set internal bus read and clear the read request flag
int_read <= 1'b1;
read_req <= 1'b0;
end
else
int_read <= 1'b0;
end
 
// external request signal is active on read or write request
assign int_req = write_req | read_req;
 
// internal address
always @ (posedge clock or posedge reset)
begin
453,7 → 475,6
int_address <= addr_param[AW-1:0];
else if (addr_auto_inc &&
((bin_read_op && tx_end_p && !bin_last_byte) ||
// (bin_write_op && (main_sm == `MAIN_BIN_DATA) && new_rx_data)))
(bin_write_op && int_write)))
// address is incremented on every read or write if enabled
int_address <= int_address + 1;
/verilog/rtl/uart2bus_top.v
11,7 → 11,8
ser_in, ser_out,
// internal bus to register file
int_address, int_wr_data, int_write,
int_rd_data, int_read
int_rd_data, int_read,
int_req, int_gnt
);
//---------------------------------------------------------------------------------------
// modules inputs and outputs
24,6 → 25,8
output int_write; // write control to register file
output int_read; // read control to register file
input [7:0] int_rd_data; // data read from register file
output int_req; // bus access request signal
input int_gnt; // bus access grant signal
 
// baud rate configuration, see baud_gen.v for more details.
// baud rate generator parameters for 115200 baud on 40MHz clock
70,7 → 73,8
.rx_data(rx_data), .new_rx_data(new_rx_data),
.tx_data(tx_data), .new_tx_data(new_tx_data), .tx_busy(tx_busy),
.int_address(int_address), .int_wr_data(int_wr_data), .int_write(int_write),
.int_rd_data(int_rd_data), .int_read(int_read)
.int_rd_data(int_rd_data), .int_read(int_read),
.int_req(int_req), .int_gnt(int_gnt)
);
 
endmodule

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