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/v1.1/bench/vhdl/IP_complete_nomac_tb.vhd
0,0 → 1,387
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:32 06/04/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IP_complete_nomac_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IP_complete_nomac
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
ENTITY IP_complete_nomac_tb IS
END IP_complete_nomac_tb;
ARCHITECTURE behavior OF IP_complete_nomac_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IP_complete_nomac
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
 
--Inputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
 
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_tready : std_logic := '0';
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_rx_tvalid : std_logic := '0';
signal mac_rx_tlast : std_logic := '0';
--Outputs
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
signal ip_rx_start : std_logic;
signal ip_rx : ipv4_rx_type;
signal arp_pkt_count : std_logic_vector(7 downto 0);
signal mac_tx_tdata : std_logic_vector(7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tfirst : std_logic;
signal mac_tx_tlast : std_logic;
signal mac_rx_tready : std_logic;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IP_complete_nomac PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => clk,
tx_clk => clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_pkt_count => arp_pkt_count,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 80 ns;
 
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
ip_tx_start <= '0';
mac_tx_tready <= '0';
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
assert mac_tx_tlast = '0' report " mac_tx_tlast not initialised correctly on reset";
assert arp_pkt_count = x"00" report " arp_pkt_count not initialised correctly on reset";
assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
 
-- insert stimulus here
 
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
 
report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
 
mac_tx_tready <= '1';
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
mac_rx_tdata <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_rx_tdata <= x"45"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- total len
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
-- ID
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- flags & frag
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- TTL
mac_rx_tdata <= x"00"; wait for clk_period;
-- Protocol
mac_rx_tdata <= x"11"; wait for clk_period;
-- Header CKS
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- SRC IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- DST IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
-- user data
mac_rx_tdata <= x"24"; wait for clk_period;
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
assert ip_rx_start = '1' report "T1: ip_rx_start not set";
assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
 
mac_rx_tdata <= x"25"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"27"; mac_rx_tlast <= '1'; wait for clk_period;
 
assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
mac_rx_tdata <= x"00";
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait for clk_period;
assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
 
------------
-- TEST 2 -- respond with IP TX
------------
report "T2: respond with IP TX";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period;
ip_tx_start <= '1'; wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
wait for clk_period*2;
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
-- need to wait for ARP tx to complete
wait for clk_period*50;
assert mac_tx_tvalid = '0' report "T2: mac_tx_tvalid not cleared after ARP tx";
assert mac_tx_tlast = '0' report "T2: mac_tx_tlast not cleared after ARP tx";
 
-- now create the ARP response (rx)
 
-- Send the reply
-- Send an ARP reply: x"c0123478" has mac 02:12:03:23:04:54
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"06"; wait for clk_period;
-- HW type
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Protocol type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- HW size
mac_rx_tdata <= x"06"; wait for clk_period;
-- protocol size
mac_rx_tdata <= x"04"; wait for clk_period;
-- Opcode
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"02"; wait for clk_period;
-- Sender MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- Sender IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"34"; wait for clk_period;
mac_rx_tdata <= x"78"; wait for clk_period;
-- Target MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- Target IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '1';
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"56"; wait for clk_period;
ip_tx.data.data_out <= x"57"; wait for clk_period;
ip_tx.data.data_out <= x"58"; wait for clk_period;
ip_tx.data.data_out <= x"59"; wait for clk_period;
ip_tx.data.data_out <= x"5a"; wait for clk_period;
ip_tx.data.data_out <= x"5b";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
 
assert mac_tx_tlast = '1' report "T1: mac_tx_tlast not set on last byte";
 
wait for clk_period;
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
 
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be SENT";
wait for clk_period*2;
 
 
report "-- end of tests --";
 
wait;
end process;
 
END;
/v1.1/bench/vhdl/IPv4_TX_tb.vhd
0,0 → 1,309
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:35:58 06/03/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4_TX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
ENTITY IPv4_TX_tb IS
END IPv4_TX_tb;
ARCHITECTURE behavior OF IPv4_TX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPv4_TX
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
 
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
 
--Inputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_granted : std_logic := '0';
signal mac_data_out_ready : std_logic := '0';
signal arp_req_rslt : arp_req_rslt_type;
 
--Outputs
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
signal mac_tx_req : std_logic;
signal mac_data_out_valid : std_logic;
signal mac_data_out_last : std_logic;
signal mac_data_out_first : std_logic;
signal mac_data_out : std_logic_vector(7 downto 0);
signal arp_req_req : arp_req_req_type;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IPv4_TX PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
clk => clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
mac_data_out_ready => mac_data_out_ready,
mac_data_out_valid => mac_data_out_valid,
mac_data_out_first => mac_data_out_first,
mac_data_out_last => mac_data_out_last,
mac_data_out => mac_data_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
ip_tx_start <= '0';
mac_tx_granted <= '0';
mac_data_out_ready <= '0';
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
arp_req_rslt.got_mac <= '0';
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
 
-- insert stimulus here
------------
-- TEST 1 -- basic functional tx test with some delays for arp and chn access
------------
report "T1: basic functional tx test with some delays for arp and chn access";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0008";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx_start <= '1';
wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
arp_req_rslt.got_mac <= '0';
arp_req_rslt.got_err <= '0';
assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
wait for clk_period*10; -- simulate arp lookup time
arp_req_rslt.mac <= x"050423271016";
arp_req_rslt.got_mac <= '1';
 
wait for clk_period*2;
assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
 
wait for clk_period*10; -- simulate mac chn access time
mac_tx_granted <= '1';
wait for clk_period*2;
mac_data_out_ready <= '1';
assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
 
wait for clk_period;
 
assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
wait for clk_period;
assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
-- wait until in eth hdr
wait for clk_period*3;
-- go mac not ready for 2 clocks
mac_data_out_ready <= '0';
wait for clk_period*2;
mac_data_out_ready <= '1';
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"56"; wait for clk_period;
-- delay data in for 1 clk cycle
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out <= x"57"; wait for clk_period;
ip_tx.data.data_out_valid <= '1'; wait for clk_period;
ip_tx.data.data_out <= x"58"; wait for clk_period;
ip_tx.data.data_out <= x"59"; wait for clk_period;
-- delay mac ready for 2 clk cycles
mac_data_out_ready <= '0';
ip_tx.data.data_out <= x"5a"; wait for clk_period;
assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
ip_tx.data.data_out <= x"5a"; wait for clk_period;
mac_data_out_ready <= '1';
wait until ip_tx_data_out_ready = '1';
wait for clk_period;
assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
ip_tx.data.data_out <= x"5b"; wait for clk_period;
ip_tx.data.data_out <= x"5c"; wait for clk_period;
ip_tx.data.data_out <= x"5d";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
 
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
mac_tx_granted <= '0';
wait for clk_period*2;
 
------------
-- TEST 2 -- basic functional tx test with no delays for arp and chn access
------------
report "T2: basic functional tx test with no delays for arp and chn access";
ip_tx.hdr.protocol <= x"11";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx_start <= '1';
wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
arp_req_rslt.got_mac <= '0';
assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
wait for clk_period; -- simulate arp lookup time
arp_req_rslt.mac <= x"050423271016";
arp_req_rslt.got_mac <= '1';
 
wait for clk_period*2;
assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
 
wait for clk_period; -- simulate mac chn access time
mac_tx_granted <= '1';
wait for clk_period*2;
mac_data_out_ready <= '1';
 
assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"c1"; wait for clk_period;
ip_tx.data.data_out <= x"c2"; wait for clk_period;
ip_tx.data.data_out <= x"c3"; wait for clk_period;
ip_tx.data.data_out <= x"c4"; wait for clk_period;
ip_tx.data.data_out <= x"c5"; wait for clk_period;
ip_tx.data.data_out <= x"c6";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
 
assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
 
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
 
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
mac_tx_granted <= '0';
wait for clk_period*2;
 
report "--- end of tests ---";
 
wait;
end process;
 
END;
/v1.1/bench/vhdl/UDP_complete_nomac_tb.vhd
0,0 → 1,656
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:57:01 06/13/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/udp1/UDP_complete_nomac_tb.vhd
-- Project Name: udp1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: UDP_Complete_nomac
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
ENTITY UDP_complete_nomac_tb IS
END UDP_complete_nomac_tb;
ARCHITECTURE behavior OF UDP_complete_nomac_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UDP_Complete_nomac
PORT(
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
 
type state_type is (IDLE, DATA_OUT);
type count_mode_type is (RST, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
 
--Inputs
signal udp_tx_start_int : std_logic := '0';
signal udp_tx_int : udp_tx_type;
signal clk_int : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_tready : std_logic := '0';
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_rx_tvalid : std_logic := '0';
signal mac_rx_tlast : std_logic := '0';
 
--Outputs
signal udp_rx_start_int : std_logic;
signal udp_rx_int : udp_rx_type;
signal ip_rx_hdr : ipv4_rx_header_type;
signal udp_tx_result : std_logic_vector (1 downto 0);
signal udp_tx_data_out_ready_int: std_logic;
 
signal arp_pkt_count : std_logic_vector(7 downto 0);
signal ip_pkt_count : std_logic_vector(7 downto 0);
signal mac_tx_tdata : std_logic_vector(7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tfirst : std_logic;
signal mac_tx_tlast : std_logic;
signal mac_rx_tready : std_logic;
 
signal pbtx_led : std_logic;
signal pbtx : std_logic := '0';
-- state signals
signal state : state_type;
signal count : unsigned (7 downto 0);
signal tx_hdr : udp_tx_header_type;
signal tx_start_reg : std_logic;
signal tx_started_reg : std_logic;
signal tx_fin_reg : std_logic;
-- control signals
signal next_state : state_type;
signal set_state : std_logic;
signal set_count : count_mode_type;
signal set_hdr : std_logic;
signal set_tx_start : set_clr_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_tx_started : set_clr_type;
signal set_tx_fin : set_clr_type;
 
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UDP_Complete_nomac PORT MAP (
udp_tx_start => udp_tx_start_int,
udp_txi => udp_tx_int,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
udp_rx_start => udp_rx_start_int,
udp_rxo => udp_rx_int,
ip_rx_hdr => ip_rx_hdr,
rx_clk => clk_int,
tx_clk => clk_int,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
 
-- Clock process definitions
clk_process :process
begin
clk_int <= '0';
wait for clk_period/2;
clk_int <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
mac_tx_tready <= '0';
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert udp_tx_result = UDPTX_RESULT_NONE report "udp_tx_result not initialised correctly on reset";
assert udp_tx_data_out_ready_int = '0' report "ip_udp_txitx.data.data_out_ready not initialised correctly on reset";
assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
assert mac_tx_tlast = '0' report "mac_tx_tlast not initialised correctly on reset";
assert arp_pkt_count = x"00" report "arp_pkt_count not initialised correctly on reset";
assert ip_pkt_count = x"00" report "ip_pkt_count not initialised correctly on reset";
assert udp_rx_start_int = '0' report "udp_rx_start not initialised correctly on reset";
assert udp_rx_int.hdr.is_valid = '0' report "udp_rx_int.hdr.is_valid not initialised correctly on reset";
assert udp_rx_int.hdr.data_length = x"0000" report "udp_rx_int.hdr.data_length not initialised correctly on reset";
assert udp_rx_int.hdr.src_ip_addr = x"00000000" report "udp_rx_int.hdr.src_ip_addr not initialised correctly on reset";
assert udp_rx_int.hdr.src_port = x"0000" report "udp_rx_int.hdr.src_port not initialised correctly on reset";
assert udp_rx_int.hdr.dst_port = x"0000" report "udp_rx_int.hdr.dst_port not initialised correctly on reset";
assert udp_rx_int.data.data_in = x"00" report "udp_rx_start.data.data_in not initialised correctly on reset";
assert udp_rx_int.data.data_in_valid = '0' report "udp_rx_start.data.data_in_valid not initialised correctly on reset";
assert udp_rx_int.data.data_in_last = '0' report "udp_rx_start.data.data_in_last not initialised correctly on reset";
assert ip_rx_hdr.is_valid = '0' report "ip_rx_hdr.is_valid not initialised correctly on reset";
assert ip_rx_hdr.protocol = x"00" report "ip_rx_hdr.protocol not initialised correctly on reset";
assert ip_rx_hdr.data_length = x"0000" report "ip_rx_hdr.data_length not initialised correctly on reset";
assert ip_rx_hdr.src_ip_addr = x"00000000" report "ip_rx_hdr.src_ip_addr not initialised correctly on reset";
assert ip_rx_hdr.num_frame_errors = x"00" report "ip_rx_hdr.num_frame_errors not initialised correctly on reset";
 
 
-- insert stimulus here
------------
-- TEST 1 -- send ARP request
------------
 
report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
 
mac_tx_tready <= '1';
 
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"06"; wait for clk_period;
-- HW type
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Protocol type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- HW size
mac_rx_tdata <= x"06"; wait for clk_period;
-- protocol size
mac_rx_tdata <= x"04"; wait for clk_period;
-- Opcode
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Sender MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- Sender IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Target MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- Target IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '1';
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
-- check we got the ARP pkt
assert arp_pkt_count = x"01" report "T1: arp_pkt_count wrong value";
assert ip_pkt_count = x"00" report "T1: ip_pkt_count wrong value";
assert udp_tx_result = UDPTX_RESULT_NONE report "T1: udp_tx_result wrong value";
assert udp_tx_data_out_ready_int = '0' report "T1: ip_udp_txitx.data.data_out_ready wrong value";
assert udp_rx_start_int = '0' report "T1: udp_rx_start wrong value";
assert udp_rx_int.hdr.is_valid = '0' report "T1: udp_rx_int.hdr.is_valid wrong value";
assert ip_rx_hdr.is_valid = '0' report "T1: ip_rx_hdr.is_valid wrong value";
 
-- check we tx a response
wait for clk_period*25;
assert mac_tx_tvalid = '1' report "T1: not transmitting a response";
wait for clk_period*25;
assert mac_tx_tvalid = '0' report "T1: tx held on for too long";
------------
-- TEST 2 -- send UDP pkt (same as sample from Java program
------------
report "T2: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
 
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
mac_rx_tdata <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_rx_tdata <= x"45"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- total len
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
-- ID
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"7a"; wait for clk_period;
-- flags & frag
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- TTL
mac_rx_tdata <= x"80"; wait for clk_period;
-- Protocol
mac_rx_tdata <= x"11"; wait for clk_period;
-- Header CKS
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- SRC IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- DST IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
-- SRC port
mac_rx_tdata <= x"f4"; wait for clk_period;
mac_rx_tdata <= x"9a"; wait for clk_period;
-- DST port
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"94"; wait for clk_period;
-- length
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"0d"; wait for clk_period;
-- cks
mac_rx_tdata <= x"8b"; wait for clk_period;
mac_rx_tdata <= x"79"; wait for clk_period;
-- user data
mac_rx_tdata <= x"68"; wait for clk_period;
 
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
assert udp_rx_int.hdr.is_valid = '1' report "T2: udp_rx_int.hdr.is_valid not set";
assert udp_rx_int.hdr.data_length = x"0005" report "T2: udp_rx_int.hdr.data_length not set correctly";
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rx_int.hdr.src_ip_addr not set correctly";
assert udp_rx_int.hdr.src_port = x"f49a" report "T2: udp_rx_int.hdr.src_port not set correctly";
assert udp_rx_int.hdr.dst_port = x"2694" report "T2: udp_rx_int.hdr.dst_port not set correctly";
 
assert udp_rx_start_int = '1' report "T2: udp_rx_start not set";
assert udp_rx_int.data.data_in_valid = '1' report "T2: udp_rx_int.data.data_in_valid not set";
 
assert ip_rx_hdr.is_valid = '1' report "T2: ip_rx_hdr.is_valid not set";
assert ip_rx_hdr.protocol = x"11" report "T2: ip_rx_hdr.protocol not set correctly";
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T2: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code not set correctly";
 
-- put the rest of the user data
mac_rx_tdata <= x"65"; wait for clk_period;
mac_rx_tdata <= x"6c"; wait for clk_period;
mac_rx_tdata <= x"6c"; wait for clk_period;
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
 
assert udp_rx_int.data.data_in_last = '1' report "T2: udp_rx_int.data.data_in_last not set";
mac_rx_tdata <= x"00";
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait for clk_period;
assert udp_rx_int.data.data_in_valid = '0' report "T2: udp_rx_int.data.data_in_valid not cleared";
assert udp_rx_int.data.data_in_last = '0' report "T2: udp_rx_int.data.data_in_last not cleared";
assert udp_rx_start_int = '0' report "T2: udp_rx_start not cleared";
assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx_hdr.num_frame_errors non zero at end of test";
assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx_hdr.last_error_code indicates error at end of test";
assert ip_pkt_count = x"01" report "T2: ip pkt cnt incorrect";
 
wait for clk_period*20;
 
------------
-- TEST 3 -- send UDP pkt again (same as sample from Java program
------------
report "T3: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
 
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
mac_rx_tdata <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_rx_tdata <= x"45"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- total len
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
-- ID
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"7a"; wait for clk_period;
-- flags & frag
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- TTL
mac_rx_tdata <= x"80"; wait for clk_period;
-- Protocol
mac_rx_tdata <= x"11"; wait for clk_period;
-- Header CKS
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- SRC IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- DST IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
-- SRC port
mac_rx_tdata <= x"f4"; wait for clk_period;
mac_rx_tdata <= x"9a"; wait for clk_period;
-- DST port
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"94"; wait for clk_period;
-- length
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"0d"; wait for clk_period;
-- cks
mac_rx_tdata <= x"8b"; wait for clk_period;
mac_rx_tdata <= x"79"; wait for clk_period;
-- user data
mac_rx_tdata <= x"68"; wait for clk_period;
 
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
assert udp_rx_int.hdr.is_valid = '1' report "T3: udp_rx_int.hdr.is_valid not set";
assert udp_rx_int.hdr.data_length = x"0005" report "T3: udp_rx_int.hdr.data_length not set correctly";
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T3: udp_rx_int.hdr.src_ip_addr not set correctly";
assert udp_rx_int.hdr.src_port = x"f49a" report "T3: udp_rx_int.hdr.src_port not set correctly";
assert udp_rx_int.hdr.dst_port = x"2694" report "T3: udp_rx_int.hdr.dst_port not set correctly";
 
assert udp_rx_start_int = '1' report "T3: udp_rx_start not set";
assert udp_rx_int.data.data_in_valid = '1' report "T3: udp_rx_int.data.data_in_valid not set";
 
assert ip_rx_hdr.is_valid = '1' report "T3: ip_rx_hdr.is_valid not set";
assert ip_rx_hdr.protocol = x"11" report "T3: ip_rx_hdr.protocol not set correctly";
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T3: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx.hdr.last_error_code not set correctly";
 
-- put the rest of the user data
mac_rx_tdata <= x"65"; wait for clk_period;
mac_rx_tdata <= x"6c"; wait for clk_period;
mac_rx_tdata <= x"6c"; wait for clk_period;
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
 
assert udp_rx_int.data.data_in_last = '1' report "T3: udp_rx_int.data.data_in_last not set";
mac_rx_tdata <= x"00";
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait for clk_period;
assert udp_rx_int.data.data_in_valid = '0' report "T3: udp_rx_int.data.data_in_valid not cleared";
assert udp_rx_int.data.data_in_last = '0' report "T3: udp_rx_int.data.data_in_last not cleared";
assert udp_rx_start_int = '0' report "T3: udp_rx_start not cleared";
assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx_hdr.num_frame_errors non zero at end of test";
assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx_hdr.last_error_code indicates error at end of test";
assert ip_pkt_count = x"02" report "T3: ip pkt cnt incorrect";
 
report "--- end of tests ---";
wait;
end process;
-- AUTO TX process - on receipt of any UDP pkt, send a response
-- TX response process - COMB
tx_proc_combinatorial: process(
-- inputs
udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX,
-- state
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
-- controls
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
set_tx_started, set_tx_fin
)
begin
-- set output_followers
udp_tx_int.hdr <= tx_hdr;
udp_tx_int.data.data_out_last <= set_last;
udp_tx_start_int <= tx_start_reg;
 
-- set control signal defaults
next_state <= IDLE;
set_state <= '0';
set_count <= HOLD;
set_hdr <= '0';
set_tx_start <= HOLD;
set_last <= '0';
set_tx_started <= HOLD;
set_tx_fin <= HOLD;
-- FSM
case state is
when IDLE =>
udp_tx_int.data.data_out <= (others => '0');
udp_tx_int.data.data_out_valid <= '0';
if udp_rx_start_int = '1' or PBTX = '1' then
set_tx_started <= SET;
set_hdr <= '1';
set_tx_start <= SET;
set_tx_fin <= CLR;
set_count <= RST;
next_state <= DATA_OUT;
set_state <= '1';
end if;
when DATA_OUT =>
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
if udp_tx_data_out_ready_int = '1' then
set_tx_start <= CLR;
if unsigned(count) = x"03" then
set_last <= '1';
set_tx_fin <= SET;
set_tx_started <= CLR;
next_state <= IDLE;
set_state <= '1';
else
set_count <= INCR;
end if;
end if;
end case;
end process;
 
-- TX response process - SEQ
tx_proc_sequential: process(clk_int)
begin
if rising_edge(clk_int) then
if reset = '1' then
-- reset state variables
state <= IDLE;
count <= x"00";
tx_start_reg <= '0';
tx_hdr.dst_ip_addr <= (others => '0');
tx_hdr.dst_port <= (others => '0');
tx_hdr.src_port <= (others => '0');
tx_hdr.data_length <= (others => '0');
tx_hdr.checksum <= (others => '0');
tx_started_reg <= '0';
tx_fin_reg <= '0';
PBTX_LED <= '0';
else
PBTX_LED <= PBTX;
-- Next rx_state processing
if set_state = '1' then
state <= next_state;
else
state <= state;
end if;
-- count processing
case set_count is
when RST => count <= x"00";
when INCR => count <= count + 1;
when HOLD => count <= count;
end case;
-- set tx hdr
if set_hdr = '1' then
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
tx_hdr.data_length <= x"0004";
tx_hdr.checksum <= x"0000";
else
tx_hdr <= tx_hdr;
end if;
-- set tx start signal
case set_tx_start is
when SET => tx_start_reg <= '1';
when CLR => tx_start_reg <= '0';
when HOLD => tx_start_reg <= tx_start_reg;
end case;
 
-- set tx started signal
case set_tx_started is
when SET => tx_started_reg <= '1';
when CLR => tx_started_reg <= '0';
when HOLD => tx_started_reg <= tx_started_reg;
end case;
 
-- set tx finished signal
case set_tx_fin is
when SET => tx_fin_reg <= '1';
when CLR => tx_fin_reg <= '0';
when HOLD => tx_fin_reg <= tx_fin_reg;
end case;
end if;
end if;
 
end process;
 
END;
/v1.1/bench/vhdl/arp_tb.vhd
0,0 → 1,384
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:35:50 05/31/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/arp1/arp_tb.vhd
-- Project Name: arp1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: arp
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.arp_types.all;
ENTITY arp_tb IS
END arp_tb;
ARCHITECTURE behavior OF arp_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT arp
PORT(
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in_valid : std_logic := '0';
signal data_in_last : std_logic := '0';
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal data_out_ready : std_logic;
signal data_out_valid : std_logic;
signal data_out_first : std_logic;
signal data_out_last : std_logic;
signal data_out : std_logic_vector (7 downto 0);
signal req_count : STD_LOGIC_VECTOR(7 downto 0);
signal arp_req_req : arp_req_req_type;
signal arp_req_rslt : arp_req_rslt_type;
signal mac_tx_req : std_logic;
signal mac_tx_granted : std_logic;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: arp PORT MAP (
-- lookup request mappings
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- rx mappings
data_in_clk => clk,
reset => reset,
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- tx mappings
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_clk => clk,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system mappings
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
req_count => req_count
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
mac_tx_granted <= '1'; -- FIXME 0
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
assert mac_tx_req = '0' report "mac_tx_req asserted on reset";
 
-- insert stimulus here
arp_req_req.lookup_req <= '0';
arp_req_req.ip <= (others => '0');
data_out_ready <= '1';
 
report "T1: Send an ARP request: who has 192.168.5.8? Tell 192.168.5.1";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
-- check tx arbitration signals
assert mac_tx_req = '1' report "T1: mac_tx_req not set";
-- ready to tx
data_out_ready <= '1';
mac_tx_granted <= '1';
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*50;
report "T2: Send another ARP request: who has 192.168.5.8? Tell 192.168.5.1, holding off transmitter";
data_out_ready <= '0';
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
-- ready to tx
wait for clk_period*10;
data_out_ready <= '1';
wait for clk_period*50;
-- Send a request for the IP that is already cached
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
 
wait for clk_period*50;
-- Send a request for the IP that is not cached
arp_req_req.ip <= x"c0a80503";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period*80;
-- Send the reply
data_out_ready <= '1';
 
report "T3: Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
 
report "--- end of tests ---";
wait;
end process;
 
END;
/v1.1/bench/vhdl/IPv4_RX_tb.vhd
0,0 → 1,301
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:32:02 06/03/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_RX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
ENTITY IPv4_RX_tb IS
END IPv4_RX_tb;
ARCHITECTURE behavior OF IPv4_RX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPv4_RX
PORT(
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC -- indicates last data in frame
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal mac_data_in : std_logic_vector(7 downto 0) := (others => '0');
signal mac_data_in_valid : std_logic := '0';
signal mac_data_in_last : std_logic := '0';
 
--Outputs
signal ip_rx_start : std_logic;
signal ip_rx : ipv4_rx_type;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IPv4_RX PORT MAP (
ip_rx => ip_rx,
ip_rx_start => ip_rx_start,
clk => clk,
reset => reset,
our_ip_address => our_ip_address,
mac_data_in => mac_data_in,
mac_data_in_valid => mac_data_in_valid,
mac_data_in_last => mac_data_in_last
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
our_ip_address <= x"c0a80509"; -- 192.168.5.9
mac_data_in_valid <= '0';
mac_data_in_last <= '0';
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
 
-- insert stimulus here
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
 
report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
 
mac_data_in_valid <= '1';
-- dst MAC (bc)
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"23"; wait for clk_period;
mac_data_in <= x"20"; wait for clk_period;
mac_data_in <= x"21"; wait for clk_period;
mac_data_in <= x"22"; wait for clk_period;
mac_data_in <= x"23"; wait for clk_period;
-- src MAC
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"23"; wait for clk_period;
mac_data_in <= x"18"; wait for clk_period;
mac_data_in <= x"29"; wait for clk_period;
mac_data_in <= x"26"; wait for clk_period;
mac_data_in <= x"7c"; wait for clk_period;
-- type
mac_data_in <= x"08"; wait for clk_period; -- IP pkt
mac_data_in <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_data_in <= x"45"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- total len
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"18"; wait for clk_period;
-- ID
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- flags & frag
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- TTL
mac_data_in <= x"00"; wait for clk_period;
-- Protocol
mac_data_in <= x"11"; wait for clk_period;
-- Header CKS
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- SRC IP
mac_data_in <= x"c0"; wait for clk_period;
mac_data_in <= x"a8"; wait for clk_period;
mac_data_in <= x"05"; wait for clk_period;
mac_data_in <= x"01"; wait for clk_period;
-- DST IP
mac_data_in <= x"c0"; wait for clk_period;
mac_data_in <= x"a8"; wait for clk_period;
mac_data_in <= x"05"; wait for clk_period;
mac_data_in <= x"09"; wait for clk_period;
-- user data
mac_data_in <= x"24"; wait for clk_period;
assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
assert ip_rx_start = '1' report "T1: ip_rx_start not set";
assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
 
mac_data_in <= x"25"; wait for clk_period;
mac_data_in <= x"26"; wait for clk_period;
mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;
 
assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
mac_data_in <= x"00";
mac_data_in_last <= '0';
mac_data_in_valid <= '0';
wait for clk_period;
assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
 
------------
-- TEST 2 -- basic functional rx test with received ip pkt that is not for us
------------
 
report "T2: Send an eth frame with IP pkt dst ip_address c0a80507, dst mac 002320212223";
 
mac_data_in_valid <= '1';
-- dst MAC (bc)
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"23"; wait for clk_period;
mac_data_in <= x"20"; wait for clk_period;
mac_data_in <= x"21"; wait for clk_period;
mac_data_in <= x"22"; wait for clk_period;
mac_data_in <= x"23"; wait for clk_period;
 
assert ip_rx.hdr.is_valid = '0' report "T2: ip_rx.hdr.is_valid remains set";
 
-- src MAC
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"23"; wait for clk_period;
mac_data_in <= x"18"; wait for clk_period;
mac_data_in <= x"29"; wait for clk_period;
mac_data_in <= x"26"; wait for clk_period;
mac_data_in <= x"7c"; wait for clk_period;
-- type
mac_data_in <= x"08"; wait for clk_period; -- IP pkt
mac_data_in <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_data_in <= x"45"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- total len
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"18"; wait for clk_period;
-- ID
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- flags & frag
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- TTL
mac_data_in <= x"00"; wait for clk_period;
-- Protocol
mac_data_in <= x"11"; wait for clk_period;
-- Header CKS
mac_data_in <= x"00"; wait for clk_period;
mac_data_in <= x"00"; wait for clk_period;
-- SRC IP
mac_data_in <= x"c0"; wait for clk_period;
mac_data_in <= x"a8"; wait for clk_period;
mac_data_in <= x"05"; wait for clk_period;
mac_data_in <= x"02"; wait for clk_period;
-- DST IP
mac_data_in <= x"c0"; wait for clk_period;
mac_data_in <= x"a8"; wait for clk_period;
mac_data_in <= x"05"; wait for clk_period;
mac_data_in <= x"07"; wait for clk_period;
-- user data
mac_data_in <= x"24"; wait for clk_period;
assert ip_rx.hdr.is_valid = '1' report "T2: ip_rx.hdr.is_valid not set";
assert ip_rx.hdr.protocol = x"11" report "T2: ip_rx.hdr.protocol not set correctly";
assert ip_rx.hdr.data_length = x"0004" report "T2: ip_rx.hdr.data_length not set correctly";
assert ip_rx.hdr.src_ip_addr = x"c0a80502" report "T2: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx.hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx.hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code not set correctly";
assert ip_rx_start = '0' report "T2: ip_rx_start set when pkt not for us";
assert ip_rx.data.data_in_valid = '0' report "T2: ip_rx.data.data_in_valid set when pkt not for us";
 
mac_data_in <= x"25"; wait for clk_period;
mac_data_in <= x"26"; wait for clk_period;
mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;
 
assert ip_rx.data.data_in_last = '0' report "T2: ip_rx.data.data_in_last set";
mac_data_in <= x"00";
mac_data_in_last <= '0';
mac_data_in_valid <= '0';
wait for clk_period;
assert ip_rx.data.data_in_valid = '0' report "T2: ip_rx.data.data_in_valid not cleared";
assert ip_rx.data.data_in_last = '0' report "T2: ip_rx.data.data_in_last not cleared";
assert ip_rx.hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors non zero at end of test";
assert ip_rx.hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code indicates error at end of test";
assert ip_rx_start = '0' report "T2: ip_rx_start not cleared";
report "--- end of tests ---";
wait;
end process;
 
END;
/v1.1/bench/vhdl/UDP_RX_tb.vhd
0,0 → 1,324
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:03 06/10/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_RX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: UDP_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
ENTITY UDP_RX_tb IS
END UDP_RX_tb;
ARCHITECTURE behavior OF UDP_RX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rxo : inout udp_rx_type;
udp_rx_start : out std_logic; -- indicates receipt of udp header
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : inout ipv4_rx_type
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ip_rx_start : std_logic := '0';
 
--BiDirs
signal udp_rxo : udp_rx_type;
signal ip_rx : ipv4_rx_type;
 
--Outputs
signal udp_rx_start : std_logic;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UDP_RX PORT MAP (
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
clk => clk,
reset => reset,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
ip_rx.hdr.protocol <= (others => '0');
ip_rx.hdr.num_frame_errors <= (others => '0');
ip_rx.hdr.last_error_code <= (others => '0');
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
reset <= '0';
-- check reset conditions
assert udp_rx_start = '0' report "udp_rx_start not initialised correctly on reset";
assert udp_rxo.hdr.is_valid = '0' report "udp_rxo.hdr.is_valid not initialised correctly on reset";
assert udp_rxo.data.data_in = x"00" report "udp_rxo.data.data_in not initialised correctly on reset";
assert udp_rxo.data.data_in_valid = '0' report "udp_rxo.data.data_in_valid not initialised correctly on reset";
assert udp_rxo.data.data_in_last = '0' report "udp_rxo.data.data_in_last not initialised correctly on reset";
 
-- insert stimulus here
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
 
report "T1: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
 
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"98"; wait for clk_period;
ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"24"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0b"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T1: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T1: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"1498" report "T1: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"8724" report "T1: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0003" report "T1: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T1: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T1: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T1: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T1: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T1: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T1: udp_rxo.data.data_in_last not cleared";
 
wait for clk_period;
 
------------
-- TEST 2 -- ability to receive 2nd ip pkt
------------
 
report "T2: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x7623 to port x0365 and 5 bytes data";
 
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"23"; wait for clk_period;
ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"65"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0d"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T2: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"7623" report "T2: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"0365" report "T2: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0005" report "T2: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T2: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T2: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T2: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T2: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T2: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T2: udp_rxo.data.data_in_last not cleared";
 
------------
-- TEST 3 -- ability to reject non-udp protocols
------------
 
report "T3: Send an ip frame with IP src ip_address c0a80501, protocol x12 from port x7623 to port x0365 and 5 bytes data";
 
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"12"; -- non-UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"23"; wait for clk_period;
ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"65"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0d"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '0' report "T3: udp_rxo.hdr.is_valid incorrectly set";
ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
assert udp_rx_start = '0' report "T3: udp_rx_start incorrectly set";
assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last incorrectly set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T3: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last not cleared";
 
wait for clk_period;
 
------------
-- TEST 4 -- Ability to receive UDP pkt after non-UDP pkt
------------
 
report "T4: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
 
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"98"; wait for clk_period;
ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"24"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0b"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T4: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T4: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"1498" report "T4: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"8724" report "T4: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0003" report "T4: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T4: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T4: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T4: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T4: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T4: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T4: udp_rxo.data.data_in_last not cleared";
 
wait for clk_period;
 
report "--- end of tests ---";
wait;
end process;
 
END;
/v1.1/bench/vhdl/UDP_TX_tb.vhd
0,0 → 1,219
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:43:49 06/10/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_TX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: UDP_TX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
ENTITY UDP_TX_tb IS
END UDP_TX_tb;
ARCHITECTURE behavior OF UDP_TX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
END COMPONENT;
 
--Inputs
signal udp_tx_start : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal udp_txi : udp_tx_type;
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
--Outputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
signal udp_tx_result : std_logic_vector (1 downto 0);
signal udp_tx_data_out_ready : std_logic;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UDP_TX PORT MAP (
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready,
clk => clk,
reset => reset,
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
udp_tx_start <= '0';
 
udp_txi.hdr.dst_ip_addr <= (others => '0');
udp_txi.hdr.dst_port <= (others => '0');
udp_txi.hdr.src_port <= (others => '0');
udp_txi.hdr.data_length <= (others => '0');
udp_txi.hdr.checksum <= (others => '0');
udp_txi.data.data_out_last <= '0';
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert ip_tx_start = '0' report "ip_tx_start not initialised correctly on reset";
assert ip_tx.data.data_out_valid = '0' report "ip_tx.data.data_out_valid not initialised correctly on reset";
assert ip_tx.data.data_out_last = '0' report "ip_tx.data.data_out_last not initialised correctly on reset";
assert udp_tx_result = UDPTX_RESULT_NONE report "udp_tx_result not initialised correctly on reset";
 
-- insert stimulus here
 
wait for clk_period*5;
------------
-- TEST 1 -- basic functional tx test
------------
report "T1: basic functional tx test - send 56, 57, 58 to port 8532";
udp_txi.hdr.dst_ip_addr <= x"c0123478";
udp_txi.hdr.dst_port <= x"1467";
udp_txi.hdr.src_port <= x"8532";
udp_txi.hdr.data_length <= x"0003";
 
udp_tx_start <= '1';
ip_tx_data_out_ready <= '1'; -- IP layer can accept data
wait for clk_period;
udp_tx_start <= '0'; wait for clk_period;
ip_tx_result <= IPTX_RESULT_NONE;
assert udp_tx_result = UDPTX_RESULT_SENDING report "T1: result should be UDPTX_RESULT_SENDING";
wait until udp_tx_data_out_ready = '1';
-- start to tx IP data
udp_txi.data.data_out_valid <= '1';
udp_txi.data.data_out <= x"56"; wait for clk_period;
udp_txi.data.data_out <= x"57"; wait for clk_period;
udp_txi.data.data_out <= x"58";
udp_txi.data.data_out_last <= '1';
wait for clk_period;
 
assert ip_tx.data.data_out_last = '1' report "T1: ip_tx.datda_out_last not set on last byte";
 
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
wait for clk_period*2;
ip_tx_result <= IPTX_RESULT_SENT;
 
assert udp_tx_result = UDPTX_RESULT_SENT report "T1: result should be UDPTX_RESULT_SENT";
wait for clk_period*2;
 
------------
-- TEST 2 -- 2nd pkt
------------
report "T2: send a second pkt - 56,57,58,59 to port 8532";
udp_txi.hdr.dst_ip_addr <= x"c0123475";
udp_txi.hdr.dst_port <= x"1467";
udp_txi.hdr.src_port <= x"8532";
udp_txi.hdr.data_length <= x"0005";
 
udp_tx_start <= '1';
ip_tx_data_out_ready <= '1'; -- IP layer can accept data
wait for clk_period;
udp_tx_start <= '0'; wait for clk_period;
assert udp_tx_result = UDPTX_RESULT_SENDING report "T1: result should be UDPTX_RESULT_SENDING";
wait until udp_tx_data_out_ready = '1';
-- start to tx IP data
udp_txi.data.data_out_valid <= '1';
udp_txi.data.data_out <= x"56"; wait for clk_period;
udp_txi.data.data_out <= x"57"; wait for clk_period;
udp_txi.data.data_out <= x"58"; wait for clk_period;
udp_txi.data.data_out <= x"59"; wait for clk_period;
udp_txi.data.data_out <= x"5a";
udp_txi.data.data_out_last <= '1';
wait for clk_period;
assert ip_tx.data.data_out_last = '1' report "T1: ip_tx.datda_out_last not set on last byte";
 
udp_txi.data.data_out_valid <= '0';
udp_txi.data.data_out_last <= '0';
wait for clk_period*2;
 
assert udp_tx_result = UDPTX_RESULT_SENT report "T1: result should be UDPTX_RESULT_SENT";
wait for clk_period*2;
 
report "--- end of tests ---";
 
wait;
end process;
 
END;
/v1.1/rtl/vhdl/IPv4.vhd
0,0 → 1,152
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX and TX
-- doesnt handle seg & reass
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not IP
-- Ignore pkts that are not addressed to us--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_data_out_first
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity IPv4 is
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4;
 
architecture structural of IPv4 is
 
COMPONENT IPv4_TX
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
 
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
 
COMPONENT IPv4_RX
PORT(
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC -- indicates last data in frame
);
END COMPONENT;
 
begin
 
TX : IPv4_TX PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready=> ip_tx_data_out_ready,
clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
mac_data_out_ready => mac_data_out_ready,
mac_data_out_valid => mac_data_out_valid,
mac_data_out_first => mac_data_out_first,
mac_data_out_last => mac_data_out_last,
mac_data_out => mac_data_out
);
 
RX : IPv4_RX PORT MAP (
ip_rx => ip_rx,
ip_rx_start => ip_rx_start,
clk => rx_clk,
reset => reset,
our_ip_address => our_ip_address,
rx_pkt_count => rx_pkt_count,
mac_data_in => mac_data_in,
mac_data_in_valid => mac_data_in_valid,
mac_data_in_last => mac_data_in_last
);
 
 
end structural;
 
/v1.1/rtl/vhdl/arp.vhd
0,0 → 1,720
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in cache
-- request cache fill through ARP protocol if required
-- cache is simple 1 deep
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added req for mac tx and wait for grant
-- Revision 0.03 - Added data_out_first
 
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.arp_types.all;
 
entity arp is
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
end arp;
 
architecture Behavioral of arp is
 
type req_state_type is (IDLE,LOOKUP,REQUEST,WAIT_REPLY);
type rx_state_type is (IDLE,PARSE,PROCESS_ARP,WAIT_END);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST,INCR,HOLD);
type arp_oper_type is (NOP,REQUEST,REPLY);
type set_clr_type is (SET, CLR, HOLD);
 
type tx_state_type is (IDLE,WAIT_MAC,SEND);
type arp_entry_type is record
ip : std_logic_vector (31 downto 0);
mac : std_logic_vector (47 downto 0);
is_valid : std_logic;
reply_required : std_logic;
end record;
-- state variables
signal req_state : req_state_type;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal mac_addr_found : STD_LOGIC_VECTOR (47 downto 0); -- mac address found
signal mac_addr_valid_reg: std_logic;
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal rx_state : rx_state_type;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_type;
signal arp_req_count : unsigned (7 downto 0);
signal arp_entry : arp_entry_type; -- arp entry store
signal new_arp_entry : arp_entry_type;
signal tx_state : tx_state_type;
signal tx_count : unsigned (7 downto 0);
 
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
 
-- requester control signals
signal next_req_state : req_state_type;
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal set_mac_addr : std_logic;
signal set_mac_addr_invalid : std_logic;
signal set_send_req : std_logic;
signal clear_send_req : std_logic;
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : count_mode_type;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_arp_entry_request : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
 
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal tx_count_mode : count_mode_type;
signal clear_reply_req : std_logic;
signal set_chn_reqd : set_clr_type;
signal kill_data_out_valid : std_logic;
 
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : STD_LOGIC_VECTOR; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
 
begin
req_combinatorial : process (
-- input signals
arp_req_req,
-- state variables
req_state, req_ip_addr, mac_addr_found, mac_addr_valid_reg, send_request_needed, arp_entry,
-- control signals
next_req_state, set_req_state, set_req_ip, set_mac_addr,set_mac_addr_invalid,set_send_req, clear_send_req)
begin
-- set output followers
arp_req_rslt.got_err <= '0'; -- errors not returned in this version
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry.mac;
else
arp_req_rslt.got_mac <= mac_addr_valid_reg;
arp_req_rslt.mac <= mac_addr_found;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
set_mac_addr <= '0';
set_mac_addr_invalid <= '0';
set_send_req <= '0';
clear_send_req <= '0';
-- REQ FSM
case req_state is
when IDLE =>
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if arp_req_req.ip = arp_entry.ip and arp_entry.is_valid = '1' then
-- already have this IP
set_mac_addr <= '1';
else
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
set_mac_addr_invalid <= '1';
end if;
end if;
 
when LOOKUP =>
if arp_entry.ip = req_ip_addr and arp_entry.is_valid = '1' then
-- already have this IP
next_req_state <= IDLE;
set_req_state <= '1';
set_mac_addr <= '1';
else
-- need to request mac for this IP
next_req_state <= REQUEST;
set_req_state <= '1';
set_send_req <= '1';
end if;
when REQUEST =>
clear_send_req <= '1';
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when WAIT_REPLY =>
if arp_entry.is_valid = '1' then
-- have reply, go back to LOOKUP state to see if it is the right one
next_req_state <= LOOKUP;
set_req_state <= '1';
end if;
-- TODO: add timeout here
 
end case;
end process;
 
req_sequential : process (data_in_clk,reset)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
send_request_needed <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
 
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= arp_req_req.ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- send request to TX&RX FSMs to send an ARP request
if set_send_req = '1' then
send_request_needed <= '1';
elsif clear_send_req = '1' then
send_request_needed <= '0';
else
send_request_needed <= send_request_needed;
end if;
-- Set the found mac address
if set_mac_addr = '1' then
mac_addr_found <= arp_entry.mac;
mac_addr_valid_reg <= '1';
elsif set_mac_addr_invalid = '1' then
mac_addr_found <= (others => '0');
mac_addr_valid_reg <= '0';
else
mac_addr_found <= mac_addr_found;
mac_addr_valid_reg <= mac_addr_valid_reg;
end if;
end if;
end if;
end process;
 
 
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval,set_mac5,set_mac4,set_mac3,set_mac2,set_mac1,set_mac0,set_ip3,set_ip2,set_ip1,set_ip0, set_err_data,
set_arp_entry_request)
begin
-- set output followers
req_count <= STD_LOGIC_VECTOR(arp_req_count);
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_arp_entry_request <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
 
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 42 then
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in,rx_count,our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
end if;
end case;
 
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
when REPLY =>
set_arp_entry_request <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
end case;
 
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
 
rx_sequential : process (data_in_clk)
begin
if rising_edge(data_in_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
-- reset arp entry store
arp_entry.ip <= x"00000000";
arp_entry.mac <= x"000000000000";
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
 
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if set_arp_entry_request = '1' then
-- copy info from new entry to arp_entry and set reply required
arp_entry.mac <= new_arp_entry.mac;
arp_entry.ip <= new_arp_entry.ip;
arp_entry.is_valid <= '1';
if arp_operation = REQUEST then
arp_entry.reply_required <= '1';
else
arp_entry.reply_required <= '0';
end if;
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
elsif clear_reply_req = '1' then
-- note: clear_reply_req is set by tx logic, but handled in the clk domain of the rx
-- maintain arp entry state, but reset the reply required flag
arp_entry.mac <= arp_entry.mac;
arp_entry.ip <= arp_entry.ip;
arp_entry.is_valid <= arp_entry.is_valid;
arp_entry.reply_required <= '0';
arp_req_count <= arp_req_count;
elsif send_request_needed = '1' then
-- set up the arp entry to take the request to be transmitted out by the TX FSM
arp_entry.ip <= req_ip_addr;
arp_entry.mac <= (others => '0');
arp_entry.is_valid <= '0';
arp_entry.reply_required <= '0';
else
arp_entry <= arp_entry;
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
 
tx_combinatorial : process (
-- input signals
data_out_ready, send_request_needed, mac_tx_granted, our_mac_address, our_ip_address,
-- state variables
tx_state, tx_count, tx_mac_chn_reqd, arp_entry,
-- control signals
next_rx_state, set_rx_state, tx_count_mode, kill_data_out_valid,
set_chn_reqd, clear_reply_req)
begin
-- set output followers
mac_tx_req <= tx_mac_chn_reqd;
-- set initial values for combinatorial outputs
data_out_first <= '0';
case tx_state is
when SEND =>
if data_out_ready = '1' and kill_data_out_valid = '0' then
data_out_valid <= '1';
else
data_out_valid <= '0';
end if;
when OTHERS => data_out_valid <= '0';
end case;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
data_out <= x"00";
data_out_last <= '0';
clear_reply_req <= '0';
set_chn_reqd <= HOLD;
kill_data_out_valid <= '0';
-- TX FSM
case tx_state is
when IDLE =>
tx_count_mode <= RST;
if arp_entry.reply_required = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
elsif send_request_needed = '1' then
set_chn_reqd <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
else
set_chn_reqd <= CLR;
end if;
 
when WAIT_MAC =>
tx_count_mode <= RST;
if mac_tx_granted = '1' then
next_tx_state <= SEND;
set_tx_state <= '1';
end if;
-- TODO - should handle timeout here
when SEND =>
if data_out_ready = '1' then
tx_count_mode <= INCR;
end if;
case tx_count is
when x"00" =>
data_out_first <= data_out_ready;
data_out <= x"ff"; -- dst = broadcast
when x"01" => data_out <= x"ff";
when x"02" => data_out <= x"ff";
when x"03" => data_out <= x"ff";
when x"04" => data_out <= x"ff";
when x"05" => data_out <= x"ff";
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac
when x"07" => data_out <= our_mac_address (39 downto 32);
when x"08" => data_out <= our_mac_address (31 downto 24);
when x"09" => data_out <= our_mac_address (23 downto 16);
when x"0a" => data_out <= our_mac_address (15 downto 8);
when x"0b" => data_out <= our_mac_address (7 downto 0);
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP
when x"0d" => data_out <= x"06";
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth
when x"0f" => data_out <= x"01";
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip
when x"11" => data_out <= x"00";
when x"12" => data_out <= x"06"; -- HW size = 06
when x"13" => data_out <= x"04"; -- prot size = 04
when x"14" => data_out <= x"00"; -- opcode =
when x"15" =>
if arp_entry.is_valid = '1' then
data_out <= x"02"; -- 02 : REPLY if arp_entry valid
else
data_out <= x"01"; -- 01 : REQ if arp_entry invalid
end if;
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac
when x"17" => data_out <= our_mac_address (39 downto 32);
when x"18" => data_out <= our_mac_address (31 downto 24);
when x"19" => data_out <= our_mac_address (23 downto 16);
when x"1a" => data_out <= our_mac_address (15 downto 8);
when x"1b" => data_out <= our_mac_address (7 downto 0);
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip
when x"1d" => data_out <= our_ip_address (23 downto 16);
when x"1e" => data_out <= our_ip_address (15 downto 8);
when x"1f" => data_out <= our_ip_address (7 downto 0);
when x"20" => data_out <= arp_entry.mac (47 downto 40); -- target mac
when x"21" => data_out <= arp_entry.mac (39 downto 32);
when x"22" => data_out <= arp_entry.mac (31 downto 24);
when x"23" => data_out <= arp_entry.mac (23 downto 16);
when x"24" => data_out <= arp_entry.mac (15 downto 8);
when x"25" => data_out <= arp_entry.mac (7 downto 0);
when x"26" => data_out <= arp_entry.ip (31 downto 24); -- target ip
when x"27" => data_out <= arp_entry.ip (23 downto 16);
when x"28" => data_out <= arp_entry.ip (15 downto 8);
when x"29" =>
data_out <= arp_entry.ip(7 downto 0);
data_out_last <= '1';
when x"2a" =>
clear_reply_req <= '1'; -- reset the reply request (done in the rx clk process domain)
kill_data_out_valid <= '1'; -- data is no longer valid
next_tx_state <= IDLE;
set_tx_state <= '1';
 
when others =>
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end case;
end process;
 
tx_sequential : process (data_out_clk,reset)
begin
if rising_edge(data_out_clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_mac_chn_reqd <= '0';
else
-- Next rx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx_count processing
case tx_count_mode is
when RST =>
tx_count <= x"00";
when INCR =>
tx_count <= tx_count + 1;
when HOLD =>
tx_count <= tx_count;
end case;
 
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
end if;
end if;
end process;
 
 
end Behavioral;
 
/v1.1/rtl/vhdl/ml605/IP_complete.vhd
0,0 → 1,251
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 20:25:56 06/03/2011
-- Design Name:
-- Module Name: IP_complete - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP and MAC
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity IP_complete is
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
clk_out : out std_logic;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- GMII Interface
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end IP_complete;
 
architecture structural of IP_complete is
 
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
 
COMPONENT IP_complete_nomac
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
 
 
------------------------------------------------------------------------------
-- Component Declaration for the MAC layer
------------------------------------------------------------------------------
component mac_layer
port (
-- System controls
------------------
glbl_rst : in std_logic; -- asynchronous reset
mac_reset : in std_logic; -- reset mac layer
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
-- MAC Transmitter (AXI-S) Interface
---------------------------------------------
mac_tx_clock : out std_logic; -- data sampled on rising edge
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : in std_logic; -- tdata is valid
mac_tx_tready : out std_logic; -- mac is ready to accept data
mac_tx_tlast : in std_logic; -- indicates last byte of frame
 
-- MAC Receiver (AXI-S) Interface
------------------------------------------
mac_rx_clock : out std_logic; -- data valid on rising edge
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : out std_logic; -- indicates tdata is valid
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : out std_logic; -- indicates last byte of the trame
-- GMII Interface
-----------------
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end component;
 
---------------------------
-- Signals
---------------------------
-- MAC RX bus
signal mac_rx_clock : std_logic;
signal mac_rx_tdata : std_logic_vector (7 downto 0);
signal mac_rx_tvalid : std_logic;
signal mac_rx_tready : std_logic;
signal mac_rx_tlast : std_logic;
-- MAC TX bus
signal mac_tx_clock : std_logic;
signal mac_tx_tdata : std_logic_vector (7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tready : std_logic;
signal mac_tx_tlast : std_logic;
-- control signals
signal mac_tx_tready_int : std_logic;
signal mac_tx_granted_int : std_logic;
 
begin
 
clk_out <= mac_rx_clock;
 
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
 
IP_layer : IP_complete_nomac PORT MAP
(
-- IP Layer signals
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
-- system signals
rx_clk => mac_rx_clock,
tx_clk => mac_rx_clock,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tready => mac_tx_tready_int,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tfirst => open,
mac_tx_tlast => mac_tx_tlast,
mac_tx_tdata => mac_tx_tdata,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
 
------------------------------------------------------------------------------
-- Instantiate the MAC layer
------------------------------------------------------------------------------
mac_block : mac_layer
Port map(
-- System controls
------------------
glbl_rst => reset,
mac_reset => '0',
clk_in_p => clk_in_p,
clk_in_n => clk_in_n,
-- MAC Transmitter (AXI-S) Interface
---------------------------------------------
mac_tx_clock => mac_tx_clock,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready_int,
mac_tx_tlast => mac_tx_tlast,
 
-- MAC Receiver (AXI-S) Interface
------------------------------------------
mac_rx_clock => mac_rx_clock,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast,
-- GMII Interface
-----------------
phy_resetn => phy_resetn,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
gmii_col => gmii_col,
gmii_crs => gmii_crs,
mii_tx_clk => mii_tx_clk
);
 
end structural;
 
/v1.1/rtl/vhdl/ml605/UDP_Complete.vhd
0,0 → 1,269
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:51:18 06/11/2011
-- Design Name:
-- Module Name: UDP_Complete - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity UDP_Complete is
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
clk_out : out std_logic;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- GMII Interface
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end UDP_Complete;
 
architecture structural of UDP_Complete is
 
------------------------------------------------------------------------------
-- Component Declaration for UDP complete no mac
------------------------------------------------------------------------------
 
COMPONENT UDP_Complete_nomac
PORT(
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
 
 
------------------------------------------------------------------------------
-- Component Declaration for the MAC layer
------------------------------------------------------------------------------
component mac_layer
port (
-- System controls
------------------
glbl_rst : in std_logic; -- asynchronous reset
mac_reset : in std_logic; -- reset mac layer
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
-- MAC Transmitter (AXI-S) Interface
---------------------------------------------
mac_tx_clock : out std_logic; -- data sampled on rising edge
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : in std_logic; -- tdata is valid
mac_tx_tready : out std_logic; -- mac is ready to accept data
mac_tx_tlast : in std_logic; -- indicates last byte of frame
 
-- MAC Receiver (AXI-S) Interface
------------------------------------------
mac_rx_clock : out std_logic; -- data valid on rising edge
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : out std_logic; -- indicates tdata is valid
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : out std_logic; -- indicates last byte of the trame
-- GMII Interface
-----------------
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end component;
 
 
---------------------------
-- Signals
---------------------------
-- MAC RX bus
signal mac_rx_clock : std_logic;
signal mac_rx_tdata : std_logic_vector (7 downto 0);
signal mac_rx_tvalid : std_logic;
signal mac_rx_tready : std_logic;
signal mac_rx_tlast : std_logic;
-- MAC TX bus
signal mac_tx_clock : std_logic;
signal mac_tx_tdata : std_logic_vector (7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tready : std_logic;
signal mac_tx_tlast : std_logic;
-- control signals
signal mac_tx_tready_int : std_logic;
signal mac_tx_granted_int : std_logic;
 
 
begin
 
 
process (mac_tx_clock)
begin
-- output followers
clk_out <= mac_tx_clock;
end process;
 
------------------------------------------------------------------------------
-- Instantiate the UDP layer
------------------------------------------------------------------------------
 
udp_block: UDP_Complete_nomac PORT MAP (
-- UDP TX signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready,
-- UDP RX signals
udp_rx_start => udp_rx_start,
udp_rxo => udp_rxo,
-- IP RX signals
ip_rx_hdr => ip_rx_hdr,
-- system signals
rx_clk => mac_rx_clock,
tx_clk => mac_tx_clock,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
 
-- MAC Transmitter
mac_tx_tready => mac_tx_tready_int,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tfirst => open,
mac_tx_tlast => mac_tx_tlast,
mac_tx_tdata => mac_tx_tdata,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
 
 
------------------------------------------------------------------------------
-- Instantiate the MAC layer
------------------------------------------------------------------------------
mac_block : mac_layer
Port map(
-- System controls
------------------
glbl_rst => reset,
mac_reset => '0',
clk_in_p => clk_in_p,
clk_in_n => clk_in_n,
-- MAC Transmitter (AXI-S) Interface
---------------------------------------------
mac_tx_clock => mac_tx_clock,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready_int,
mac_tx_tlast => mac_tx_tlast,
 
-- MAC Receiver (AXI-S) Interface
------------------------------------------
mac_rx_clock => mac_rx_clock,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast,
-- GMII Interface
-----------------
phy_resetn => phy_resetn,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
gmii_col => gmii_col,
gmii_crs => gmii_crs,
mii_tx_clk => mii_tx_clk
);
 
 
end structural;
 
/v1.1/rtl/vhdl/ml605/UDP_integration_example.vhd
0,0 → 1,367
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:01:00 06/11/2011
-- Design Name:
-- Module Name: UDP_integration_example - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity UDP_integration_example is
port (
-- System signals
------------------
reset : in std_logic; -- asynchronous reset
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
 
-- System controls
------------------
PBTX : in std_logic;
UDP_RX : out std_logic;
UDP_Start : out std_logic;
PBTX_LED : out std_logic;
TX_Started : out std_logic;
TX_Completed : out std_logic;
reset_leds : in std_logic;
display : out std_logic_vector(7 downto 0);
-- GMII Interface
-----------------
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end UDP_integration_example;
 
architecture Behavioral of UDP_integration_example is
 
------------------------------------------------------------------------------
-- Component Declaration for the complete IP layer
------------------------------------------------------------------------------
component UDP_Complete
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
clk_out : out std_logic;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- GMII Interface
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end component;
 
 
type state_type is (IDLE, DATA_OUT);
type count_mode_type is (RST, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
-- system signals
signal clk_int : std_logic;
signal our_mac : STD_LOGIC_VECTOR (47 downto 0);
signal our_ip : STD_LOGIC_VECTOR (31 downto 0);
signal udp_tx_int : udp_tx_type;
signal udp_tx_result_int : std_logic_vector (1 downto 0);
signal udp_tx_data_out_ready_int : std_logic;
signal udp_rx_int : udp_rx_type;
signal udp_tx_start_int : std_logic;
signal udp_rx_start_int : std_logic;
signal arp_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
signal ip_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
signal ip_rx_hdr_int : ipv4_rx_header_type;
-- state signals
signal state : state_type;
signal count : unsigned (7 downto 0);
signal tx_hdr : udp_tx_header_type;
signal tx_start_reg : std_logic;
signal tx_started_reg : std_logic;
signal tx_fin_reg : std_logic;
signal udp_rx_start_reg : std_logic;
-- control signals
signal next_state : state_type;
signal set_state : std_logic;
signal set_count : count_mode_type;
signal set_hdr : std_logic;
signal set_tx_start : set_clr_type;
signal set_last : std_logic;
signal set_tx_started : set_clr_type;
signal set_tx_fin : set_clr_type;
signal set_udp_rx_start_reg : set_clr_type;
begin
 
process (
our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg,
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
reset, tx_started_reg, tx_fin_reg, tx_start_reg
)
begin
-- set up our local addresses
our_ip <= x"c0a80509"; -- 192.168.5.9
our_mac <= x"002320212223";
-- determine RX good and error LEDs
if udp_rx_int.hdr.is_valid = '1' then
UDP_RX <= '1';
else
UDP_RX <= '0';
end if;
UDP_Start <= udp_rx_start_reg;
TX_Started <= tx_start_reg; --tx_started_reg;
TX_Completed <= tx_fin_reg;
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
end process;
-- AUTO TX process - on receipt of any UDP pkt, send a response
-- TX response process - COMB
tx_proc_combinatorial: process(
-- inputs
udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX, reset_leds,
-- state
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg,
-- controls
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
set_tx_started, set_tx_fin, set_udp_rx_start_reg
)
begin
-- set output_followers
udp_tx_int.hdr <= tx_hdr;
udp_tx_int.data.data_out_last <= set_last;
udp_tx_start_int <= tx_start_reg;
 
-- set control signal defaults
next_state <= IDLE;
set_state <= '0';
set_count <= HOLD;
set_hdr <= '0';
set_tx_start <= HOLD;
set_last <= '0';
set_tx_started <= HOLD;
set_tx_fin <= HOLD;
set_udp_rx_start_reg <= HOLD;
-- FSM
case state is
when IDLE =>
udp_tx_int.data.data_out <= (others => '0');
udp_tx_int.data.data_out_valid <= '0';
if udp_rx_start_int = '1' or PBTX = '1' then
set_udp_rx_start_reg <= SET;
set_tx_started <= SET;
set_hdr <= '1';
set_tx_start <= SET;
set_tx_fin <= CLR;
set_count <= RST;
next_state <= DATA_OUT;
set_state <= '1';
elsif reset_leds = '1' then
set_udp_rx_start_reg <= CLR;
set_tx_started <= CLR;
set_tx_fin <= CLR;
end if;
when DATA_OUT =>
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
if udp_tx_data_out_ready_int = '1' then
set_tx_start <= CLR;
if unsigned(count) = x"03" then
set_last <= '1';
set_tx_fin <= SET;
set_tx_started <= CLR;
next_state <= IDLE;
set_state <= '1';
else
set_count <= INCR;
end if;
end if;
end case;
end process;
 
-- TX response process - SEQ
tx_proc_sequential: process(clk_int)
begin
if rising_edge(clk_int) then
if reset = '1' then
-- reset state variables
state <= IDLE;
count <= x"00";
tx_start_reg <= '0';
tx_hdr.dst_ip_addr <= (others => '0');
tx_hdr.dst_port <= (others => '0');
tx_hdr.src_port <= (others => '0');
tx_hdr.data_length <= (others => '0');
tx_hdr.checksum <= (others => '0');
tx_started_reg <= '0';
tx_fin_reg <= '0';
PBTX_LED <= '0';
else
PBTX_LED <= PBTX;
-- Next rx_state processing
if set_state = '1' then
state <= next_state;
else
state <= state;
end if;
-- count processing
case set_count is
when RST => count <= x"00";
when INCR => count <= count + 1;
when HOLD => count <= count;
end case;
-- set tx hdr
if set_hdr = '1' then
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
tx_hdr.data_length <= x"0004";
tx_hdr.checksum <= x"0000";
else
tx_hdr <= tx_hdr;
end if;
-- set tx start signal
case set_tx_start is
when SET => tx_start_reg <= '1';
when CLR => tx_start_reg <= '0';
when HOLD => tx_start_reg <= tx_start_reg;
end case;
 
-- set tx started signal
case set_tx_started is
when SET => tx_started_reg <= '1';
when CLR => tx_started_reg <= '0';
when HOLD => tx_started_reg <= tx_started_reg;
end case;
 
-- set tx finished signal
case set_tx_fin is
when SET => tx_fin_reg <= '1';
when CLR => tx_fin_reg <= '0';
when HOLD => tx_fin_reg <= tx_fin_reg;
end case;
 
-- set UDP START signal
case set_udp_rx_start_reg is
when SET => udp_rx_start_reg <= '1';
when CLR => udp_rx_start_reg <= '0';
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
end case;
end if;
end if;
 
end process;
------------------------------------------------------------------------------
-- Instantiate the UDP layer
------------------------------------------------------------------------------
UDP_block : UDP_Complete PORT MAP
(
-- UDP interface
udp_tx_start => udp_tx_start_int,
udp_txi => udp_tx_int,
udp_tx_result => udp_tx_result_int,
udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
udp_rx_start => udp_rx_start_int,
udp_rxo => udp_rx_int,
-- IP RX signals
ip_rx_hdr => ip_rx_hdr_int,
-- System interface
clk_in_p => clk_in_p,
clk_in_n => clk_in_n,
clk_out => clk_int,
reset => reset,
our_ip_address => our_ip,
our_mac_address => our_mac,
-- status signals
arp_pkt_count => arp_pkt_count_int,
ip_pkt_count => ip_pkt_count_int,
-- GMII Interface
-----------------
phy_resetn => phy_resetn,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
gmii_col => gmii_col,
gmii_crs => gmii_crs,
mii_tx_clk => mii_tx_clk
);
 
 
end Behavioral;
 
/v1.1/rtl/vhdl/ml605/udp_constraints.ucf
0,0 → 1,76
CONFIG PART = xc6vlx240tff1156-1;
 
 
########## ML605 Board ##########
NET clk_in_p LOC = J9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
NET clk_in_n LOC = H9 |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE;
 
Net reset LOC = H10 |IOSTANDARD = LVCMOS15 |TIG;
 
# downgrade the Place:1153 error in the mapper
NET "reset" CLOCK_DEDICATED_ROUTE = FALSE;
 
#### Module LEDs_8Bit constraints
NET "display[0]" LOC = AC22;
NET "display[1]" LOC = AC24;
NET "display[2]" LOC = AE22;
NET "display[3]" LOC = AE23;
NET "display[4]" LOC = AB23;
NET "display[5]" LOC = AG23;
NET "display[6]" LOC = AE24;
NET "display[7]" LOC = AD24;
 
NET PBTX_LED LOC = AD21;
 
#### Module Push_Buttons_4Bit constraints
NET PBTX LOC = H17;
NET reset_leds LOC = G26;
 
#### Module DIP_Switches_4Bit constraints
 
 
Net phy_resetn LOC = AH13 |IOSTANDARD = LVCMOS25 |TIG;
 
Net gmii_rxd<7> LOC = AC13 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<6> LOC = AC12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<5> LOC = AD11 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<4> LOC = AM12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<3> LOC = AN12 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<2> LOC = AE14 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<1> LOC = AF14 |IOSTANDARD = LVCMOS25;
Net gmii_rxd<0> LOC = AN13 |IOSTANDARD = LVCMOS25;
 
Net gmii_txd<7> LOC = AF11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<6> LOC = AE11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<5> LOC = AM10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<4> LOC = AL10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<3> LOC = AG11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<2> LOC = AG10 |IOSTANDARD = LVCMOS25;
Net gmii_txd<1> LOC = AL11 |IOSTANDARD = LVCMOS25;
Net gmii_txd<0> LOC = AM11 |IOSTANDARD = LVCMOS25;
 
Net gmii_col LOC = AK13 |IOSTANDARD = LVCMOS25;
Net gmii_crs LOC = AL13 |IOSTANDARD = LVCMOS25;
Net mii_tx_clk LOC = AD12 |IOSTANDARD = LVCMOS25;
 
Net gmii_tx_en LOC = AJ10 |IOSTANDARD = LVCMOS25;
Net gmii_tx_er LOC = AH10 |IOSTANDARD = LVCMOS25;
Net gmii_tx_clk LOC = AH12 |IOSTANDARD = LVCMOS25;
 
Net gmii_rx_dv LOC = AM13 |IOSTANDARD = LVCMOS25;
Net gmii_rx_er LOC = AG12 |IOSTANDARD = LVCMOS25;
# P20 - GCLK7
Net gmii_rx_clk LOC = AP11 |IOSTANDARD = LVCMOS25;
 
 
 
NET "clk_in_p" TNM_NET = "clk_in_p";
TIMESPEC "TS_emac1_clk_in_p" = PERIOD "clk_in_p" 5.000 ns HIGH 50% INPUT_JITTER 50.0ps;
 
 
# Ethernet GTX_CLK high quality 125 MHz reference clock
NET "*mac_block/gtx_clk_bufg" TNM_NET = "ref_gtx_clk";
TIMEGRP "emac1_clk_ref_gtx" = "ref_gtx_clk";
TIMESPEC TS_emac1_clk_ref_gtx = PERIOD "N/A" 8 ns HIGH 50%;
 
 
/v1.1/rtl/vhdl/tx_arbitrator.vhd
0,0 → 1,116
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between two sources that want to transmit onto a bus
-- handles arbitration and multiplexing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.03 - Added first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity tx_arbitrator is
port (
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
 
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end tx_arbitrator;
 
architecture Behavioral of tx_arbitrator is
 
type grant_type is (M1,M2);
 
signal grant : grant_type;
begin
combinatorial : process (
grant,
data_1, valid_1, first_1, last_1,
data_2, valid_2, first_2, last_2
)
begin
-- grant outputs
case grant is
when M1 =>
grant_1 <= '1';
grant_2 <= '0';
when M2 =>
grant_1 <= '0';
grant_2 <= '1';
end case;
-- multiplexer
if grant = M1 then
data <= data_1;
valid <= valid_1;
first <= first_1;
last <= last_1;
else
data <= data_2;
valid <= valid_2;
first <= first_2;
last <= last_2;
end if;
end process;
sequential : process (clk, reset, req_1, req_2, grant)
begin
if rising_edge(clk) then
if reset = '1' then
grant <= M1;
else
case grant is
when M1 =>
if req_1 = '1' then
grant <= M1;
elsif req_2 = '1' then
grant <= M2;
end if;
when M2 =>
if req_2 = '1' then
grant <= M2;
else
grant <= M1;
end if;
end case;
end if;
end if;
end process;
 
 
end Behavioral;
 
/v1.1/rtl/vhdl/IP_complete_nomac.vhd
0,0 → 1,284
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP (but no MAC)
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity IP_complete_nomac is
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end IP_complete_nomac;
 
architecture structural of IP_complete_nomac is
 
COMPONENT IPv4
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
COMPONENT arp
PORT(
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
END COMPONENT;
COMPONENT tx_arbitrator
PORT(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
 
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
END COMPONENT;
---------------------------
-- Signals
---------------------------
-- ARP REQUEST
signal arp_req_req_int : arp_req_req_type;
signal arp_req_rslt_int : arp_req_rslt_type;
-- MAC arbitration busses
signal ip_mac_req : std_logic;
signal ip_mac_grant : std_logic;
signal ip_mac_data_out : std_logic_vector (7 downto 0);
signal ip_mac_valid : std_logic;
signal ip_mac_first : std_logic;
signal ip_mac_last : std_logic;
signal arp_mac_req : std_logic;
signal arp_mac_grant : std_logic;
signal arp_mac_data_out : std_logic_vector (7 downto 0);
signal arp_mac_valid : std_logic;
signal arp_mac_first : std_logic;
signal arp_mac_last : std_logic;
-- MAC RX bus
signal mac_rx_tready_int : std_logic;
-- MAC TX bus
signal mac_tx_tdata_int : std_logic_vector (7 downto 0);
signal mac_tx_tvalid_int : std_logic;
signal mac_tx_tfirst_int : std_logic;
signal mac_tx_tlast_int : std_logic;
-- control signals
signal mac_tx_granted_int : std_logic;
 
begin
 
mac_rx_tready_int <= '1'; -- enable the mac receiver
-- set followers
mac_tx_tdata <= mac_tx_tdata_int;
mac_tx_tvalid <= mac_tx_tvalid_int;
mac_tx_tfirst <= mac_tx_tfirst_int;
mac_tx_tlast <= mac_tx_tlast_int;
mac_rx_tready <= mac_rx_tready_int;
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
 
IP_layer : IPv4 PORT MAP
(
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready=> ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
rx_pkt_count => ip_pkt_count,
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
mac_tx_req => ip_mac_req,
mac_tx_granted => ip_mac_grant,
mac_data_out_ready => mac_tx_tready,
mac_data_out_valid => ip_mac_valid,
mac_data_out_first => ip_mac_first,
mac_data_out_last => ip_mac_last,
mac_data_out => ip_mac_data_out,
mac_data_in => mac_rx_tdata,
mac_data_in_valid => mac_rx_tvalid,
mac_data_in_last => mac_rx_tlast
);
------------------------------------------------------------------------------
-- Instantiate the ARP layer
------------------------------------------------------------------------------
arp_layer : arp
Port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
req_count => arp_pkt_count
);
 
 
------------------------------------------------------------------------------
-- Instantiate the TX Arbitrator
------------------------------------------------------------------------------
mac_tx_arb : tx_arbitrator
Port map(
clk => tx_clk,
reset => reset,
req_1 => ip_mac_req,
grant_1 => ip_mac_grant,
data_1 => ip_mac_data_out,
valid_1 => ip_mac_valid,
first_1 => ip_mac_first,
last_1 => ip_mac_last,
 
req_2 => arp_mac_req,
grant_2 => arp_mac_grant,
data_2 => arp_mac_data_out,
valid_2 => arp_mac_valid,
first_2 => arp_mac_first,
last_2 => arp_mac_last,
data => mac_tx_tdata_int,
valid => mac_tx_tvalid_int,
first => mac_tx_tfirst_int,
last => mac_tx_tlast_int
);
 
end structural;
 
/v1.1/rtl/vhdl/IPv4_TX.vhd
0,0 → 1,522
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP TX
-- doesnt handle segmentation
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - fixed up setting of tx_result control defaults
-- Revision 0.03 - Added data_out_first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity IPv4_TX is
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
 
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4_TX;
 
architecture Behavioral of IPv4_TX is
 
type tx_state_type is (
IDLE,
WAIT_MAC, -- waiting for response from ARP for mac lookup
WAIT_CHN, -- waiting for tx access to MAC channel
SEND_ETH_HDR, -- sending the ethernet header
SEND_IP_HDR, -- sending the IP header
SEND_USER_DATA -- sending the users data
);
type crc_state_type is (IDLE,TOT_LEN,ID,FLAGS,TTL,CKS,SAH,SAL,DAH,DAL,FINAL,WAIT_END);
 
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- Configuration
constant IP_TTL : std_logic_vector (7 downto 0) := x"80";
 
-- TX state variables
signal tx_state : tx_state_type;
signal tx_count : unsigned (11 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal tx_mac : std_logic_vector (47 downto 0);
signal tx_mac_chn_reqd : std_logic;
signal tx_hdr_cks : std_logic_vector (23 downto 0);
signal mac_lookup_req : std_logic;
signal crc_state : crc_state_type;
signal arp_req_ip_reg : std_logic_vector (31 downto 0);
signal mac_data_out_ready_reg : std_logic;
 
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal set_tx_mac : std_logic;
signal tx_count_val : unsigned (11 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_chn_reqd : set_clr_type;
signal set_mac_lku_req : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
FUNCTION inv_if_one(s1:std_logic_vector;en:std_logic) return std_logic_vector is
--this function inverts all the bits of a vector if
--'en' is '1'.
VARIABLE Z : std_logic_vector(s1'high downto s1'low);
BEGIN
FOR i IN (s1'low) to s1'high LOOP
Z(i) := en XOR s1(i);
END LOOP;
RETURN Z;
END inv_if_one; -- end function
 
 
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
ip_tx_start, ip_tx, clk, our_ip_address, our_mac_address, arp_req_rslt,
mac_tx_granted, mac_data_out_ready,
-- state variables
tx_state, tx_count, tx_result_reg, tx_mac, tx_mac_chn_reqd,
mac_lookup_req, tx_hdr_cks, arp_req_ip_reg, mac_data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, set_tx_mac, tx_count_mode,
tx_data, set_last, set_chn_reqd, set_mac_lku_req, total_length,
tx_data_valid, tx_count_val
)
begin
-- set output followers
ip_tx_result <= tx_result_reg;
mac_tx_req <= tx_mac_chn_reqd;
arp_req_req.lookup_req <= mac_lookup_req;
arp_req_req.ip <= arp_req_ip_reg;
-- set initial values for combinatorial outputs
mac_data_out_first <= '0';
case tx_state is
when SEND_ETH_HDR | SEND_IP_HDR =>
mac_data_out <= tx_data;
tx_data_valid <= mac_data_out_ready; -- generated internally
mac_data_out_last <= set_last;
when SEND_USER_DATA =>
mac_data_out <= ip_tx.data.data_out;
tx_data_valid <= ip_tx.data.data_out_valid;
mac_data_out_last <= ip_tx.data.data_out_last;
 
when others =>
mac_data_out <= (others => '0');
tx_data_valid <= '0'; -- not transmitting during this phase
mac_data_out_last <= '0';
end case;
mac_data_out_valid <= tx_data_valid and mac_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
set_tx_mac <= '0';
set_chn_reqd <= HOLD;
set_mac_lku_req <= HOLD;
next_tx_result <= IPTX_RESULT_NONE;
set_tx_result <= '0';
tx_count_val <= (others => '0');
-- set temp signals
total_length <= std_logic_vector(unsigned(ip_tx.hdr.data_length) + 20); -- total length = user data length + header length (bytes)
-- TX FSM
case tx_state is
when IDLE =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
set_chn_reqd <= CLR;
if ip_tx_start = '1' then
-- check header count for error if too high
if unsigned(ip_tx.hdr.data_length) > 1480 then
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
else
-- TODO - check if we already have the mac addr for this ip, if so, bypass the WAIT_MAC state
-- req the mac address for this ip
set_mac_lku_req <= SET;
next_tx_result <= IPTX_RESULT_SENDING;
set_tx_result <= '1';
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
end if;
else
set_mac_lku_req <= CLR;
end if;
 
when WAIT_MAC =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if arp_req_rslt.got_mac = '1' then
-- save the MAC we got back from the ARP lookup
set_tx_mac <= '1';
set_chn_reqd <= SET;
set_mac_lku_req <= CLR;
-- check for optimise when already have the channel
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
else
next_tx_state <= WAIT_CHN;
set_tx_state <= '1';
end if;
elsif arp_req_rslt.got_err = '1' then
set_mac_lku_req <= CLR;
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end if;
when WAIT_CHN =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
end if;
-- probably should handle a timeout here
when SEND_ETH_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"00d" then
tx_count_mode <= RST;
next_tx_state <= SEND_IP_HDR;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" =>
mac_data_out_first <= mac_data_out_ready;
tx_data <= tx_mac (47 downto 40); -- trg = mac from ARP lookup
when x"001" => tx_data <= tx_mac (39 downto 32);
when x"002" => tx_data <= tx_mac (31 downto 24);
when x"003" => tx_data <= tx_mac (23 downto 16);
when x"004" => tx_data <= tx_mac (15 downto 8);
when x"005" => tx_data <= tx_mac (7 downto 0);
when x"006" => tx_data <= our_mac_address (47 downto 40); -- src = our mac
when x"007" => tx_data <= our_mac_address (39 downto 32);
when x"008" => tx_data <= our_mac_address (31 downto 24);
when x"009" => tx_data <= our_mac_address (23 downto 16);
when x"00a" => tx_data <= our_mac_address (15 downto 8);
when x"00b" => tx_data <= our_mac_address (7 downto 0);
when x"00c" => tx_data <= x"08"; -- pkt type = 0800 : IP
when x"00d" => tx_data <= x"00";
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_IP_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"013" then
tx_count_val <= x"001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" => tx_data <= x"45"; -- v4, 5 words in hdr
when x"001" => tx_data <= x"00"; -- service type
when x"002" => tx_data <= total_length (15 downto 8); -- total length
when x"003" => tx_data <= total_length (7 downto 0);
when x"004" => tx_data <= x"00"; -- identification
when x"005" => tx_data <= x"00";
when x"006" => tx_data <= x"00"; -- flags and fragment offset
when x"007" => tx_data <= x"00";
when x"008" => tx_data <= IP_TTL; -- TTL
when x"009" => tx_data <= ip_tx.hdr.protocol; -- protocol
when x"00a" => tx_data <= tx_hdr_cks (15 downto 8); -- HDR checksum
when x"00b" => tx_data <= tx_hdr_cks (7 downto 0); -- HDR checksum
when x"00c" => tx_data <= our_ip_address (31 downto 24); -- src ip
when x"00d" => tx_data <= our_ip_address (23 downto 16);
when x"00e" => tx_data <= our_ip_address (15 downto 8);
when x"00f" => tx_data <= our_ip_address (7 downto 0);
when x"010" => tx_data <= ip_tx.hdr.dst_ip_addr (31 downto 24); -- dst ip
when x"011" => tx_data <= ip_tx.hdr.dst_ip_addr (23 downto 16);
when x"012" => tx_data <= ip_tx.hdr.dst_ip_addr (15 downto 8);
when x"013" => tx_data <= ip_tx.hdr.dst_ip_addr (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_USER_DATA =>
ip_tx_data_out_ready <= mac_data_out_ready and mac_data_out_ready_reg; -- in this state, we are always ready to accept user data for tx
if mac_data_out_ready = '1' then
if ip_tx.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_SENT;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
tx_data <= ip_tx.data.data_out;
end if;
end if;
end if;
 
end case;
end process;
 
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
 
tx_sequential : process (clk,reset,mac_data_out_ready_reg)
begin
if rising_edge(clk) then
mac_data_out_ready_reg <= mac_data_out_ready;
else
mac_data_out_ready_reg <= mac_data_out_ready_reg;
end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= x"000";
tx_result_reg <= IPTX_RESULT_NONE;
tx_mac <= (others => '0');
tx_mac_chn_reqd <= '0';
mac_lookup_req <= '0';
else
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- control arp lookup request
case set_mac_lku_req is
when SET =>
arp_req_ip_reg <= ip_tx.hdr.dst_ip_addr;
mac_lookup_req <= '1';
 
when CLR =>
mac_lookup_req <= '0';
arp_req_ip_reg <= arp_req_ip_reg;
when HOLD =>
mac_lookup_req <= mac_lookup_req;
arp_req_ip_reg <= arp_req_ip_reg;
end case;
-- save MAC
if set_tx_mac = '1' then
tx_mac <= arp_req_rslt.mac;
else
tx_mac <= tx_mac;
end if;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Process to calculate CRC in parallel with pkt out processing
-- this process must yield a valid CRC before it is required to be used in the hdr
-----------------------------------------------------------------------------
 
crc : process (clk,reset)
begin
if rising_edge(clk) then
case crc_state is
when IDLE =>
if ip_tx_start = '1' then
tx_hdr_cks <= x"004500"; -- vers & hdr len & service
crc_state <= TOT_LEN;
end if;
when TOT_LEN =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(total_length));
crc_state <= ID;
when ID =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= FLAGS;
when FLAGS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= TTL;
when TTL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(IP_TTL & ip_tx.hdr.protocol));
crc_state <= CKS;
when CKS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= SAH;
when SAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(31 downto 16)));
crc_state <= SAL;
when SAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(15 downto 0)));
crc_state <= DAH;
when DAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
crc_state <= DAL;
when DAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
crc_state <= FINAL;
 
when FINAL =>
tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))),'1');
crc_state <= WAIT_END;
when WAIT_END =>
tx_hdr_cks <= tx_hdr_cks;
if ip_tx_start = '0' then
crc_state <= IDLE;
else
crc_state <= WAIT_END;
end if;
 
end case;
end if;
end process;
 
 
end Behavioral;
 
/v1.1/rtl/vhdl/UDP_Complete_nomac.vhd
0,0 → 1,225
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity UDP_Complete_nomac is
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end UDP_Complete_nomac;
 
 
architecture structural of UDP_Complete_nomac is
 
------------------------------------------------------------------------------
-- Component Declaration for UDP TX
------------------------------------------------------------------------------
 
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
END COMPONENT;
 
------------------------------------------------------------------------------
-- Component Declaration for UDP RX
------------------------------------------------------------------------------
 
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
 
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
 
component IP_complete_nomac
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end component;
 
-- IP TX connectivity
signal ip_tx_int : ipv4_tx_type;
signal ip_tx_start_int : std_logic;
signal ip_tx_result_int : std_logic_vector (1 downto 0);
signal ip_tx_data_out_ready_int : std_logic;
 
-- IP RX connectivity
signal ip_rx_int : ipv4_rx_type;
signal ip_rx_start_int : std_logic := '0';
 
 
begin
 
-- output followers
ip_rx_hdr <= ip_rx_int.hdr;
 
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready=> udp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
-- IP layer TX signals
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int
);
 
-- Instantiate the UDP RX block
udp_rx_block: UDP_RX PORT MAP (
-- UDP Layer signals
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
 
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac PORT MAP
(
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- System interface
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
 
 
end structural;
 
/v1.1/rtl/vhdl/UDP_RX.vhd
0,0 → 1,343
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP RX
-- doesnt check the checsum
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
 
entity UDP_RX is
Port (
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
end UDP_RX;
 
architecture Behavioral of UDP_RX is
 
type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
signal udp_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal rx_count_val : unsigned (15 downto 0);
signal set_sph : std_logic;
signal set_spl : std_logic;
signal set_dph : std_logic;
signal set_dpl : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_udp_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_src_ip : std_logic;
signal set_data_last : std_logic;
 
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
 
 
begin
 
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
 
rx_combinatorial : process (
-- input signals
ip_rx, ip_rx_start,
-- state variables
rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
)
begin
-- set output followers
udp_rx_start <= udp_rx_start_reg;
udp_rxo.hdr.is_valid <= hdr_valid_reg;
udp_rxo.hdr.data_length <= data_len;
udp_rxo.hdr.src_port <= src_port;
udp_rxo.hdr.dst_port <= dst_port;
udp_rxo.hdr.src_ip_addr <= src_ip_addr;
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
udp_rxo.data.data_in <= ip_rx.data.data_in;
udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
udp_rxo.data.data_in_last <= set_data_last;
else
udp_rxo.data.data_in <= (others => '0');
udp_rxo.data.data_in_valid <= '0';
udp_rxo.data.data_in_last <= '0';
end if;
 
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_sph <= '0';
set_spl <= '0';
set_dph <= '0';
set_dpl <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_udp_rx_start <= HOLD;
set_hdr_valid <= HOLD;
dataval <= (others => '0');
set_src_ip <= '0';
rx_count_val <= (others => '0');
set_data_last <= '0';
-- determine event (if any)
if ip_rx.data.data_in_valid = '1' then
rx_event <= DATA;
dataval <= ip_rx.data.data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.hdr.protocol = x"11" then
-- UDP protocol
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
set_src_ip <= '1';
set_sph <= '1';
next_rx_state <= UDP_HDR;
set_rx_state <= '1';
else
-- non-UDP protocol - ignore this pkt
set_hdr_valid <= CLR;
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
end case;
 
when UDP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0007" then
rx_count_mode <= SET_VAL;
rx_count_val <= x"0001";
next_rx_state <= USER_DATA;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if ip_rx.data.data_in_last = '1' then
next_rx_state <= ERR;
set_rx_state <= '1';
else
case rx_count is
when x"0000" => set_sph <= '1';
when x"0001" => set_spl <= '1';
when x"0002" => set_dph <= '1';
when x"0003" => set_dpl <= '1';
 
when x"0004" => set_len_H <= '1';
when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
when x"0006" => -- ignore checksum values
when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
 
when others => -- ignore other bytes in udp header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_udp_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_udp_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
-- TODO need to mark frame as errored
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
set_data_last <= '1';
end if;
end if;
end case;
 
when ERR =>
if ip_rx.data.data_in_last = '0' then
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
 
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
 
 
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
 
rx_sequential : process (clk,reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_port <= (others => '0');
dst_port <= (others => '0');
data_len <= (others => '0');
udp_rx_start_reg <= '0';
hdr_valid_reg <= '0';
src_ip_addr <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
 
-- port number capture
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
 
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
else
data_len <= data_len;
end if;
case set_udp_rx_start is
when SET => udp_rx_start_reg <= '1';
when CLR => udp_rx_start_reg <= '0';
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
end case;
-- capture src IP address
if set_src_ip = '1' then
src_ip_addr <= ip_rx.hdr.src_ip_addr;
else
src_ip_addr <= src_ip_addr;
end if;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
end if;
end if;
end process;
 
end Behavioral;
 
/v1.1/rtl/vhdl/axi.vhd
0,0 → 1,25
--
-- Package File Template
--
-- Purpose: This package defines data types for AXI transfers
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package axi is
 
type axi_in_type is record
data_in : STD_LOGIC_VECTOR (7 downto 0);
data_in_valid : STD_LOGIC; -- indicates data_in valid on clock
data_in_last : STD_LOGIC; -- indicates last data in frame
end record;
type axi_out_type is record
data_out_valid : std_logic; -- indicates data out is valid
data_out_last : std_logic; -- with data out valid indicates the last byte of a frame
data_out : std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
end record;
 
end axi;
/v1.1/rtl/vhdl/UDP_TX.vhd
0,0 → 1,274
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP TX
-- doesnt generate the checksum(supposedly optional)
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
 
entity UDP_TX is
Port (
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
end UDP_TX;
 
architecture Behavioral of UDP_TX is
type tx_state_type is (IDLE, SEND_UDP_HDR, SEND_USER_DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
-- TX state variables
signal udp_tx_state : tx_state_type;
signal tx_count : unsigned (15 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal ip_tx_start_reg : std_logic;
signal data_out_ready_reg : std_logic;
 
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_count_val : unsigned (15 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_ip_tx_start : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
 
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
 
tx_combinatorial : process(
-- input signals
udp_tx_start, udp_txi, clk, ip_tx_result, ip_tx_data_out_ready,
-- state variables
udp_tx_state, tx_count, tx_result_reg, ip_tx_start_reg, data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_count_mode, tx_count_val,
tx_data, set_last, total_length, set_ip_tx_start, tx_data_valid
)
begin
-- set output followers
ip_tx_start <= ip_tx_start_reg;
ip_tx.hdr.protocol <= x"11"; -- UDP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr;
udp_tx_result <= tx_result_reg;
 
case udp_tx_state is
when SEND_USER_DATA =>
ip_tx.data.data_out <= udp_txi.data.data_out;
tx_data_valid <= udp_txi.data.data_out_valid;
ip_tx.data.data_out_last <= udp_txi.data.data_out_last;
when SEND_UDP_HDR =>
ip_tx.data.data_out <= tx_data;
tx_data_valid <= ip_tx_data_out_ready;
ip_tx.data.data_out_last <= set_last;
when others =>
ip_tx.data.data_out <= (others => '0');
tx_data_valid <= '0';
ip_tx.data.data_out_last <= set_last;
end case;
ip_tx.data.data_out_valid <= tx_data_valid and ip_tx_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
next_tx_result <= UDPTX_RESULT_NONE;
set_tx_result <= '0';
set_ip_tx_start <= HOLD;
tx_count_val <= (others => '0');
-- set temp signals
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes)
-- TX FSM
case udp_tx_state is
when IDLE =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
if udp_tx_start = '1' then
-- check header count for error if too high
if unsigned(udp_txi.hdr.data_length) > 1472 then
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
else
-- start to send UDP header
tx_count_mode <= RST;
next_tx_result <= UDPTX_RESULT_SENDING;
set_ip_tx_start <= SET;
set_tx_result <= '1';
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
end if;
end if;
when SEND_UDP_HDR =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"0000" => tx_data <= udp_txi.hdr.src_port (15 downto 8); -- src port
when x"0001" => tx_data <= udp_txi.hdr.src_port (7 downto 0);
when x"0002" => tx_data <= udp_txi.hdr.dst_port (15 downto 8); -- dst port
when x"0003" => tx_data <= udp_txi.hdr.dst_port (7 downto 0);
when x"0004" => tx_data <= total_length (15 downto 8); -- length
when x"0005" => tx_data <= total_length (7 downto 0);
when x"0006" => tx_data <= udp_txi.hdr.checksum (15 downto 8); -- checksum (set by upstream)
when x"0007" => tx_data <= udp_txi.hdr.checksum (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
end case;
end if;
when SEND_USER_DATA =>
udp_tx_data_out_ready <= '1'; -- in this state, we are always ready to accept user data for tx
if ip_tx_data_out_ready = '1' then
if udp_txi.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(udp_txi.hdr.data_length) then
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_SENT;
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
tx_data <= udp_txi.data.data_out;
end if;
end if;
end if;
 
end case;
end process;
 
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
 
tx_sequential : process (clk,reset,data_out_ready_reg)
begin
if rising_edge(clk) then
data_out_ready_reg <= ip_tx_data_out_ready;
else
data_out_ready_reg <= data_out_ready_reg;
end if;
 
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
udp_tx_state <= IDLE;
tx_count <= x"0000";
tx_result_reg <= IPTX_RESULT_NONE;
ip_tx_start_reg <= '0';
else
-- Next udp_tx_state processing
if set_tx_state = '1' then
udp_tx_state <= next_tx_state;
else
udp_tx_state <= udp_tx_state;
end if;
-- ip_tx_start_reg processing
case set_ip_tx_start is
when SET => ip_tx_start_reg <= '1';
when CLR => ip_tx_start_reg <= '0';
when HOLD => ip_tx_start_reg <= ip_tx_start_reg;
end case;
 
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"0000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
 
 
end Behavioral;
 
/v1.1/rtl/vhdl/ipv4_types.vhd
0,0 → 1,108
--
--
-- Purpose: This package defines types for use in IPv4
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.axi.all;
 
package ipv4_types is
 
--------------
-- IPv4 TX --
--------------
 
-- coding for result in tx
constant IPTX_RESULT_NONE : std_logic_vector (1 downto 0) := "00";
constant IPTX_RESULT_SENDING : std_logic_vector (1 downto 0) := "01";
constant IPTX_RESULT_ERR : std_logic_vector (1 downto 0) := "10";
constant IPTX_RESULT_SENT : std_logic_vector (1 downto 0) := "11";
 
type ipv4_tx_header_type is record
protocol : std_logic_vector (7 downto 0);
data_length : STD_LOGIC_VECTOR (15 downto 0); -- user data size, bytes
dst_ip_addr : STD_LOGIC_VECTOR (31 downto 0);
end record;
type ipv4_tx_type is record
hdr : ipv4_tx_header_type; -- header to tx
data : axi_out_type; -- tx axi bus
end record;
 
 
--------------
-- IPv4 RX --
--------------
 
-- coding for last_error_code in rx hdr
constant RX_EC_NONE : std_logic_vector (3 downto 0) := x"0";
constant RX_EC_ET_ETH : std_logic_vector (3 downto 0) := x"1"; -- early termination in ETH hdr phase
constant RX_EC_ET_IP : std_logic_vector (3 downto 0) := x"2"; -- early termination in IP hdr phase
constant RX_EC_ET_USER : std_logic_vector (3 downto 0) := x"3"; -- early termination in USER DATA phase
 
type ipv4_rx_header_type is record
is_valid : std_logic;
protocol : std_logic_vector (7 downto 0);
data_length : STD_LOGIC_VECTOR (15 downto 0); -- user data size, bytes
src_ip_addr : STD_LOGIC_VECTOR (31 downto 0);
num_frame_errors : std_logic_vector (7 downto 0);
last_error_code : std_logic_vector (3 downto 0); -- see RX_EC_xxx constants
end record;
 
type ipv4_rx_type is record
hdr : ipv4_rx_header_type; -- header received
data : axi_in_type; -- rx axi bus
end record;
 
------------
-- UDP TX --
------------
 
-- coding for result in tx
constant UDPTX_RESULT_NONE : std_logic_vector (1 downto 0) := "00";
constant UDPTX_RESULT_SENDING : std_logic_vector (1 downto 0) := "01";
constant UDPTX_RESULT_ERR : std_logic_vector (1 downto 0) := "10";
constant UDPTX_RESULT_SENT : std_logic_vector (1 downto 0) := "11";
 
type udp_tx_header_type is record
dst_ip_addr : STD_LOGIC_VECTOR (31 downto 0);
dst_port : STD_LOGIC_VECTOR (15 downto 0);
src_port : STD_LOGIC_VECTOR (15 downto 0);
data_length : STD_LOGIC_VECTOR (15 downto 0); -- user data size, bytes
checksum : STD_LOGIC_VECTOR (15 downto 0);
end record;
 
 
type udp_tx_type is record
hdr : udp_tx_header_type; -- header received
data : axi_out_type; -- tx axi bus
end record;
------------
-- UDP RX --
------------
 
type udp_rx_header_type is record
is_valid : std_logic;
src_ip_addr : STD_LOGIC_VECTOR (31 downto 0);
src_port : STD_LOGIC_VECTOR (15 downto 0);
dst_port : STD_LOGIC_VECTOR (15 downto 0);
data_length : STD_LOGIC_VECTOR (15 downto 0); -- user data size, bytes
end record;
 
 
type udp_rx_type is record
hdr : udp_rx_header_type; -- header received
data : axi_in_type; -- rx axi bus
end record;
type udp_addr_type is record
ip_addr : STD_LOGIC_VECTOR (31 downto 0);
port_num : STD_LOGIC_VECTOR (15 downto 0);
end record;
end ipv4_types;
/v1.1/rtl/vhdl/arp_types.vhd
0,0 → 1,29
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package arp_types is
 
type arp_req_req_type is
record
lookup_req : std_logic; -- set high when wanting mac adr for the requested IP
ip : std_logic_vector (31 downto 0);
end record;
 
type arp_req_rslt_type is
record
got_mac : std_logic; -- indicates that we got the mac
mac : std_logic_vector (47 downto 0);
got_err : std_logic; -- indicates that we got an error (prob a timeout)
end record;
 
end arp_types;
/v1.1/rtl/vhdl/IPv4_RX.vhd
0,0 → 1,483
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX
-- doesnt handle reassembly
-- checks and filters for IP protocol
-- checks and filters for IP addr
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity IPv4_RX is
Port (
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC -- indicates last data in frame
);
end IPv4_RX;
 
architecture Behavioral of IPv4_RX is
 
type rx_state_type is (IDLE, ETH_HDR, IP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_ip : std_logic_vector (31 downto 0); -- src IP captured from input
signal protocol : std_logic_vector (7 downto 0); -- src protocol captured from input
signal data_len : std_logic_vector (15 downto 0); -- src data length captured from input
signal ip_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal frame_err_cnt : unsigned (7 downto 0); -- number of frame errors
signal error_code_reg : std_logic_vector (3 downto 0);
signal rx_pkt_counter : unsigned (7 downto 0); -- number of rx frames received for us
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
signal set_protocol : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_ip_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal set_frame_err_cnt: count_mode_type;
signal dataval : std_logic_vector (7 downto 0);
signal rx_count_val : unsigned (15 downto 0);
signal set_error_code : std_logic;
signal error_code_val : std_logic_vector (3 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_data_last : std_logic;
 
 
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
 
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
 
rx_combinatorial : process (
-- input signals
mac_data_in, mac_data_in_valid, mac_data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, src_ip, protocol, data_len, ip_rx_start_reg, hdr_valid_reg, frame_err_cnt, error_code_reg, rx_pkt_counter,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode,
set_ip3, set_ip2, set_ip1, set_ip0, set_protocol, set_len_H, set_len_L,
set_ip_rx_start, set_hdr_valid, set_frame_err_cnt, dataval, rx_count_val,
set_error_code, error_code_val, set_pkt_cnt, set_data_last
)
begin
-- set output followers
ip_rx_start <= ip_rx_start_reg;
ip_rx.hdr.is_valid <= hdr_valid_reg;
ip_rx.hdr.protocol <= protocol;
ip_rx.hdr.data_length <= data_len;
ip_rx.hdr.src_ip_addr <= src_ip;
ip_rx.hdr.num_frame_errors <= std_logic_vector(frame_err_cnt);
ip_rx.hdr.last_error_code <= error_code_reg;
rx_pkt_count <= STD_LOGIC_VECTOR(rx_pkt_counter);
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
ip_rx.data.data_in <= mac_data_in;
ip_rx.data.data_in_valid <= mac_data_in_valid;
ip_rx.data.data_in_last <= set_data_last;
else
ip_rx.data.data_in <= (others => '0');
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
end if;
 
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_protocol <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_ip_rx_start <= HOLD;
set_hdr_valid <= HOLD;
set_frame_err_cnt <= HOLD;
rx_count_val <= x"0000";
set_error_code <= '0';
error_code_val <= RX_EC_NONE;
set_pkt_cnt <= HOLD;
dataval <= (others => '0');
set_data_last <= '0';
-- determine event (if any)
if mac_data_in_valid = '1' then
rx_event <= DATA;
dataval <= mac_data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
next_rx_state <= ETH_HDR;
set_rx_state <= '1';
end case;
 
when ETH_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"000d" then
rx_count_mode <= RST;
next_rx_state <= IP_HDR;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_ETH;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
set_rx_state <= '1';
else
case rx_count is
when x"000c" =>
if mac_data_in /= x"08" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"000d" =>
if mac_data_in /= x"00" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when others => -- ignore other bytes in eth header
end case;
end if;
end case;
 
when IP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0013" then
rx_count_val <= x"0001"; -- start counter at 1
rx_count_mode <= SET_VAL;
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_IP;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
set_rx_state <= '1';
else
case rx_count is
when x"0000" =>
if mac_data_in /= x"45" then -- ignore pkts that are not v4 with 5 header words
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0002" => set_len_H <= '1';
when x"0003" => set_len_L <= '1';
 
when x"0006" =>
if (mac_data_in(7) = '1') or (mac_data_in (4 downto 0) /= "00000") then
-- ignore pkts that require reassembly (MF=1 or frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0007" =>
if mac_data_in /= x"00" then -- ignore pkts that require reassembly (frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
 
when x"0009" => set_protocol <= '1';
 
when x"000c" => set_ip3 <= '1';
when x"000d" => set_ip2 <= '1';
when x"000e" => set_ip1 <= '1';
when x"000f" => set_ip0 <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
 
when x"0010" =>
if mac_data_in /= our_ip_address(31 downto 24) then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
 
when x"0011" =>
if mac_data_in /= our_ip_address(23 downto 16) then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
 
when x"0012" =>
if mac_data_in /= our_ip_address(15 downto 8) then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
 
when x"0013" =>
if mac_data_in /= our_ip_address(7 downto 0) then -- ignore pkts that are not addressed to us
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= USER_DATA;
set_pkt_cnt <= INCR; -- count another pkt
set_rx_state <= '1';
set_ip_rx_start <= SET;
end if;
when others => -- ignore other bytes in ip header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_ip_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if mac_data_in_last = '1' then
next_rx_state <= IDLE;
set_ip_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_USER;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end if;
end case;
 
when ERR =>
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
if mac_data_in_last = '0' then
set_data_last <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
 
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if mac_data_in_last = '1' then
set_data_last <= '1';
next_rx_state <= IDLE;
set_rx_state <= '1';
set_ip_rx_start <= CLR;
end if;
end case;
end case;
end process;
 
 
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
 
rx_sequential : process (clk,reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_ip <= (others => '0');
protocol <= (others => '0');
data_len <= (others => '0');
ip_rx_start_reg <= '0';
hdr_valid_reg <= '0';
frame_err_cnt <= (others => '0');
error_code_reg <= RX_EC_NONE;
rx_pkt_counter <= x"00";
 
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
 
-- frame error count processing
case set_frame_err_cnt is
when RST => frame_err_cnt <= x"00";
when INCR => frame_err_cnt <= frame_err_cnt + 1;
when HOLD => frame_err_cnt <= frame_err_cnt;
end case;
 
-- ip pkt processing
case set_pkt_cnt is
when RST => rx_pkt_counter <= x"00";
when INCR => rx_pkt_counter <= rx_pkt_counter + 1;
when HOLD => rx_pkt_counter <= rx_pkt_counter;
end case;
-- source ip capture
if (set_ip3 = '1') then src_ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then src_ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then src_ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then src_ip(7 downto 0) <= dataval; end if;
 
if (set_protocol = '1') then
protocol <= dataval;
else
protocol <= protocol;
end if;
 
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 20);
else
data_len <= data_len;
end if;
case set_ip_rx_start is
when SET => ip_rx_start_reg <= '1';
when CLR => ip_rx_start_reg <= '0';
when HOLD => ip_rx_start_reg <= ip_rx_start_reg;
end case;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
-- set error code
if set_error_code = '1' then
error_code_reg <= error_code_val;
else
error_code_reg <= error_code_reg;
end if;
end if;
end if;
end process;
 
end Behavioral;
 
/v1.1/doc/release_notes.txt
0,0 → 1,6
V1.1 - Added mac_tx_tfirst output to assist coupling to MAC layers that require a start of frame indication.
Migration Notes: V1.0 to V1.1
- The entity declaration for UDP_Complete_nomac and IP_Complete_nomac have changed.
- if you dont need to use the new mac_tx_tfirst output, leave it open.
 
V1.0 - initial release
/v1.1/doc/src/UDP_IP_Stack.pptx Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
v1.1/doc/src/UDP_IP_Stack.pptx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: v1.1/doc/src/zero latency receive.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: v1.1/doc/src/zero latency receive.jpg =================================================================== --- v1.1/doc/src/zero latency receive.jpg (nonexistent) +++ v1.1/doc/src/zero latency receive.jpg (revision 5)
v1.1/doc/src/zero latency receive.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: v1.1/doc/UDP_IP_Stack.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: v1.1/doc/UDP_IP_Stack.pdf =================================================================== --- v1.1/doc/UDP_IP_Stack.pdf (nonexistent) +++ v1.1/doc/UDP_IP_Stack.pdf (revision 5)
v1.1/doc/UDP_IP_Stack.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: v1.1/sw/test_results/UDPTestStream_console.txt =================================================================== --- v1.1/sw/test_results/UDPTestStream_console.txt (nonexistent) +++ v1.1/sw/test_results/UDPTestStream_console.txt (revision 5) @@ -0,0 +1,152 @@ +Sending price tick 225 +Sending price tick 224 +Sending price tick 223 +Sending price tick 222 +Sending price tick 221 +Sending price tick 220 +Sending price tick 219 +Sending price tick 218 +Sending price tick 217 +Sending price tick 216 +Sending price tick 215 +Sending price tick 214 +Sending price tick 213 +Sending price tick 212 +Sending price tick 211 +Sending price tick 210 +Sending price tick 209 +Sending price tick 208 +Sending price tick 207 +Sending price tick 206 +Sending price tick 205 +Sending price tick 204 +Sending price tick 203 +Sending price tick 202 +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Sending price tick 201 +Sending price tick 200 +Sending price tick 199 +Got [@ABC] +Sending price tick 198 +Sending price tick 197 +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Sending price tick 196 +Sending price tick 195 +Got [@ABC] +Sending price tick 194 +Sending price tick 193 +Got [@ABC] +Sending price tick 192 +Sending price tick 191 +Got [@ABC] +Sending price tick 190 +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Sending price tick 189 +Sending price tick 188 +Sending price tick 187 +Got [@ABC] +Got [@ABC] +Sending price tick 186 +Got [@ABC] +Sending price tick 185 +Sending price tick 184 +Got [@ABC] +Sending price tick 183 +Got [@ABC] +Got [@ABC] +Got [@ABC] +Sending price tick 182 +Sending price tick 181 +Got [@ABC] +Sending price tick 180 +Got [@ABC] +Sending price tick 179 +Got [@ABC] +Sending price tick 178 +Sending price tick 177 +Got [@ABC] +Sending price tick 176 +Got [@ABC] +Sending price tick 175 +Got [@ABC] +Got [@ABC] +Sending price tick 174 +Sending price tick 173 +Got [@ABC] +Sending price tick 172 +Got [@ABC] +Got [@ABC] +Got [@ABC] +Sending price tick 171 +Sending price tick 170 +Got [@ABC] +Sending price tick 169 +Sending price tick 168 +Got [@ABC] +Sending price tick 167 +Sending price tick 166 +Got [@ABC] +Sending price tick 165 +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Sending price tick 164 +Got [@ABC] +Sending price tick 163 +Sending price tick 162 +Got [@ABC] +Sending price tick 161 +Got [@ABC] +Sending price tick 160 +Got [@ABC] +Sending price tick 159 +Sending price tick 158 +Got [@ABC] +Sending price tick 157 +Sending price tick 156 +Got [@ABC] +Sending price tick 155 +Got [@ABC] +Sending price tick 154 +Got [@ABC] +Sending price tick 153 +Got [@ABC] +Sending price tick 152 +Got [@ABC] +Got [@ABC] +Got [@ABC] +Got [@ABC] +Sending price tick 151 +Sending price tick 150 +Got [@ABC] +Got [@ABC] Index: v1.1/sw/test_results/UDPTestStream_wireshark.pcap =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: v1.1/sw/test_results/UDPTestStream_wireshark.pcap =================================================================== --- v1.1/sw/test_results/UDPTestStream_wireshark.pcap (nonexistent) +++ v1.1/sw/test_results/UDPTestStream_wireshark.pcap (revision 5)
v1.1/sw/test_results/UDPTestStream_wireshark.pcap Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: v1.1/sw/test_results/UDPTest_console.txt =================================================================== --- v1.1/sw/test_results/UDPTest_console.txt (nonexistent) +++ v1.1/sw/test_results/UDPTest_console.txt (revision 5) @@ -0,0 +1,2 @@ +Sending packet: 1=45~34=201~18=23~ on port 2000 +Got [@ABC] Index: v1.1/sw/test_results/UDPTest_wireshark.pcap =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: v1.1/sw/test_results/UDPTest_wireshark.pcap =================================================================== --- v1.1/sw/test_results/UDPTest_wireshark.pcap (nonexistent) +++ v1.1/sw/test_results/UDPTest_wireshark.pcap (revision 5)
v1.1/sw/test_results/UDPTest_wireshark.pcap Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: v1.1/sw/UDPCxn.java =================================================================== --- v1.1/sw/UDPCxn.java (nonexistent) +++ v1.1/sw/UDPCxn.java (revision 5) @@ -0,0 +1,72 @@ +package com.pjf; + +import java.io.IOException; +import java.net.DatagramPacket; +import java.net.DatagramSocket; +import java.net.InetAddress; +import java.net.SocketException; +import java.net.UnknownHostException; + + +public class UDPCxn { + private DatagramSocket skt; + private InetAddress dstIP; + + public UDPCxn(long dstIPadr) throws SocketException, UnknownHostException { + skt = new DatagramSocket(); + byte[] target = new byte[4]; + target[0] = (byte) ((dstIPadr >> 24) & 0xff); + target[1] = (byte) ((dstIPadr >> 16) & 0xff); + target[2] = (byte) ((dstIPadr >> 8) & 0xff); + target[3] = (byte) (dstIPadr & 0xff); + dstIP = InetAddress.getByAddress(target); + } + + public UDPCxn(String dstIPadr) throws SocketException, UnknownHostException { + skt = new DatagramSocket(); + String[] parts = dstIPadr.split("[.]"); + if (parts.length != 4) { + throw new UnknownHostException("ip addr must have 4 parts"); + } + byte[] target = new byte[4]; + for (int i = 0; i<4; i++) { + target[i] = (byte) Integer.parseInt(parts[i]); + } + dstIP = InetAddress.getByAddress(target); + } + + public void send(byte[] data, int port) throws IOException { + DatagramPacket pkt = new DatagramPacket(data, data.length, dstIP, port); + System.out.println("Sending packet"); + skt.send(pkt); + } + + public void fixSend(String str, int port, boolean print) throws IOException { + String s1 = str.replace('~','\001'); + byte[] data = s1.getBytes(); + DatagramPacket pkt = new DatagramPacket(data, data.length, dstIP, port); + if (print) { + System.out.println("Sending packet: " + str + " on port " + port); + } + skt.send(pkt); + } + + + public byte[] rcv() throws IOException { + byte[] buf = new byte[1024]; + DatagramPacket pkt = new DatagramPacket(buf, buf.length); +// System.out.println("waiting to receive ..."); + skt.receive(pkt); + int len = pkt.getLength(); + byte[] rd = pkt.getData(); + byte[] data = new byte[len]; + for (int i=0; i=150; price--) { + StringBuffer fixmsg = new StringBuffer(fix1); + fixmsg.append(Integer.toString(price)); + fixmsg.append(fix2); + System.out.println("Sending price tick " + price); + cxn.fixSend(fixmsg.toString(), 2000, false); + } + Thread.sleep(2000); + } + + + public static void main(String[] args) { + UDPTestStream ut; + try { + ut = new UDPTestStream(); + ut.go(); + } catch (Exception e) { + e.printStackTrace(); + } + } + + +} Index: v1.1/sw/UDPTest.java =================================================================== --- v1.1/sw/UDPTest.java (nonexistent) +++ v1.1/sw/UDPTest.java (revision 5) @@ -0,0 +1,34 @@ +package com.pjf; + +import java.io.IOException; +import java.net.SocketException; +import java.net.UnknownHostException; + +public class UDPTest { + private UDPCxn cxn; + + public UDPTest() throws SocketException, UnknownHostException { + cxn = new UDPCxn("192.168.5.9"); + } + + public void go() throws IOException { + String fix1 = "1=45~34=201~18=23~"; + cxn.fixSend(fix1, 2000, true); + byte[] rep = cxn.rcv(); + String reply = new String(rep); + System.out.println("Got [" + reply + "]"); + } + + + public static void main(String[] args) { + UDPTest ut; + try { + ut = new UDPTest(); + ut.go(); + } catch (Exception e) { + e.printStackTrace(); + } + } + + +}

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