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/bench/vhdl/arpv2_tb.vhd
16,7 → 16,7
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added tests for ARP timeout
-- Revision 0.02 - Added tests for ARP timeout
-- Additional Comments:
--
-- Notes:
26,931 → 26,1109
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arp_types.all;
ENTITY arpv2_tb IS
END arpv2_tb;
ARCHITECTURE behavior OF arpv2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT arpv2
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
END COMPONENT;
 
entity arpv2_tb is
end arpv2_tb;
 
architecture behavior of arpv2_tb is
 
-- Component Declaration for the Unit Under Test (UUT)
component arpv2
generic (
no_default_gateway : boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
nwk_gateway : in std_logic_vector (31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector (31 downto 0); -- Net mask
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end component;
 
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in_valid : std_logic := '0';
signal data_in_last : std_logic := '0';
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal nwk_gateway : std_logic_vector(31 downto 0) := (others => '0');
signal nwk_mask : std_logic_vector(31 downto 0) := (others => '0');
signal data_out_ready : std_logic;
signal data_out_valid : std_logic;
signal data_out_first : std_logic;
signal data_out_last : std_logic;
signal data_out : std_logic_vector (7 downto 0);
signal req_count : std_logic_vector(7 downto 0);
signal arp_req_req : arp_req_req_type;
signal arp_req_rslt : arp_req_rslt_type;
signal mac_tx_req : std_logic;
signal mac_tx_granted : std_logic;
signal control : arp_control_type;
 
constant no_default_gateway : boolean := false;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
begin
 
-- Instantiate the Unit Under Test (UUT)
uut : arpv2
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => 10, -- artificially low count to enable pragmatic testing
ARP_TIMEOUT => 20
)
port map (
-- lookup request mappings
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- rx mappings
data_in_clk => clk,
reset => reset,
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- tx mappings
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_clk => clk,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system mappings
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
nwk_gateway => nwk_gateway,
nwk_mask => nwk_mask,
control => control,
req_count => req_count
);
 
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
 
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
our_ip_address <= x"c0a80509"; -- 192.168.5.9
nwk_mask <= x"FFFFFF00";
nwk_gateway <= x"c0a80501"; -- 192.168.5.9
our_mac_address <= x"002320212223";
mac_tx_granted <= '1'; -- FIXME 0
control.clear_cache <= '0';
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
 
assert mac_tx_req = '0' report "mac_tx_req asserted on reset";
 
wait until clk = '1';
-- insert stimulus here
arp_req_req.lookup_req <= '0';
arp_req_req.ip <= (others => '0');
data_out_ready <= '1';
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in_valid : std_logic := '0';
signal data_in_last : std_logic := '0';
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal data_out_ready : std_logic;
signal data_out_valid : std_logic;
signal data_out_first : std_logic;
signal data_out_last : std_logic;
signal data_out : std_logic_vector (7 downto 0);
signal req_count : STD_LOGIC_VECTOR(7 downto 0);
signal arp_req_req : arp_req_req_type;
signal arp_req_rslt : arp_req_rslt_type;
signal mac_tx_req : std_logic;
signal mac_tx_granted : std_logic;
signal control : arp_control_type;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: arpv2
generic map (
CLOCK_FREQ => 10, -- artificially low count to enable pragmatic testing
ARP_TIMEOUT => 20
)
PORT MAP (
-- lookup request mappings
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- rx mappings
data_in_clk => clk,
reset => reset,
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- tx mappings
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_clk => clk,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system mappings
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control,
req_count => req_count
);
report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
report "T1: Expect that we send an 'I have 192.168.5.9' msg";
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- check tx arbitration signals
 
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
mac_tx_granted <= '1'; -- FIXME 0
control.clear_cache <= '0';
report "T1: waiting for tx req";
wait until mac_tx_req = '1';
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
assert mac_tx_req = '0' report "mac_tx_req asserted on reset";
-- ready to tx
data_out_ready <= '1';
mac_tx_granted <= '1';
report "T1: waiting for data_out_valid";
wait until data_out_valid = '1';
report "T1: got data_out_valid";
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*12;
assert data_out = x"02" report "T1: expected opcode = 02 for reply 'I have'";
-- expect our mac 00 23 20 21 22 23
wait for clk_period;
assert data_out = x"00" report "T1: incorrect our mac.0";
wait for clk_period;
assert data_out = x"23" report "T1: incorrect our mac.1";
wait for clk_period;
assert data_out = x"20" report "T1: incorrect our mac.2";
wait for clk_period;
assert data_out = x"21" report "T1: incorrect our mac.3";
wait for clk_period;
assert data_out = x"22" report "T1: incorrect our mac.4";
wait for clk_period;
assert data_out = x"23" report "T1: incorrect our mac.5";
-- expect our IP c0 a8 05 05
wait for clk_period;
assert data_out = x"c0" report "T1: incorrect our IP.0";
wait for clk_period;
assert data_out = x"a8" report "T1: incorrect our IP.1";
wait for clk_period;
assert data_out = x"05" report "T1: incorrect our IP.2";
wait for clk_period;
assert data_out = x"09" report "T1: incorrect our IP.3";
 
-- insert stimulus here
arp_req_req.lookup_req <= '0';
arp_req_req.ip <= (others => '0');
data_out_ready <= '1';
-- expect target mac 00 23 18 29 26 7c
wait for clk_period;
assert data_out = x"00" report "T1: incorrect target mac.0";
wait for clk_period;
assert data_out = x"23" report "T1: incorrect target mac.1";
wait for clk_period;
assert data_out = x"18" report "T1: incorrect target mac.2";
wait for clk_period;
assert data_out = x"29" report "T1: incorrect target mac.3";
wait for clk_period;
assert data_out = x"26" report "T1: incorrect target mac.4";
wait for clk_period;
assert data_out = x"7c" report "T1: incorrect target mac.5";
-- expect target IP c0 a8 05 01
wait for clk_period;
assert data_out = x"c0" report "T1: incorrect target IP.0";
wait for clk_period;
assert data_out = x"a8" report "T1: incorrect target IP.1";
wait for clk_period;
assert data_out = x"05" report "T1: incorrect target IP.2";
assert data_out_last = '0' report "T1: data out last incorrectly set on target IP.2 byte";
wait for clk_period;
assert data_out = x"01" report "T1: incorrect target IP.3";
assert data_out_last = '1' report "T1: data out last should be set";
 
report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
 
report "T1: Expect that we send an 'I have 192.168.5.9' msg";
-- check tx arbitration signals
 
report "T1: waiting for tx req";
wait until mac_tx_req = '1';
-- ready to tx
data_out_ready <= '1';
mac_tx_granted <= '1';
report "T1: waiting for data_out_valid";
wait until data_out_valid = '1';
report "T1: got data_out_valid";
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*12;
assert data_out = x"02" report "T1: expected opcode = 02 for reply 'I have'";
-- expect our mac 00 23 20 21 22 23
wait for clk_period;
assert data_out = x"00" report "T1: incorrect our mac.0";
wait for clk_period;
assert data_out = x"23" report "T1: incorrect our mac.1";
wait for clk_period;
assert data_out = x"20" report "T1: incorrect our mac.2";
wait for clk_period;
assert data_out = x"21" report "T1: incorrect our mac.3";
wait for clk_period;
assert data_out = x"22" report "T1: incorrect our mac.4";
wait for clk_period;
assert data_out = x"23" report "T1: incorrect our mac.5";
-- expect our IP c0 a8 05 05
wait for clk_period;
assert data_out = x"c0" report "T1: incorrect our IP.0";
wait for clk_period;
assert data_out = x"a8" report "T1: incorrect our IP.1";
wait for clk_period;
assert data_out = x"05" report "T1: incorrect our IP.2";
wait for clk_period;
assert data_out = x"09" report "T1: incorrect our IP.3";
 
-- expect target mac 00 23 18 29 26 7c
wait for clk_period;
assert data_out = x"00" report "T1: incorrect target mac.0";
wait for clk_period;
assert data_out = x"23" report "T1: incorrect target mac.1";
wait for clk_period;
assert data_out = x"18" report "T1: incorrect target mac.2";
wait for clk_period;
assert data_out = x"29" report "T1: incorrect target mac.3";
wait for clk_period;
assert data_out = x"26" report "T1: incorrect target mac.4";
wait for clk_period;
assert data_out = x"7c" report "T1: incorrect target mac.5";
-- expect target IP c0 a8 05 01
wait for clk_period;
assert data_out = x"c0" report "T1: incorrect target IP.0";
wait for clk_period;
assert data_out = x"a8" report "T1: incorrect target IP.1";
wait for clk_period;
assert data_out = x"05" report "T1: incorrect target IP.2";
assert data_out_last = '0' report "T1: data out last incorrectly set on target IP.2 byte";
wait for clk_period;
assert data_out = x"01" report "T1: incorrect target IP.3";
assert data_out_last = '1' report "T1: data out last should be set";
wait for clk_period*10;
report "T2: Send another ARP request: who has 192.168.5.8? Tell 192.168.5.1, holding off transmitter";
data_out_ready <= '0';
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
-- ready to tx
wait for clk_period*10;
data_out_ready <= '1';
wait for clk_period*50;
 
report "T3: Send a request for the IP that is already in the store";
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T3: wait for reply from store";
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T3: expected got mac";
assert arp_req_rslt.got_err = '0' report "T3: expected got err = 0";
assert arp_req_rslt.mac = x"00231829267c" report "T3: wrong mac value";
wait for clk_period*2;
-- the entry that was in the store should now be in the cache - check it
report "T4: Send a request for the IP that is already in the cache";
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
assert arp_req_rslt.got_mac = '1' report "T4: expected got mac";
assert arp_req_rslt.got_err = '0' report "T4: expected got err = 0";
assert arp_req_rslt.mac = x"00231829267c" report "T4: wrong mac value";
wait for clk_period*50;
report "T5 - Send a request for the IP that is not cached or in the store";
arp_req_req.ip <= x"c0a80503";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T5: waiting for data_out_valid";
wait until data_out_valid = '1';
report "T5: got data_out_valid";
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*12;
assert data_out = x"01" report "T5: expected opcode = 01 for request 'who has'";
-- expect our mac 00 23 20 21 22 23
wait for clk_period;
assert data_out = x"00" report "T5: incorrect our mac.0";
wait for clk_period;
assert data_out = x"23" report "T5: incorrect our mac.1";
wait for clk_period;
assert data_out = x"20" report "T5: incorrect our mac.2";
wait for clk_period;
assert data_out = x"21" report "T5: incorrect our mac.3";
wait for clk_period;
assert data_out = x"22" report "T5: incorrect our mac.4";
wait for clk_period;
assert data_out = x"23" report "T5: incorrect our mac.5";
-- expect our IP c0 a8 05 05
wait for clk_period;
assert data_out = x"c0" report "T5: incorrect our IP.0";
wait for clk_period;
assert data_out = x"a8" report "T5: incorrect our IP.1";
wait for clk_period;
assert data_out = x"05" report "T5: incorrect our IP.2";
wait for clk_period;
assert data_out = x"09" report "T5: incorrect our IP.3";
 
-- expect empty target mac
wait for clk_period;
assert data_out = x"00" report "T5: incorrect target mac.0";
wait for clk_period;
assert data_out = x"00" report "T5: incorrect target mac.1";
wait for clk_period;
assert data_out = x"00" report "T5: incorrect target mac.2";
wait for clk_period;
assert data_out = x"00" report "T5: incorrect target mac.3";
wait for clk_period;
assert data_out = x"00" report "T5: incorrect target mac.4";
wait for clk_period;
assert data_out = x"00" report "T5: incorrect target mac.5";
-- expect target IP c0 a8 05 01
wait for clk_period;
assert data_out = x"c0" report "T5: incorrect target IP.0";
wait for clk_period;
assert data_out = x"a8" report "T5: incorrect target IP.1";
wait for clk_period;
assert data_out = x"05" report "T5: incorrect target IP.2";
assert data_out_last = '0' report "T5: data out last incorrectly set on target IP.2 byte";
wait for clk_period;
assert data_out = x"03" report "T5: incorrect target IP.3";
assert data_out_last = '1' report "T5: data out last should be set";
wait for clk_period*10;
-- Send the reply
data_out_ready <= '1';
wait for clk_period*10;
 
report "T5.2: Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T5.2: expected got mac";
assert arp_req_rslt.got_err = '0' report "T5.2: expected got err = 0";
assert arp_req_rslt.mac = x"021203230454" report "T5.2: wrong mac value";
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period*4;
 
report "T6: check that both these IPs remain in the store";
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period;
report "T6.1: wait for reply from store";
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T6.1: expected got mac";
assert arp_req_rslt.got_err = '0' report "T6.1: expected got err = 0";
assert arp_req_rslt.mac = x"00231829267c" report "T6.1: wrong mac value";
wait for clk_period*2;
 
arp_req_req.ip <= x"c0a80503";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period;
report "T6.2: wait for reply from store";
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T6.2: expected got mac";
assert arp_req_rslt.got_err = '0' report "T6.2: expected got err = 0";
assert arp_req_rslt.mac = x"021203230454" report "T6.2: wrong mac value";
wait for clk_period*2;
 
report "T7 - test that receipt of wrong I Have does not satisfy a current req";
arp_req_req.ip <= x"c0a8050e";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T7: waiting for data_out_valid";
wait until data_out_valid = '1';
report "T7: got data_out_valid";
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*12;
assert data_out = x"01" report "T7: expected opcode = 01 for request 'who has'";
-- expect our mac 00 23 20 21 22 23
wait for clk_period;
assert data_out = x"00" report "T7: incorrect our mac.0";
wait for clk_period;
assert data_out = x"23" report "T7: incorrect our mac.1";
wait for clk_period;
assert data_out = x"20" report "T7: incorrect our mac.2";
wait for clk_period;
assert data_out = x"21" report "T7: incorrect our mac.3";
wait for clk_period;
assert data_out = x"22" report "T7: incorrect our mac.4";
wait for clk_period;
assert data_out = x"23" report "T7: incorrect our mac.5";
-- expect our IP c0 a8 05 05
wait for clk_period;
assert data_out = x"c0" report "T7: incorrect our IP.0";
wait for clk_period;
assert data_out = x"a8" report "T7: incorrect our IP.1";
wait for clk_period;
assert data_out = x"05" report "T7: incorrect our IP.2";
wait for clk_period;
assert data_out = x"09" report "T7: incorrect our IP.3";
 
-- expect empty target mac
wait for clk_period;
assert data_out = x"00" report "T7: incorrect target mac.0";
wait for clk_period;
assert data_out = x"00" report "T7: incorrect target mac.1";
wait for clk_period;
assert data_out = x"00" report "T7: incorrect target mac.2";
wait for clk_period;
assert data_out = x"00" report "T7: incorrect target mac.3";
wait for clk_period;
assert data_out = x"00" report "T7: incorrect target mac.4";
wait for clk_period;
assert data_out = x"00" report "T7: incorrect target mac.5";
-- expect target IP c0 a8 05 0e
wait for clk_period;
assert data_out = x"c0" report "T7: incorrect target IP.0";
wait for clk_period;
assert data_out = x"a8" report "T7: incorrect target IP.1";
wait for clk_period;
assert data_out = x"05" report "T7: incorrect target IP.2";
assert data_out_last = '0' report "T7: data out last incorrectly set on target IP.2 byte";
wait for clk_period;
assert data_out = x"0e" report "T7: incorrect target IP.3";
assert data_out_last = '1' report "T7: data out last should be set";
wait for clk_period*10;
-- Send the reply
data_out_ready <= '1';
report "T2: Send another ARP request: who has 192.168.5.8? Tell 192.168.5.1, holding off transmitter";
data_out_ready <= '0';
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Sender MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"18"; wait for clk_period;
data_in <= x"29"; wait for clk_period;
data_in <= x"26"; wait for clk_period;
data_in <= x"7c"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
 
report "T7.2: Send an arbitrary unwanted ARP reply: 192.168.7.3 has mac 57:12:34:19:23:9a";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"57"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"19"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"9a"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"57"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"19"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"9a"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"07"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T7.2: expected got mac = 0";
assert arp_req_rslt.got_err = '0' report "T7.2: expected got err = 0";
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period*4;
 
-- Send the reply
data_out_ready <= '1';
-- ready to tx
wait for clk_period*10;
data_out_ready <= '1';
 
report "T7.3: Send a wanted ARP reply: 192.168.5.e has mac 76:34:98:55:aa:37";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"76"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"98"; wait for clk_period;
data_in <= x"55"; wait for clk_period;
data_in <= x"aa"; wait for clk_period;
data_in <= x"37"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"76"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"98"; wait for clk_period;
data_in <= x"55"; wait for clk_period;
data_in <= x"aa"; wait for clk_period;
data_in <= x"37"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"0e"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T7.3: expected got mac";
assert arp_req_rslt.got_err = '0' report "T7.3: expected got err = 0";
assert arp_req_rslt.mac = x"76349855aa37" report "T7.3: wrong mac value";
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period*4;
 
 
report "T8: Request 192.168.5.4 (not cached), dont send a reply and wait for timeout";
arp_req_req.ip <= x"c0a80504";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T8: should be requesting TX channel";
wait for clk_period*220;
assert arp_req_rslt.got_mac = '0' report "T8: should not have got mac";
assert arp_req_rslt.got_err = '1' report "T8: should have got err";
report "T9: Request 192.168.5.7 (not cached= and Send an ARP reply: 192.168.5.7 has mac 02:15:03:23:04:54";
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T9: should not yet have mac";
assert arp_req_rslt.got_err = '0' report "T9: should not have got err";
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T9: should be requesting TX channel";
wait for clk_period*50;
-- Send the reply
data_out_ready <= '1';
wait for clk_period*50;
 
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"07"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T9: should have got mac";
assert arp_req_rslt.mac = x"021503230454" report "T9: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T9: should not have got err";
wait for clk_period*10;
 
report "T10: Request 192.168.5.7 again an expect it to be in the cache";
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T10: should have mac";
assert arp_req_rslt.got_err = '0' report "T10: should not have got err";
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
report "T11: Clear the cache, Request 192.168.5.7 again an expect a 'who has' to be sent";
control.clear_cache <= '1';
wait for clk_period;
control.clear_cache <= '0';
wait for clk_period;
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T11: should not yet have mac";
assert arp_req_rslt.got_err = '0' report "T11: should not have got err";
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T11: should be requesting TX channel";
wait for clk_period*50;
-- Send the reply
data_out_ready <= '1';
report "T3: Send a request for the IP that is already in the store";
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T3: wait for reply from store";
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T3: expected got mac";
assert arp_req_rslt.got_err = '0' report "T3: expected got err = 0";
assert arp_req_rslt.mac = x"00231829267c" report "T3: wrong mac value";
wait for clk_period*2;
 
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"55"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"07"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T11: should have got mac";
assert arp_req_rslt.mac = x"021503235554" report "T11: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T11: should not have got err";
wait for clk_period*10;
report "--- end of tests ---";
wait;
end process;
-- the entry that was in the store should now be in the cache - check it
report "T4: Send a request for the IP that is already in the cache";
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
assert arp_req_rslt.got_mac = '1' report "T4: expected got mac";
assert arp_req_rslt.got_err = '0' report "T4: expected got err = 0";
assert arp_req_rslt.mac = x"00231829267c" report "T4: wrong mac value";
 
END;
wait for clk_period*50;
 
report "T5 - Send a request for the IP that is not cached or in the store";
arp_req_req.ip <= x"c0a80503";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T5: waiting for data_out_valid";
wait until data_out_valid = '1';
report "T5: got data_out_valid";
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*12;
assert data_out = x"01" report "T5: expected opcode = 01 for request 'who has'";
-- expect our mac 00 23 20 21 22 23
wait for clk_period;
assert data_out = x"00" report "T5: incorrect our mac.0";
wait for clk_period;
assert data_out = x"23" report "T5: incorrect our mac.1";
wait for clk_period;
assert data_out = x"20" report "T5: incorrect our mac.2";
wait for clk_period;
assert data_out = x"21" report "T5: incorrect our mac.3";
wait for clk_period;
assert data_out = x"22" report "T5: incorrect our mac.4";
wait for clk_period;
assert data_out = x"23" report "T5: incorrect our mac.5";
-- expect our IP c0 a8 05 05
wait for clk_period;
assert data_out = x"c0" report "T5: incorrect our IP.0";
wait for clk_period;
assert data_out = x"a8" report "T5: incorrect our IP.1";
wait for clk_period;
assert data_out = x"05" report "T5: incorrect our IP.2";
wait for clk_period;
assert data_out = x"09" report "T5: incorrect our IP.3";
 
-- expect empty target mac
wait for clk_period;
assert data_out = x"ff" report "T5: incorrect target mac.0";
wait for clk_period;
assert data_out = x"ff" report "T5: incorrect target mac.1";
wait for clk_period;
assert data_out = x"ff" report "T5: incorrect target mac.2";
wait for clk_period;
assert data_out = x"ff" report "T5: incorrect target mac.3";
wait for clk_period;
assert data_out = x"ff" report "T5: incorrect target mac.4";
wait for clk_period;
assert data_out = x"ff" report "T5: incorrect target mac.5";
-- expect target IP c0 a8 05 01
wait for clk_period;
assert data_out = x"c0" report "T5: incorrect target IP.0";
wait for clk_period;
assert data_out = x"a8" report "T5: incorrect target IP.1";
wait for clk_period;
assert data_out = x"05" report "T5: incorrect target IP.2";
assert data_out_last = '0' report "T5: data out last incorrectly set on target IP.2 byte";
wait for clk_period;
assert data_out = x"03" report "T5: incorrect target IP.3";
assert data_out_last = '1' report "T5: data out last should be set";
 
wait for clk_period*10;
 
-- Send the reply
data_out_ready <= '1';
 
report "T5.2: Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T5.2: expected got mac";
assert arp_req_rslt.got_err = '0' report "T5.2: expected got err = 0";
assert arp_req_rslt.mac = x"021203230454" report "T5.2: wrong mac value";
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period*4;
 
report "T6: check that both these IPs remain in the store";
arp_req_req.ip <= x"c0a80501";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period;
report "T6.1: wait for reply from store";
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T6.1: expected got mac";
assert arp_req_rslt.got_err = '0' report "T6.1: expected got err = 0";
assert arp_req_rslt.mac = x"00231829267c" report "T6.1: wrong mac value";
wait for clk_period*2;
 
arp_req_req.ip <= x"c0a80503";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period;
report "T6.2: wait for reply from store";
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T6.2: expected got mac";
assert arp_req_rslt.got_err = '0' report "T6.2: expected got err = 0";
assert arp_req_rslt.mac = x"021203230454" report "T6.2: wrong mac value";
wait for clk_period*2;
 
report "T7 - test that receipt of wrong I Have does not satisfy a current req";
arp_req_req.ip <= x"c0a8050e";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T7: waiting for data_out_valid";
wait until data_out_valid = '1';
report "T7: got data_out_valid";
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*12;
assert data_out = x"01" report "T7: expected opcode = 01 for request 'who has'";
-- expect our mac 00 23 20 21 22 23
wait for clk_period;
assert data_out = x"00" report "T7: incorrect our mac.0";
wait for clk_period;
assert data_out = x"23" report "T7: incorrect our mac.1";
wait for clk_period;
assert data_out = x"20" report "T7: incorrect our mac.2";
wait for clk_period;
assert data_out = x"21" report "T7: incorrect our mac.3";
wait for clk_period;
assert data_out = x"22" report "T7: incorrect our mac.4";
wait for clk_period;
assert data_out = x"23" report "T7: incorrect our mac.5";
-- expect our IP c0 a8 05 05
wait for clk_period;
assert data_out = x"c0" report "T7: incorrect our IP.0";
wait for clk_period;
assert data_out = x"a8" report "T7: incorrect our IP.1";
wait for clk_period;
assert data_out = x"05" report "T7: incorrect our IP.2";
wait for clk_period;
assert data_out = x"09" report "T7: incorrect our IP.3";
 
-- expect empty target mac
wait for clk_period;
assert data_out = x"ff" report "T7: incorrect target mac.0";
wait for clk_period;
assert data_out = x"ff" report "T7: incorrect target mac.1";
wait for clk_period;
assert data_out = x"ff" report "T7: incorrect target mac.2";
wait for clk_period;
assert data_out = x"ff" report "T7: incorrect target mac.3";
wait for clk_period;
assert data_out = x"ff" report "T7: incorrect target mac.4";
wait for clk_period;
assert data_out = x"ff" report "T7: incorrect target mac.5";
-- expect target IP c0 a8 05 0e
wait for clk_period;
assert data_out = x"c0" report "T7: incorrect target IP.0";
wait for clk_period;
assert data_out = x"a8" report "T7: incorrect target IP.1";
wait for clk_period;
assert data_out = x"05" report "T7: incorrect target IP.2";
assert data_out_last = '0' report "T7: data out last incorrectly set on target IP.2 byte";
wait for clk_period;
assert data_out = x"0e" report "T7: incorrect target IP.3";
assert data_out_last = '1' report "T7: data out last should be set";
 
wait for clk_period*10;
 
-- Send the reply
data_out_ready <= '1';
 
report "T7.2: Send an arbitrary unwanted ARP reply: 192.168.5.143 has mac 57:12:34:19:23:9a";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"57"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"19"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"9a"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"57"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"19"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"9a"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"25"; wait for clk_period;
data_in <= x"93"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T7.2: expected got mac = 0";
assert arp_req_rslt.got_err = '0' report "T7.2: expected got err = 0";
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period*4;
 
-- Send the reply
data_out_ready <= '1';
 
report "T7.3: Send a wanted ARP reply: 192.168.5.e has mac 76:34:98:55:aa:37";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"76"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"98"; wait for clk_period;
data_in <= x"55"; wait for clk_period;
data_in <= x"aa"; wait for clk_period;
data_in <= x"37"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"76"; wait for clk_period;
data_in <= x"34"; wait for clk_period;
data_in <= x"98"; wait for clk_period;
data_in <= x"55"; wait for clk_period;
data_in <= x"aa"; wait for clk_period;
data_in <= x"37"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"0e"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T7.3: expected got mac";
assert arp_req_rslt.got_err = '0' report "T7.3: expected got err = 0";
assert arp_req_rslt.mac = x"76349855aa37" report "T7.3: wrong mac value";
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period*4;
 
 
report "T8: Request 192.168.5.4 (not cached), dont send a reply and wait for timeout";
arp_req_req.ip <= x"c0a80504";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T8: should be requesting TX channel";
wait for clk_period*220;
assert arp_req_rslt.got_mac = '0' report "T8: should not have got mac";
assert arp_req_rslt.got_err = '1' report "T8: should have got err";
 
report "T9: Request 192.168.5.7 (not cached= and Send an ARP reply: 192.168.5.7 has mac 02:15:03:23:04:54";
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T9: should not yet have mac";
assert arp_req_rslt.got_err = '0' report "T9: should not have got err";
 
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
assert mac_tx_req = '1' report "T9: should be requesting TX channel";
wait for clk_period*50;
-- Send the reply
data_out_ready <= '1';
 
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"07"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T9: should have got mac";
assert arp_req_rslt.mac = x"021503230454" report "T9: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T9: should not have got err";
wait for clk_period*10;
 
report "T10: Request 192.168.5.7 again an expect it to be in the cache";
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T10: should have mac";
assert arp_req_rslt.got_err = '0' report "T10: should not have got err";
 
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
--
wait until clk = '1';
report "T11 - Send a request for the IP that is not on the local network";
arp_req_req.ip <= x"0a000003"; --c0a80501
arp_req_req.lookup_req <= '1';
wait until clk = '1'; --for clk_period
arp_req_req.lookup_req <= '0';
report "T11: wait for reply from store";
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T11: expected got mac";
assert arp_req_rslt.got_err = '0' report "T11: expected got err = 0";
assert arp_req_rslt.mac = x"00231829267c" report "T11: wrong mac value";-- severity failure;
wait for clk_period*2;
--
 
report "T12: Clear the cache, Request 192.168.5.7 again an expect a 'who has' to be sent";
control.clear_cache <= '1';
wait for clk_period;
control.clear_cache <= '0';
wait for clk_period;
 
arp_req_req.ip <= x"c0a80507";
arp_req_req.lookup_req <= '1';
wait for clk_period;
assert arp_req_rslt.got_mac = '0' report "T12: should not yet have mac";
assert arp_req_rslt.got_err = '0' report "T12: should not have got err";
 
arp_req_req.lookup_req <= '0';
wait for clk_period*20;
 
 
assert mac_tx_req = '1' report "T12: should be requesting TX channel";
wait for clk_period*50;
-- Send the reply
data_out_ready <= '1';
 
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"15"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"55"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"07"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T12: should have got mac";
assert arp_req_rslt.mac = x"021503235554" report "T12: incorrect mac";
assert arp_req_rslt.got_err = '0' report "T12: should not have got err";
wait for clk_period*10;
 
--
report "T13 - Send a request for the IP that is not on the local network";
arp_req_req.ip <= x"0a000003";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T13: waiting for data_out_valid";
wait until data_out_valid = '1';
report "T13: got data_out_valid";
wait for clk_period*10;
data_out_ready <= '0';
wait for clk_period*2;
data_out_ready <= '1';
wait for clk_period*12;
assert data_out = x"01" report "T13: expected opcode = 01 for request 'who has'";
-- expect our mac 00 23 20 21 22 23
wait for clk_period;
assert data_out = x"00" report "T13: incorrect our mac.0";
wait for clk_period;
assert data_out = x"23" report "T13: incorrect our mac.1";
wait for clk_period;
assert data_out = x"20" report "T13: incorrect our mac.2";
wait for clk_period;
assert data_out = x"21" report "T13: incorrect our mac.3";
wait for clk_period;
assert data_out = x"22" report "T13: incorrect our mac.4";
wait for clk_period;
assert data_out = x"23" report "T13: incorrect our mac.5";
-- expect our IP c0 a8 05 05
wait for clk_period;
assert data_out = x"c0" report "T13: incorrect our IP.0";
wait for clk_period;
assert data_out = x"a8" report "T13: incorrect our IP.1";
wait for clk_period;
assert data_out = x"05" report "T13: incorrect our IP.2";
wait for clk_period;
assert data_out = x"09" report "T13: incorrect our IP.3";
 
-- expect empty target mac
wait for clk_period;
assert data_out = x"ff" report "T13: incorrect target mac.0";
wait for clk_period;
assert data_out = x"ff" report "T13: incorrect target mac.1";
wait for clk_period;
assert data_out = x"ff" report "T13: incorrect target mac.2";
wait for clk_period;
assert data_out = x"ff" report "T13: incorrect target mac.3";
wait for clk_period;
assert data_out = x"ff" report "T13: incorrect target mac.4";
wait for clk_period;
assert data_out = x"ff" report "T13: incorrect target mac.5";
-- expect target IP c0 a8 05 01
wait for clk_period;
assert data_out = x"c0" report "T13: incorrect target IP.0";
wait for clk_period;
assert data_out = x"a8" report "T13: incorrect target IP.1";
wait for clk_period;
assert data_out = x"05" report "T13: incorrect target IP.2";
assert data_out_last = '0' report "T13: data out last incorrectly set on target IP.2 byte";
wait for clk_period;
assert data_out = x"01" report "T13: incorrect target IP.3";
assert data_out_last = '1' report "T13: data out last should be set";
 
wait for clk_period*10;
 
-- Send the reply
data_out_ready <= '1';
 
report "T13.2: Send an ARP reply: 192.168.5.1 has mac 02:12:03:23:04:54";
data_in_valid <= '1';
-- dst MAC (bc)
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
data_in <= x"ff"; wait for clk_period;
-- src MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- type
data_in <= x"08"; wait for clk_period;
data_in <= x"06"; wait for clk_period;
-- HW type
data_in <= x"00"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Protocol type
data_in <= x"08"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
-- HW size
data_in <= x"06"; wait for clk_period;
-- protocol size
data_in <= x"04"; wait for clk_period;
-- Opcode
data_in <= x"00"; wait for clk_period;
data_in <= x"02"; wait for clk_period;
-- Sender MAC
data_in <= x"02"; wait for clk_period;
data_in <= x"12"; wait for clk_period;
data_in <= x"03"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"04"; wait for clk_period;
data_in <= x"54"; wait for clk_period;
-- Sender IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"01"; wait for clk_period;
-- Target MAC
data_in <= x"00"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
data_in <= x"20"; wait for clk_period;
data_in <= x"21"; wait for clk_period;
data_in <= x"22"; wait for clk_period;
data_in <= x"23"; wait for clk_period;
-- Target IP
data_in <= x"c0"; wait for clk_period;
data_in <= x"a8"; wait for clk_period;
data_in <= x"05"; wait for clk_period;
data_in <= x"09"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
data_in <= x"00"; wait for clk_period;
assert arp_req_rslt.got_mac = '1' report "T13.2: expected got mac";
assert arp_req_rslt.got_err = '0' report "T13.2: expected got err = 0";
assert arp_req_rslt.mac = x"021203230454" report "T13.2: wrong mac value";
data_in <= x"00"; wait for clk_period;
data_in_last <= '1';
data_in <= x"00"; wait for clk_period;
data_in_last <= '0';
data_in_valid <= '0';
wait for clk_period*4;
 
report "T14 - Send a request for an other IP that is not on the local network";
arp_req_req.ip <= x"0a000204";
arp_req_req.lookup_req <= '1';
wait for clk_period;
arp_req_req.lookup_req <= '0';
report "T14: reply should be from cache";
-- wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1';
assert arp_req_rslt.got_mac = '1' report "T14: expected got mac";
assert arp_req_rslt.got_err = '0' report "T14: expected got err = 0";
assert arp_req_rslt.mac = x"021203230454" report "T14: wrong mac value";
wait for clk_period*2;
--
 
report "--- end of tests ---";
wait;
end process;
 
end;
/bench/vhdl/IPv4_TX_tb.vhd
1,363 → 1,363
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:35:58 06/03/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4_TX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added test for IP broadcast tx
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
ENTITY IPv4_TX_tb IS
END IPv4_TX_tb;
ARCHITECTURE behavior OF IPv4_TX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPv4_TX
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
 
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
 
--Inputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_granted : std_logic := '0';
signal mac_data_out_ready : std_logic := '0';
signal arp_req_rslt : arp_req_rslt_type;
 
--Outputs
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
signal mac_tx_req : std_logic;
signal mac_data_out_valid : std_logic;
signal mac_data_out_last : std_logic;
signal mac_data_out_first : std_logic;
signal mac_data_out : std_logic_vector(7 downto 0);
signal arp_req_req : arp_req_req_type;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IPv4_TX PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
clk => clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
mac_data_out_ready => mac_data_out_ready,
mac_data_out_valid => mac_data_out_valid,
mac_data_out_first => mac_data_out_first,
mac_data_out_last => mac_data_out_last,
mac_data_out => mac_data_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
ip_tx_start <= '0';
mac_tx_granted <= '0';
mac_data_out_ready <= '0';
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
arp_req_rslt.got_mac <= '0';
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:35:58 06/03/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4_TX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added test for IP broadcast tx
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
 
-- insert stimulus here
------------
-- TEST 1 -- basic functional tx test with some delays for arp and chn access
------------
report "T1: basic functional tx test with some delays for arp and chn access";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0008";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx_start <= '1';
wait for clk_period;
ip_tx_start <= '0';
arp_req_rslt.got_mac <= '0';
arp_req_rslt.got_err <= '0';
assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
wait for clk_period*10; -- simulate arp lookup time
arp_req_rslt.mac <= x"050423271016";
arp_req_rslt.got_mac <= '1';
 
wait for clk_period*2;
assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
 
wait for clk_period*10; -- simulate mac chn access time
mac_tx_granted <= '1';
wait for clk_period*2;
mac_data_out_ready <= '1';
assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
 
wait for clk_period;
 
assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
wait for clk_period;
assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
-- wait until in eth hdr
wait for clk_period*3;
-- go mac not ready for 2 clocks
mac_data_out_ready <= '0';
wait for clk_period*2;
mac_data_out_ready <= '1';
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"56"; wait for clk_period;
-- delay data in for 1 clk cycle
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out <= x"57"; wait for clk_period;
ip_tx.data.data_out_valid <= '1'; wait for clk_period;
ip_tx.data.data_out <= x"58"; wait for clk_period;
ip_tx.data.data_out <= x"59"; wait for clk_period;
-- delay mac ready for 2 clk cycles
mac_data_out_ready <= '0';
ip_tx.data.data_out <= x"5a"; wait for clk_period;
assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
ip_tx.data.data_out <= x"5a"; wait for clk_period;
mac_data_out_ready <= '1';
wait until ip_tx_data_out_ready = '1';
wait for clk_period;
assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
ip_tx.data.data_out <= x"5b"; wait for clk_period;
ip_tx.data.data_out <= x"5c"; wait for clk_period;
ip_tx.data.data_out <= x"5d";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
 
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
mac_tx_granted <= '0';
wait for clk_period*2;
 
------------
-- TEST 2 -- basic functional tx test with no delays for arp and chn access
------------
report "T2: basic functional tx test with no delays for arp and chn access";
ip_tx.hdr.protocol <= x"11";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx_start <= '1';
wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
arp_req_rslt.got_mac <= '0';
assert arp_req_req.lookup_req = '1' report "T2: lookup_req not set on tx start";
assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
wait for clk_period; -- simulate arp lookup time
arp_req_rslt.mac <= x"050423271016";
arp_req_rslt.got_mac <= '1';
 
wait for clk_period*2;
assert arp_req_req.lookup_req = '0' report "T2: lookup_req not clear after setting";
assert mac_tx_req = '1' report "T2: mac_tx_req not set after getting mac";
 
wait for clk_period; -- simulate mac chn access time
mac_tx_granted <= '1';
wait for clk_period*2;
mac_data_out_ready <= '1';
 
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"c1"; wait for clk_period;
ip_tx.data.data_out <= x"c2"; wait for clk_period;
ip_tx.data.data_out <= x"c3"; wait for clk_period;
ip_tx.data.data_out <= x"c4"; wait for clk_period;
ip_tx.data.data_out <= x"c5"; wait for clk_period;
ip_tx.data.data_out <= x"c6";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
 
assert mac_data_out_last = '1' report "T2: mac_datda_out_last not set on last byte";
 
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
 
assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T2: mac_tx_req held on too long after TX";
mac_tx_granted <= '0';
wait for clk_period*2;
 
------------
-- TEST 3 -- tx test for IP broadcast, should be no arp req
------------
report "T3: tx test for IP broadcast, should be no arp req";
ip_tx.hdr.protocol <= x"11";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"ffffffff";
ip_tx_start <= '1';
wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
arp_req_rslt.got_mac <= '0';
assert arp_req_req.lookup_req = '0' report "T3: its trying to do an ARP req tx start";
assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
wait for clk_period; -- simulate mac chn access time
mac_tx_granted <= '1';
wait for clk_period*2;
mac_data_out_ready <= '1';
 
assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"c1"; wait for clk_period;
ip_tx.data.data_out <= x"c2"; wait for clk_period;
ip_tx.data.data_out <= x"c3"; wait for clk_period;
ip_tx.data.data_out <= x"c4"; wait for clk_period;
ip_tx.data.data_out <= x"c5"; wait for clk_period;
ip_tx.data.data_out <= x"c6";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
 
assert mac_data_out_last = '1' report "T3: mac_datda_out_last not set on last byte";
 
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
 
assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T3: mac_tx_req held on too long after TX";
mac_tx_granted <= '0';
wait for clk_period*2;
 
 
report "--- end of tests ---";
 
wait;
end process;
 
END;
 
entity IPv4_TX_tb is
end IPv4_TX_tb;
 
architecture behavior of IPv4_TX_tb is
 
-- Component Declaration for the Unit Under Test (UUT)
component IPv4_TX
port(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
 
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end component;
 
 
--Inputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_granted : std_logic := '0';
signal mac_data_out_ready : std_logic := '0';
signal arp_req_rslt : arp_req_rslt_type;
 
--Outputs
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
signal mac_tx_req : std_logic;
signal mac_data_out_valid : std_logic;
signal mac_data_out_last : std_logic;
signal mac_data_out_first : std_logic;
signal mac_data_out : std_logic_vector(7 downto 0);
signal arp_req_req : arp_req_req_type;
 
-- Clock period definitions
constant clk_period : time := 8 ns;
begin
 
-- Instantiate the Unit Under Test (UUT)
uut : IPv4_TX port map (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
clk => clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
mac_data_out_ready => mac_data_out_ready,
mac_data_out_valid => mac_data_out_valid,
mac_data_out_first => mac_data_out_first,
mac_data_out_last => mac_data_out_last,
mac_data_out => mac_data_out
);
 
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
 
-- Stimulus process
stim_proc : process
begin
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
ip_tx_start <= '0';
mac_tx_granted <= '0';
mac_data_out_ready <= '0';
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
arp_req_rslt.got_mac <= '0';
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
 
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait until clk = '1';
wait for clk_period*5;
wait until clk = '1';
 
-- check reset conditions
assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
 
-- insert stimulus here
 
------------
-- TEST 1 -- basic functional tx test with some delays for arp and chn access
------------
 
report "T1: basic functional tx test with some delays for arp and chn access";
 
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0008";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx_start <= '1';
wait until clk = '1';
ip_tx_start <= '0';
arp_req_rslt.got_mac <= '0';
arp_req_rslt.got_err <= '0';
 
wait until clk = '1';
assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
 
wait for clk_period*10; -- simulate arp lookup time
wait until clk = '1';
arp_req_rslt.mac <= x"050423271016";
arp_req_rslt.got_mac <= '1';
 
wait until clk = '1';
wait until clk = '1';
assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
 
wait for clk_period*10; -- simulate mac chn access time
wait until clk = '1';
mac_tx_granted <= '1';
wait until clk = '1'; wait until clk = '1'; mac_data_out_ready <= '1';
assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
 
wait until clk = '1';
 
assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
wait until clk = '1';
assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
 
-- wait until in eth hdr
wait for clk_period*3;
wait until clk = '1';
-- go mac not ready for 2 clocks
mac_data_out_ready <= '0';
wait until clk = '1'; wait until clk = '1'; wait until clk = '1';
mac_data_out_ready <= '1';
 
 
wait until ip_tx_data_out_ready = '1';
wait until clk = '1';
 
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"56"; wait until clk = '1';
-- delay data in for 1 clk cycle
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out <= x"57"; wait until clk = '1';
ip_tx.data.data_out_valid <= '1'; wait until clk = '1';
ip_tx.data.data_out <= x"58"; wait until clk = '1';
ip_tx.data.data_out <= x"59"; wait until clk = '1';
--wait for clk_period;
 
-- delay mac ready for 2 clk cycles
mac_data_out_ready <= '0';
ip_tx.data.data_out <= x"5a"; wait until clk = '1';
--wait for clk_period;
assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
 
ip_tx.data.data_out <= x"5a"; wait until clk = '1';
--wait for clk_period;
mac_data_out_ready <= '1';
wait until ip_tx_data_out_ready = '1';
wait until clk = '1';
-- wait for clk_period;
assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
ip_tx.data.data_out <= x"5b"; wait until clk = '1';
ip_tx.data.data_out <= x"5c"; wait until clk = '1';
 
ip_tx.data.data_out <= x"5d";
ip_tx.data.data_out_last <= '1';
wait until clk = '1';
assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait until clk = '1'; wait until clk = '1';
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
 
mac_tx_granted <= '0';
wait until clk = '1'; wait until clk = '1';
------------
-- TEST 2 -- basic functional tx test with no delays for arp and chn access
------------
 
report "T2: basic functional tx test with no delays for arp and chn access";
 
ip_tx.hdr.protocol <= x"11";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx_start <= '1';
wait until clk = '1';
ip_tx_start <= '0'; wait until clk = '1';
arp_req_rslt.got_mac <= '0';
 
assert arp_req_req.lookup_req = '1' report "T2: lookup_req not set on tx start";
assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
 
wait until clk = '1'; -- simulate arp lookup time
arp_req_rslt.mac <= x"050423271016";
arp_req_rslt.got_mac <= '1';
 
wait until clk = '1'; wait until clk = '1';
assert arp_req_req.lookup_req = '0' report "T2: lookup_req not clear after setting";
assert mac_tx_req = '1' report "T2: mac_tx_req not set after getting mac";
 
wait until clk = '1'; -- simulate mac chn access time
mac_tx_granted <= '1';
wait until clk = '1'; wait until clk = '1'; mac_data_out_ready <= '1';
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
 
wait until ip_tx_data_out_ready = '1';
 
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"c1"; wait until clk = '1';
ip_tx.data.data_out <= x"c2"; wait until clk = '1';
ip_tx.data.data_out <= x"c3"; wait until clk = '1';
ip_tx.data.data_out <= x"c4"; wait until clk = '1';
ip_tx.data.data_out <= x"c5"; wait until clk = '1';
 
ip_tx.data.data_out <= x"c6";
ip_tx.data.data_out_last <= '1';
wait until clk = '1';
 
assert mac_data_out_last = '1' report "T2: mac_datda_out_last not set on last byte";
 
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait until clk = '1'; wait until clk = '1';
assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T2: mac_tx_req held on too long after TX";
 
mac_tx_granted <= '0';
wait until clk = '1'; wait until clk = '1';
------------
-- TEST 3 -- tx test for IP broadcast, should be no arp req
------------
 
report "T3: tx test for IP broadcast, should be no arp req";
 
ip_tx.hdr.protocol <= x"11";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"ffffffff";
ip_tx_start <= '1';
wait until clk = '1';
ip_tx_start <= '0'; wait until clk = '1';
arp_req_rslt.got_mac <= '0';
 
assert arp_req_req.lookup_req = '0' report "T3: its trying to do an ARP req tx start";
assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
 
wait until clk = '1'; -- simulate mac chn access time
mac_tx_granted <= '1';
wait until clk = '1'; wait until clk = '1'; mac_data_out_ready <= '1';
 
assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
 
wait until ip_tx_data_out_ready = '1';
 
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"c1"; wait until clk = '1';
ip_tx.data.data_out <= x"c2"; wait until clk = '1';
ip_tx.data.data_out <= x"c3"; wait until clk = '1';
ip_tx.data.data_out <= x"c4"; wait until clk = '1';
ip_tx.data.data_out <= x"c5"; wait until clk = '1';
 
ip_tx.data.data_out <= x"c6";
ip_tx.data.data_out_last <= '1';
wait until clk = '1';
 
assert mac_data_out_last = '1' report "T3: mac_datda_out_last not set on last byte";
 
 
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait until clk = '1'; wait until clk = '1';
assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be IPTX_RESULT_SENT";
assert mac_tx_req = '0' report "T3: mac_tx_req held on too long after TX";
 
mac_tx_granted <= '0';
wait until clk = '1'; wait until clk = '1';
 
report "--- end of tests ---";
 
wait;
end process;
 
end;
/bench/vhdl/UDP_complete_nomac_tb.vhd
1016,12 → 1016,12
assert mac_tx_tdata = x"05" report "T6: incorrect sndr ip 2"; wait for clk_period;
assert mac_tx_tdata = x"09" report "T6: incorrect sndr ip 3"; wait for clk_period;
 
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 0"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 1"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 2"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 3"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 4"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 5"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T6: incorrect trg mac 0"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T6: incorrect trg mac 1"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T6: incorrect trg mac 2"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T6: incorrect trg mac 3"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T6: incorrect trg mac 4"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T6: incorrect trg mac 5"; wait for clk_period;
 
assert mac_tx_tdata = x"c0" report "T6: incorrect trg ip 0"; wait for clk_period;
assert mac_tx_tdata = x"bb" report "T6: incorrect trg ip 1"; wait for clk_period;
1146,141 → 1146,8
mac_rx_tvalid <= '0';
wait for clk_period;
report "T7: waiting for mac ARP REQ data tx";
if mac_tx_tvalid = '0' then
wait until mac_tx_tvalid = '1';
wait for clk_period;
end if;
report "T7: starting mac ARP REQ data tx";
-- check the ARP REQ mac data being transmitted
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 0"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 1"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 2"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 3"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 4"; wait for clk_period;
assert mac_tx_tdata = x"ff" report "T7: arp incorrect dst mac 5"; wait for clk_period;
 
assert mac_tx_tdata = x"00" report "T7: arp incorrect src mac 0"; wait for clk_period;
assert mac_tx_tdata = x"23" report "T7: arp incorrect src mac 1"; wait for clk_period;
assert mac_tx_tdata = x"20" report "T7: arp incorrect src mac 2"; wait for clk_period;
assert mac_tx_tdata = x"21" report "T7: arp incorrect src mac 3"; wait for clk_period;
assert mac_tx_tdata = x"22" report "T7: arp incorrect src mac 4"; wait for clk_period;
assert mac_tx_tdata = x"23" report "T7: arp incorrect src mac 5"; wait for clk_period;
 
assert mac_tx_tdata = x"08" report "T7: arp incorrect pkt_type 0"; wait for clk_period;
assert mac_tx_tdata = x"06" report "T7: arp incorrect pkt type 1"; wait for clk_period;
 
assert mac_tx_tdata = x"00" report "T7: arp incorrect HW type.0"; wait for clk_period;
assert mac_tx_tdata = x"01" report "T7: arp incorrect HW type.1"; wait for clk_period;
assert mac_tx_tdata = x"08" report "T7: arp incorrect prot.0"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: arp incorrect prot.1"; wait for clk_period;
assert mac_tx_tdata = x"06" report "T7: arp incorrect HW size"; wait for clk_period;
assert mac_tx_tdata = x"04" report "T7: arp incorrect prot size"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: arp incorrect opcode.0"; wait for clk_period;
assert mac_tx_tdata = x"01" report "T7: arp incorrect opcode.1"; wait for clk_period;
 
assert mac_tx_tdata = x"00" report "T7: arp incorrect sndr mac 0"; wait for clk_period;
assert mac_tx_tdata = x"23" report "T7: arp incorrect sndr mac 1"; wait for clk_period;
assert mac_tx_tdata = x"20" report "T7: arp incorrect sndr mac 2"; wait for clk_period;
assert mac_tx_tdata = x"21" report "T7: arp incorrect sndr mac 3"; wait for clk_period;
assert mac_tx_tdata = x"22" report "T7: arp incorrect sndr mac 4"; wait for clk_period;
assert mac_tx_tdata = x"23" report "T7: arp incorrect sndr mac 5"; wait for clk_period;
 
assert mac_tx_tdata = x"c0" report "T7: arp incorrect sndr ip 0"; wait for clk_period;
assert mac_tx_tdata = x"a8" report "T7: arp incorrect sndr ip 1"; wait for clk_period;
assert mac_tx_tdata = x"05" report "T7: arp incorrect sndr ip 2"; wait for clk_period;
assert mac_tx_tdata = x"09" report "T7: arp incorrect sndr ip 3"; wait for clk_period;
 
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 0"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 1"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 2"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 3"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 4"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: arp incorrect trg mac 5"; wait for clk_period;
 
assert mac_tx_tdata = x"c0" report "T7: arp incorrect trg ip 0"; wait for clk_period;
assert mac_tx_tdata = x"a8" report "T7: arp incorrect trg ip 1"; wait for clk_period;
assert mac_tx_tdata = x"05" report "T7: arp incorrect trg ip 2";
assert mac_tx_tlast = '0' report "T7: arp tlast asserted too soon";
wait for clk_period;
-- there should be no ARP exchange as this entry should already be cached.
assert mac_tx_tdata = x"01" report "T7: arp incorrect trg ip 3";
assert mac_tx_tlast = '1' report "T7: arp tlast should be set";
wait for clk_period;
 
assert udp_tx_result = IPTX_RESULT_SENDING report "T7: arp TX should still be in sending phase";
wait for clk_period*5;
report "T7: feeding in an arp reply: I have c0180501 at mac 021503230454";
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"15"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"06"; wait for clk_period;
-- HW type
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Protocol type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- HW size
mac_rx_tdata <= x"06"; wait for clk_period;
-- protocol size
mac_rx_tdata <= x"04"; wait for clk_period;
-- Opcode
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"02"; wait for clk_period;
-- Sender MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"15"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- Sender IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Target MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- Target IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '1';
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait for clk_period;
 
assert udp_tx_result = IPTX_RESULT_SENDING report "T7: TX should still be sending";
 
report "T7: waiting for mac data tx";
if mac_tx_tvalid = '0' then
wait until mac_tx_tvalid = '1';
1289,12 → 1156,12
report "T7: starting mac data tx";
-- check the mac data being transmitted
assert mac_tx_tdata = x"02" report "T7: incorrect dst mac 0"; wait for clk_period;
assert mac_tx_tdata = x"15" report "T7: incorrect dst mac 1"; wait for clk_period;
assert mac_tx_tdata = x"03" report "T7: incorrect dst mac 2"; wait for clk_period;
assert mac_tx_tdata = x"23" report "T7: incorrect dst mac 3"; wait for clk_period;
assert mac_tx_tdata = x"04" report "T7: incorrect dst mac 4"; wait for clk_period;
assert mac_tx_tdata = x"54" report "T7: incorrect dst mac 5"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T7: incorrect dst mac 0"; wait for clk_period;
assert mac_tx_tdata = x"23" report "T7: incorrect dst mac 1"; wait for clk_period;
assert mac_tx_tdata = x"18" report "T7: incorrect dst mac 2"; wait for clk_period;
assert mac_tx_tdata = x"29" report "T7: incorrect dst mac 3"; wait for clk_period;
assert mac_tx_tdata = x"26" report "T7: incorrect dst mac 4"; wait for clk_period;
assert mac_tx_tdata = x"7c" report "T7: incorrect dst mac 5"; wait for clk_period;
 
assert mac_tx_tdata = x"00" report "T7: incorrect src mac 0"; wait for clk_period;
assert mac_tx_tdata = x"23" report "T7: incorrect src mac 1"; wait for clk_period;
/bench/vhdl/arp_STORE_tb.vhd
120,7 → 120,7
assert read_result.status = NOT_FOUND report "T1: expected NOT_FOUND";
wait for clk_period;
read_req.req <= '0';
wait for clk_period;
wait for clk_period*2;
assert read_result.status = IDLE report "T1: expected IDLE";
assert entry_count = x"00" report "T1: wrong entry count";
 
144,7 → 144,7
assert read_result.entry.mac = x"002398127645" report "T3: wrong mac addr";
wait for clk_period;
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T3: expected IDLE";
 
report "T4 - check unable to find missing entry with one entry in store";
155,7 → 155,7
assert read_result.status = NOT_FOUND report "T4: expected NOT_FOUND";
wait for clk_period;
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T4: expected IDLE";
 
report "T5 - insert 2nd entry into store and check can find both entries";
175,7 → 175,7
assert read_result.entry.ip = x"12345678" report "T5.1: wrong ip addr";
assert read_result.entry.mac = x"002398127645" report "T5.1: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T5.1: expected IDLE";
read_req.ip <= x"12345679";
read_req.req <= '1';
185,7 → 185,7
assert read_result.entry.ip = x"12345679" report "T5.2: wrong ip addr";
assert read_result.entry.mac = x"101202303404" report "T5.2: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T5.2: expected IDLE";
 
report "T6 - insert 2 more entries so that the store is full. check can find all";
212,7 → 212,7
assert read_result.entry.ip = x"12345678" report "T6.1: wrong ip addr";
assert read_result.entry.mac = x"002398127645" report "T6.1: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T6.1: expected IDLE";
read_req.ip <= x"12345679";
read_req.req <= '1';
222,7 → 222,7
assert read_result.entry.ip = x"12345679" report "T6.2: wrong ip addr";
assert read_result.entry.mac = x"101202303404" report "T6.2: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T6.2: expected IDLE";
read_req.ip <= x"1234567a";
read_req.req <= '1';
232,7 → 232,7
assert read_result.entry.ip = x"1234567a" report "T6.3: wrong ip addr";
assert read_result.entry.mac = x"10120230340a" report "T6.3: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T6.3: expected IDLE";
read_req.ip <= x"1234567b";
read_req.req <= '1';
242,7 → 242,7
assert read_result.entry.ip = x"1234567b" report "T6.4: wrong ip addr";
assert read_result.entry.mac = x"10120230340b" report "T6.4: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T6.4: expected IDLE";
 
report "T7 - with store full, check that we dont find missing item";
252,7 → 252,7
wait for clk_period;
assert read_result.status = NOT_FOUND report "T7: expected NOT_FOUND";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T7: expected IDLE";
 
report "T8 - insert additional entry into store - will erase one of the others";
272,7 → 272,7
assert read_result.entry.ip = x"12345699" report "T8: wrong ip addr";
assert read_result.entry.mac = x"992398127699" report "T8: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T8: expected IDLE";
 
report "T9 - clear the store and ensure cant find something that was there";
287,7 → 287,7
wait for clk_period;
assert read_result.status = NOT_FOUND report "T9: expected NOT_FOUND";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T9: expected IDLE";
 
report "T10 - refill the store with three entries";
323,7 → 323,7
assert read_result.entry.ip = x"12345676" report "T11.1: wrong ip addr";
assert read_result.entry.mac = x"10120230340b" report "T11.1: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T11.1: expected IDLE";
write_req.entry.ip <= x"12345676";
write_req.entry.mac <= x"10120990340b";
340,7 → 340,7
assert read_result.entry.ip = x"12345676" report "T11.2: wrong ip addr";
assert read_result.entry.mac = x"10120990340b" report "T11.2: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T11.2: expected IDLE";
 
report "T12 - check 2nd write at beginning";
374,7 → 374,7
assert read_result.entry.ip = x"12345678" report "T12.4: wrong ip addr";
assert read_result.entry.mac = x"002398127647" report "T12.4: wrong mac addr";
read_req.req <= '0';
wait for clk_period*2;
wait for clk_period*3;
assert read_result.status = IDLE report "T12.5: expected IDLE";
 
report "--- end of tests ---";
/bench/vhdl/UDP_av2_complete_nomac_tb.vhd
1016,12 → 1016,12
assert mac_tx_tdata = x"05" report "T6: incorrect sndr ip 2"; wait for clk_period;
assert mac_tx_tdata = x"09" report "T6: incorrect sndr ip 3"; wait for clk_period;
 
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 0"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 1"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 2"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 3"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 4"; wait for clk_period;
assert mac_tx_tdata = x"00" report "T6: incorrect trg mac 5"; wait for clk_period;
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 0"; wait for clk_period;
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 1"; wait for clk_period;
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 2"; wait for clk_period;
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 3"; wait for clk_period;
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 4"; wait for clk_period;
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 5"; wait for clk_period;
 
assert mac_tx_tdata = x"c0" report "T6: incorrect trg ip 0"; wait for clk_period;
assert mac_tx_tdata = x"bb" report "T6: incorrect trg ip 1"; wait for clk_period;
/rtl/vhdl/UDP_RX.vhd
1,343 → 1,343
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP RX
-- doesnt check the checsum
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
 
entity UDP_RX is
Port (
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
end UDP_RX;
 
architecture Behavioral of UDP_RX is
 
type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP RX
-- doesnt check the checsum
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
 
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
signal udp_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal rx_count_val : unsigned (15 downto 0);
signal set_sph : std_logic;
signal set_spl : std_logic;
signal set_dph : std_logic;
signal set_dpl : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_udp_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_src_ip : std_logic;
signal set_data_last : std_logic;
 
entity UDP_RX is
port (
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in std_logic;
reset : in std_logic;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
end UDP_RX;
 
architecture Behavioral of UDP_RX is
 
type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
 
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
 
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
signal udp_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
 
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal rx_count_val : unsigned (15 downto 0);
signal set_sph : std_logic;
signal set_spl : std_logic;
signal set_dph : std_logic;
signal set_dpl : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_udp_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_src_ip : std_logic;
signal set_data_last : std_logic;
 
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
 
 
begin
 
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
 
rx_combinatorial : process (
-- input signals
ip_rx, ip_rx_start,
-- state variables
rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
)
begin
-- set output followers
udp_rx_start <= udp_rx_start_reg;
udp_rxo.hdr.is_valid <= hdr_valid_reg;
udp_rxo.hdr.data_length <= data_len;
udp_rxo.hdr.src_port <= src_port;
udp_rxo.hdr.dst_port <= dst_port;
udp_rxo.hdr.src_ip_addr <= src_ip_addr;
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
udp_rxo.data.data_in <= ip_rx.data.data_in;
udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
udp_rxo.data.data_in_last <= set_data_last;
else
udp_rxo.data.data_in <= (others => '0');
udp_rxo.data.data_in_valid <= '0';
udp_rxo.data.data_in_last <= '0';
end if;
 
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_sph <= '0';
set_spl <= '0';
set_dph <= '0';
set_dpl <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_udp_rx_start <= HOLD;
set_hdr_valid <= HOLD;
dataval <= (others => '0');
set_src_ip <= '0';
rx_count_val <= (others => '0');
set_data_last <= '0';
-- determine event (if any)
if ip_rx.data.data_in_valid = '1' then
rx_event <= DATA;
dataval <= ip_rx.data.data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.hdr.protocol = x"11" then
-- UDP protocol
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
set_src_ip <= '1';
set_sph <= '1';
next_rx_state <= UDP_HDR;
set_rx_state <= '1';
else
-- non-UDP protocol - ignore this pkt
set_hdr_valid <= CLR;
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
end case;
begin
 
when UDP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0007" then
rx_count_mode <= SET_VAL;
rx_count_val <= x"0001";
next_rx_state <= USER_DATA;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if ip_rx.data.data_in_last = '1' then
next_rx_state <= ERR;
set_rx_state <= '1';
else
case rx_count is
when x"0000" => set_sph <= '1';
when x"0001" => set_spl <= '1';
when x"0002" => set_dph <= '1';
when x"0003" => set_dpl <= '1';
 
when x"0004" => set_len_H <= '1';
when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
when x"0006" => -- ignore checksum values
when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
 
when others => -- ignore other bytes in udp header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_udp_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_udp_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
-- TODO need to mark frame as errored
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
set_data_last <= '1';
end if;
end if;
end case;
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
 
when ERR =>
if ip_rx.data.data_in_last = '0' then
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
rx_combinatorial : process (
-- input signals
ip_rx, ip_rx_start,
-- state variables
rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
)
begin
-- set output followers
udp_rx_start <= udp_rx_start_reg;
udp_rxo.hdr.is_valid <= hdr_valid_reg;
udp_rxo.hdr.data_length <= data_len;
udp_rxo.hdr.src_port <= src_port;
udp_rxo.hdr.dst_port <= dst_port;
udp_rxo.hdr.src_ip_addr <= src_ip_addr;
 
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
 
 
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
udp_rxo.data.data_in <= ip_rx.data.data_in;
udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
udp_rxo.data.data_in_last <= set_data_last;
else
udp_rxo.data.data_in <= (others => '0');
udp_rxo.data.data_in_valid <= '0';
udp_rxo.data.data_in_last <= '0';
end if;
 
rx_sequential : process (clk,reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_port <= (others => '0');
dst_port <= (others => '0');
data_len <= (others => '0');
udp_rx_start_reg <= '0';
hdr_valid_reg <= '0';
src_ip_addr <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
 
-- port number capture
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
 
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
else
data_len <= data_len;
end if;
case set_udp_rx_start is
when SET => udp_rx_start_reg <= '1';
when CLR => udp_rx_start_reg <= '0';
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
end case;
-- capture src IP address
if set_src_ip = '1' then
src_ip_addr <= ip_rx.hdr.src_ip_addr;
else
src_ip_addr <= src_ip_addr;
end if;
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
end if;
end if;
end process;
 
end Behavioral;
 
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_sph <= '0';
set_spl <= '0';
set_dph <= '0';
set_dpl <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_udp_rx_start <= HOLD;
set_hdr_valid <= HOLD;
dataval <= (others => '0');
set_src_ip <= '0';
rx_count_val <= (others => '0');
set_data_last <= '0';
 
-- determine event (if any)
if ip_rx.data.data_in_valid = '1' then
rx_event <= DATA;
dataval <= ip_rx.data.data_in;
end if;
 
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.hdr.protocol = x"11" then
-- UDP protocol
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
set_src_ip <= '1';
set_sph <= '1';
next_rx_state <= UDP_HDR;
set_rx_state <= '1';
else
-- non-UDP protocol - ignore this pkt
set_hdr_valid <= CLR;
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
end case;
 
when UDP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0007" then
rx_count_mode <= SET_VAL;
rx_count_val <= x"0001";
next_rx_state <= USER_DATA;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if ip_rx.data.data_in_last = '1' then
next_rx_state <= ERR;
set_rx_state <= '1';
else
case rx_count is
when x"0000" => set_sph <= '1';
when x"0001" => set_spl <= '1';
when x"0002" => set_dph <= '1';
when x"0003" => set_dpl <= '1';
 
when x"0004" => set_len_H <= '1';
when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
 
when x"0006" => -- ignore checksum values
when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
 
 
when others => -- ignore other bytes in udp header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_udp_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_udp_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
-- TODO need to mark frame as errored
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
set_data_last <= '1';
end if;
end if;
end case;
 
when ERR =>
if ip_rx.data.data_in_last = '0' then
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
 
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
 
 
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
 
rx_sequential : process (clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
src_port <= (others => '0');
dst_port <= (others => '0');
data_len <= (others => '0');
udp_rx_start_reg <= '0';
hdr_valid_reg <= '0';
src_ip_addr <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
 
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
 
-- port number capture
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
 
if (set_len_H = '1') then
data_len (15 downto 8) <= dataval;
data_len (7 downto 0) <= x"00";
elsif (set_len_L = '1') then
-- compute data length, taking into account that we need to subtract the header length
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
else
data_len <= data_len;
end if;
 
case set_udp_rx_start is
when SET => udp_rx_start_reg <= '1';
when CLR => udp_rx_start_reg <= '0';
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
end case;
 
-- capture src IP address
if set_src_ip = '1' then
src_ip_addr <= ip_rx.hdr.src_ip_addr;
else
src_ip_addr <= src_ip_addr;
end if;
 
case set_hdr_valid is
when SET => hdr_valid_reg <= '1';
when CLR => hdr_valid_reg <= '0';
when HOLD => hdr_valid_reg <= hdr_valid_reg;
end case;
end if;
end if;
end process;
 
end Behavioral;
 
/rtl/vhdl/IP_complete_nomac.vhd
1,324 → 1,365
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP (but no MAC)
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:16 06/04/2011
-- Design Name:
-- Module Name: IP_complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implements complete IP stack with ARP (but no MAC)
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.arp;
use work.arpv2;
 
entity IP_complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end IP_complete_nomac;
 
 
architecture structural of IP_complete_nomac is
 
COMPONENT IPv4
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
COMPONENT arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
END COMPONENT;
COMPONENT tx_arbitrator
PORT(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
 
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
END COMPONENT;
 
-------------------
-- Configuration
--
-- Enable one of the following to specify which
-- implementation of the ARP layer to use
-------------------
 
 
-- for arp_layer : arp use entity work.arp; -- single slot arbitrator
for arp_layer : arp use entity work.arpv2; -- multislot arbitrator
 
 
 
---------------------------
-- Signals
---------------------------
-- ARP REQUEST
signal arp_req_req_int : arp_req_req_type;
signal arp_req_rslt_int : arp_req_rslt_type;
-- MAC arbitration busses
signal ip_mac_req : std_logic;
signal ip_mac_grant : std_logic;
signal ip_mac_data_out : std_logic_vector (7 downto 0);
signal ip_mac_valid : std_logic;
signal ip_mac_first : std_logic;
signal ip_mac_last : std_logic;
signal arp_mac_req : std_logic;
signal arp_mac_grant : std_logic;
signal arp_mac_data_out : std_logic_vector (7 downto 0);
signal arp_mac_valid : std_logic;
signal arp_mac_first : std_logic;
signal arp_mac_last : std_logic;
-- MAC RX bus
signal mac_rx_tready_int : std_logic;
-- MAC TX bus
signal mac_tx_tdata_int : std_logic_vector (7 downto 0);
signal mac_tx_tvalid_int : std_logic;
signal mac_tx_tfirst_int : std_logic;
signal mac_tx_tlast_int : std_logic;
-- control signals
signal mac_tx_granted_int : std_logic;
 
begin
 
mac_rx_tready_int <= '1'; -- enable the mac receiver
-- set followers
mac_tx_tdata <= mac_tx_tdata_int;
mac_tx_tvalid <= mac_tx_tvalid_int;
mac_tx_tfirst <= mac_tx_tfirst_int;
mac_tx_tlast <= mac_tx_tlast_int;
mac_rx_tready <= mac_rx_tready_int;
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
 
IP_layer : IPv4 PORT MAP
(
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready=> ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
rx_pkt_count => ip_pkt_count,
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
mac_tx_req => ip_mac_req,
mac_tx_granted => ip_mac_grant,
mac_data_out_ready => mac_tx_tready,
mac_data_out_valid => ip_mac_valid,
mac_data_out_first => ip_mac_first,
mac_data_out_last => ip_mac_last,
mac_data_out => ip_mac_data_out,
mac_data_in => mac_rx_tdata,
mac_data_in_valid => mac_rx_tvalid,
mac_data_in_last => mac_rx_tlast
);
------------------------------------------------------------------------------
-- Instantiate the ARP layer
------------------------------------------------------------------------------
arp_layer : arp
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
Port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
 
 
------------------------------------------------------------------------------
-- Instantiate the TX Arbitrator
------------------------------------------------------------------------------
mac_tx_arb : tx_arbitrator
Port map(
clk => tx_clk,
reset => reset,
req_1 => ip_mac_req,
grant_1 => ip_mac_grant,
data_1 => ip_mac_data_out,
valid_1 => ip_mac_valid,
first_1 => ip_mac_first,
last_1 => ip_mac_last,
 
req_2 => arp_mac_req,
grant_2 => arp_mac_grant,
data_2 => arp_mac_data_out,
valid_2 => arp_mac_valid,
first_2 => arp_mac_first,
last_2 => arp_mac_last,
data => mac_tx_tdata_int,
valid => mac_tx_tvalid_int,
first => mac_tx_tfirst_int,
last => mac_tx_tlast_int
);
 
end structural;
 
 
 
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
use work.arp;
use work.arpv2;
 
entity IP_complete_nomac is
generic (
use_arpv2 : boolean := true; -- use ARP with multipule entries. for signel entry, set
-- to false
no_default_gateway : boolean := false; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end IP_complete_nomac;
 
 
architecture structural of IP_complete_nomac is
 
component IPv4
port(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end component;
 
component arp
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl)
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl)
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end component;
 
component tx_arbitrator
port(
clk : in std_logic;
reset : in std_logic;
 
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
 
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
 
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end component;
 
 
-------------------
-- Configuration
--
-- Enable one of the following to specify which
-- implementation of the ARP layer to use
-------------------
 
 
-- for arp_layer : arp use entity work.arp; -- single slot arbitrator
-- for arp_layer : arp use entity work.arpv2; -- multislot arbitrator
 
 
 
---------------------------
-- Signals
---------------------------
 
-- ARP REQUEST
signal arp_req_req_int : arp_req_req_type;
signal arp_req_rslt_int : arp_req_rslt_type;
-- MAC arbitration busses
signal ip_mac_req : std_logic;
signal ip_mac_grant : std_logic;
signal ip_mac_data_out : std_logic_vector (7 downto 0);
signal ip_mac_valid : std_logic;
signal ip_mac_first : std_logic;
signal ip_mac_last : std_logic;
signal arp_mac_req : std_logic;
signal arp_mac_grant : std_logic;
signal arp_mac_data_out : std_logic_vector (7 downto 0);
signal arp_mac_valid : std_logic;
signal arp_mac_first : std_logic;
signal arp_mac_last : std_logic;
-- MAC RX bus
signal mac_rx_tready_int : std_logic;
-- MAC TX bus
signal mac_tx_tdata_int : std_logic_vector (7 downto 0);
signal mac_tx_tvalid_int : std_logic;
signal mac_tx_tfirst_int : std_logic;
signal mac_tx_tlast_int : std_logic;
-- control signals
signal mac_tx_granted_int : std_logic;
 
begin
 
mac_rx_tready_int <= '1'; -- enable the mac receiver
 
-- set followers
mac_tx_tdata <= mac_tx_tdata_int;
mac_tx_tvalid <= mac_tx_tvalid_int;
mac_tx_tfirst <= mac_tx_tfirst_int;
mac_tx_tlast <= mac_tx_tlast_int;
 
mac_rx_tready <= mac_rx_tready_int;
 
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
 
IP_layer : IPv4 port map
(
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
rx_pkt_count => ip_pkt_count,
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
mac_tx_req => ip_mac_req,
mac_tx_granted => ip_mac_grant,
mac_data_out_ready => mac_tx_tready,
mac_data_out_valid => ip_mac_valid,
mac_data_out_first => ip_mac_first,
mac_data_out_last => ip_mac_last,
mac_data_out => ip_mac_data_out,
mac_data_in => mac_rx_tdata,
mac_data_in_valid => mac_rx_tvalid,
mac_data_in_last => mac_rx_tlast
);
 
------------------------------------------------------------------------------
-- Instantiate the ARP layer
------------------------------------------------------------------------------
signle_entry_arp: if (not use_arpv2) generate
arp_layer : entity work.arp
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate signle_entry_arp;
 
multi_entry_arp: if (use_arpv2) generate
arp_layer : entity work.arpv2
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map(
-- request signals
arp_req_req => arp_req_req_int,
arp_req_rslt => arp_req_rslt_int,
-- rx signals
data_in_clk => rx_clk,
reset => reset,
data_in => mac_rx_tdata,
data_in_valid => mac_rx_tvalid,
data_in_last => mac_rx_tlast,
-- tx signals
mac_tx_req => arp_mac_req,
mac_tx_granted => arp_mac_grant,
data_out_clk => tx_clk,
data_out_ready => mac_tx_tready,
data_out_valid => arp_mac_valid,
data_out_first => arp_mac_first,
data_out_last => arp_mac_last,
data_out => arp_mac_data_out,
-- system signals
our_mac_address => our_mac_address,
our_ip_address => our_ip_address,
control => control.arp_controls,
req_count => arp_pkt_count
);
end generate multi_entry_arp;
 
------------------------------------------------------------------------------
-- Instantiate the TX Arbitrator
------------------------------------------------------------------------------
mac_tx_arb : tx_arbitrator
port map(
clk => tx_clk,
reset => reset,
 
req_1 => ip_mac_req,
grant_1 => ip_mac_grant,
data_1 => ip_mac_data_out,
valid_1 => ip_mac_valid,
first_1 => ip_mac_first,
last_1 => ip_mac_last,
 
req_2 => arp_mac_req,
grant_2 => arp_mac_grant,
data_2 => arp_mac_data_out,
valid_2 => arp_mac_valid,
first_2 => arp_mac_first,
last_2 => arp_mac_last,
 
data => mac_tx_tdata_int,
valid => mac_tx_tvalid_int,
first => mac_tx_tfirst_int,
last => mac_tx_tlast_int
);
 
end structural;
 
 
 
/rtl/vhdl/arp_SYNC.vhd
1,163 → 1,163
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:09:01 02/20/2012
-- Design Name:
-- Module Name: arp_SYNC - Behavioral - synchronises between rx and tx clock domains
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:09:01 02/20/2012
-- Design Name:
-- Module Name: arp_SYNC - Behavioral - synchronises between rx and tx clock domains
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.arp_types.all;
 
entity arp_SYNC is
Port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out STD_LOGIC_VECTOR (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end arp_SYNC;
 
architecture Behavioral of arp_SYNC is
 
type sync_state_t is (IDLE,HOLD1, HOLD2);
-- state registers
signal ip_entry_state : sync_state_t;
signal arp_entry_state : sync_state_t;
signal ip_entry_reg : STD_LOGIC_VECTOR (31 downto 0);
signal arp_entry_reg : arp_entry_t;
-- synchronisation registers
signal send_who_has_r1 : std_logic;
signal send_who_has_r2 : std_logic;
signal send_I_have_r1 : std_logic;
signal send_I_have_r2 : std_logic;
begin
 
combinatorial : process (
-- input signals
arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset,
-- state
ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg,
-- synchronisation registers
send_who_has_r1, send_who_has_r2,
send_I_have_r1, send_I_have_r2
)
begin
-- set output followers
send_who_has <= send_who_has_r2;
ip_entry <= ip_entry_reg;
send_I_have <= send_I_have_r2;
arp_entry <= arp_entry_reg;
-- combinaltorial outputs
if I_have_received = '1' then
nwk_result_status <= RECEIVED;
else
nwk_result_status <= IDLE;
end if;
end process;
 
-- process for stablisising RX clock domain data registers
-- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles
-- during transfer to TX clk domain
rx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
ip_entry_reg <= (others => '0');
arp_entry_reg.ip <= (others => '0');
arp_entry_reg.mac <= (others => '0');
else
-- normal (non reset) processing
case ip_entry_state is
when IDLE =>
if arp_nwk_req.req = '1' then
ip_entry_reg <= arp_nwk_req.ip;
ip_entry_state <= HOLD1;
else
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= IDLE;
end if;
when HOLD1 =>
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= HOLD2;
when HOLD2 =>
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= IDLE;
end case;
 
case arp_entry_state is
when IDLE =>
if recv_who_has = '1' then
arp_entry_reg <= arp_entry_for_who_has;
arp_entry_state <= HOLD1;
else
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= IDLE;
end if;
when HOLD1 =>
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= HOLD2;
when HOLD2 =>
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= IDLE;
end case;
end if;
end if;
end process;
-- process for syncing to the TX clock domain
-- clocks control signals through 2 layers of tx clocking
tx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
send_who_has_r1 <= '0';
send_who_has_r2 <= '0';
send_I_have_r1 <= '0';
send_I_have_r2 <= '0';
else
-- normal (non reset) processing
send_who_has_r1 <= arp_nwk_req.req;
send_who_has_r2 <= send_who_has_r1;
send_I_have_r1 <= recv_who_has;
send_I_have_r2 <= send_I_have_r1;
end if;
end if;
end process;
 
 
end Behavioral;
 
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
 
entity arp_SYNC is
port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out std_logic_vector (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end arp_SYNC;
 
architecture Behavioral of arp_SYNC is
 
type sync_state_t is (IDLE, HOLD1, HOLD2);
 
-- state registers
signal ip_entry_state : sync_state_t;
signal arp_entry_state : sync_state_t;
signal ip_entry_reg : std_logic_vector (31 downto 0);
signal arp_entry_reg : arp_entry_t;
 
-- synchronisation registers
signal send_who_has_r1 : std_logic;
signal send_who_has_r2 : std_logic;
signal send_I_have_r1 : std_logic;
signal send_I_have_r2 : std_logic;
begin
 
combinatorial : process (
-- input signals
arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset,
-- state
ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg,
-- synchronisation registers
send_who_has_r1, send_who_has_r2,
send_I_have_r1, send_I_have_r2
)
begin
-- set output followers
send_who_has <= send_who_has_r2;
ip_entry <= ip_entry_reg;
send_I_have <= send_I_have_r2;
arp_entry <= arp_entry_reg;
 
-- combinaltorial outputs
if I_have_received = '1' then
nwk_result_status <= RECEIVED;
else
nwk_result_status <= IDLE;
end if;
end process;
 
-- process for stablisising RX clock domain data registers
-- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles
-- during transfer to TX clk domain
rx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
ip_entry_reg <= (others => '0');
arp_entry_reg.ip <= (others => '0');
arp_entry_reg.mac <= (others => '0');
else
-- normal (non reset) processing
case ip_entry_state is
when IDLE =>
if arp_nwk_req.req = '1' then
ip_entry_reg <= arp_nwk_req.ip;
ip_entry_state <= HOLD1;
else
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= IDLE;
end if;
when HOLD1 =>
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= HOLD2;
when HOLD2 =>
ip_entry_reg <= ip_entry_reg;
ip_entry_state <= IDLE;
end case;
 
case arp_entry_state is
when IDLE =>
if recv_who_has = '1' then
arp_entry_reg <= arp_entry_for_who_has;
arp_entry_state <= HOLD1;
else
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= IDLE;
end if;
when HOLD1 =>
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= HOLD2;
when HOLD2 =>
arp_entry_reg <= arp_entry_reg;
arp_entry_state <= IDLE;
end case;
end if;
end if;
end process;
 
-- process for syncing to the TX clock domain
-- clocks control signals through 2 layers of tx clocking
tx_sequential : process (tx_clk)
begin
if rising_edge(tx_clk) then
if reset = '1' then
-- reset state variables
send_who_has_r1 <= '0';
send_who_has_r2 <= '0';
send_I_have_r1 <= '0';
send_I_have_r2 <= '0';
else
-- normal (non reset) processing
send_who_has_r1 <= arp_nwk_req.req;
send_who_has_r2 <= send_who_has_r1;
 
send_I_have_r1 <= recv_who_has;
send_I_have_r2 <= send_I_have_r1;
end if;
end if;
end process;
 
 
end Behavioral;
 
/rtl/vhdl/arp_STORE_br.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
9,288 → 9,291
-- Target Devices:
-- Tool versions:
-- Description:
-- ARP storage table using block ram with lookup based on IP address
-- implements upto 255 entries with sequential search
-- uses round robin overwrite when full (LRU would be better, but ...)
--
-- store may take a number of cycles and the request is latched
-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup
-- ARP storage table using block ram with lookup based on IP address
-- implements upto 255 entries with sequential search
-- uses round robin overwrite when full (LRU would be better, but ...)
--
-- store may take a number of cycles and the request is latched
-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;
use work.arp_types.all;
 
entity arp_STORE_br is
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
Port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in STD_LOGIC
);
entity arp_STORE_br is
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end arp_STORE_br;
 
architecture Behavioral of arp_STORE_br is
 
type st_state_t is (IDLE,PAUSE,SEARCH,FOUND,NOT_FOUND);
type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
type count_mode_t is (RST,INCR,HOLD);
type mode_t is (MREAD,MWRITE);
 
-- state variables
signal ip_ram : ip_ram_t; -- will be implemented as block ram
signal mac_ram : mac_ram_t; -- will be implemented as block ram
signal st_state : st_state_t;
signal next_write_addr : addr_t; -- where to make the next write
signal num_entries : addr_t; -- number of entries in the store
signal next_read_addr : addr_t; -- next addr to read from
signal entry_found : arp_entry_t; -- entry found in search
signal mode : mode_t; -- are we writing or reading?
signal req_entry : arp_entry_t; -- entry latched from req
-- busses
signal next_st_state : st_state_t;
signal arp_entry_val : arp_entry_t;
signal mode_val : mode_t;
signal write_addr : addr_t; -- actual write address to use
-- control signals
signal set_st_state : std_logic;
signal set_next_write_addr : count_mode_t;
signal set_num_entries : count_mode_t;
signal set_next_read_addr : count_mode_t;
signal write_ram : std_logic;
signal set_entry_found : std_logic;
signal set_mode : std_logic;
 
function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
variable ret : arp_store_rslt_t;
begin
case status is
when IDLE =>
ret := status;
when others =>
if mode = MWRITE then
ret := BUSY;
else
ret := status;
end if;
end case;
return ret;
end read_status;
 
 
type st_state_t is (IDLE, PAUSE, SEARCH, FOUND, NOT_FOUND);
 
type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
 
type count_mode_t is (RST, INCR, HOLD);
 
type mode_t is (MREAD, MWRITE);
 
-- state variables
signal ip_ram : ip_ram_t; -- will be implemented as block ram
signal mac_ram : mac_ram_t; -- will be implemented as block ram
signal st_state : st_state_t;
signal next_write_addr : addr_t; -- where to make the next write
signal num_entries : addr_t; -- number of entries in the store
signal next_read_addr : addr_t; -- next addr to read from
signal entry_found : arp_entry_t; -- entry found in search
signal mode : mode_t; -- are we writing or reading?
signal req_entry : arp_entry_t; -- entry latched from req
 
-- busses
signal next_st_state : st_state_t;
signal arp_entry_val : arp_entry_t;
signal mode_val : mode_t;
signal write_addr : addr_t; -- actual write address to use
signal read_result_int : arp_store_result_t;
 
-- control signals
signal set_st_state : std_logic;
signal set_next_write_addr : count_mode_t;
signal set_num_entries : count_mode_t;
signal set_next_read_addr : count_mode_t;
signal write_ram : std_logic;
signal set_entry_found : std_logic;
signal set_mode : std_logic;
 
function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
variable ret : arp_store_rslt_t;
begin
case status is
when IDLE =>
ret := status;
when others =>
if mode = MWRITE then
ret := BUSY;
else
ret := status;
end if;
end case;
return ret;
end read_status;
 
begin
combinatorial : process (
-- input signals
read_req, write_req, clear_store, reset,
-- state variables
ip_ram, mac_ram, st_state, next_write_addr, num_entries,
next_read_addr, entry_found, mode, req_entry,
-- busses
next_st_state, arp_entry_val, mode_val, write_addr,
-- control signals
set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
write_ram, set_mode
)
begin
-- set output followers
read_result.status <= IDLE;
read_result.entry <= entry_found;
entry_count <= to_unsigned(num_entries,8);
-- set bus defaults
next_st_state <= IDLE;
mode_val <= MREAD;
write_addr <= next_write_addr;
-- set signal defaults
set_st_state <= '0';
set_next_write_addr <= HOLD;
set_num_entries <= HOLD;
set_next_read_addr <= HOLD;
write_ram <= '0';
set_entry_found <= '0';
set_mode <= '0';
-- STORE FSM
case st_state is
when IDLE =>
if write_req.req = '1' then
-- need to search to see if this IP already there
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MWRITE;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
elsif read_req.req = '1' then
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MREAD;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
end if;
 
when PAUSE =>
-- wait until read addr is latched and we get first data out of the ram
read_result.status <= read_status(BUSY,mode);
set_next_read_addr <= INCR;
next_st_state <= SEARCH;
set_st_state <= '1';
when SEARCH =>
read_result.status <= read_status(SEARCHING,mode);
-- check if have a match at this entry
if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
-- found it
set_entry_found <= '1';
next_st_state <= FOUND;
set_st_state <= '1';
elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
-- reached end of entry table
read_result.status <= read_status(NOT_FOUND,mode);
next_st_state <= NOT_FOUND;
set_st_state <= '1';
else
-- no match at this entry , go to next
set_next_read_addr <= INCR;
end if;
 
when FOUND =>
read_result.status <= read_status(FOUND,mode);
if mode = MWRITE then
write_addr <= next_read_addr - 1;
write_ram <= '1';
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
 
when NOT_FOUND =>
read_result.status <= read_status(NOT_FOUND,mode);
if mode = MWRITE then
-- need to write into the next free slot
write_addr <= next_write_addr;
write_ram <= '1';
set_next_write_addr <= INCR;
if num_entries < MAX_ARP_ENTRIES then
-- if not full, count another entry (if full, it just wraps)
set_num_entries <= INCR;
end if;
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
end case;
end process;
combinatorial : process (
-- input signals
read_req, write_req, clear_store, reset,
-- state variables
ip_ram, mac_ram, st_state, next_write_addr, num_entries,
next_read_addr, entry_found, mode, req_entry,
-- busses
next_st_state, arp_entry_val, mode_val, write_addr, read_result_int,
-- control signals
set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
write_ram, set_mode
)
begin
-- set output followers
read_result_int.status <= IDLE;
read_result_int.entry <= entry_found;
entry_count <= to_unsigned(num_entries, 8);
 
sequential : process (clk)
begin
if rising_edge(clk) then
-- ram processing
if write_ram = '1' then
ip_ram(write_addr) <= req_entry.ip;
mac_ram(write_addr) <= req_entry.mac;
end if;
if next_read_addr < MAX_ARP_ENTRIES then
arp_entry_val.ip <= ip_ram(next_read_addr);
arp_entry_val.mac <= mac_ram(next_read_addr);
else
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
end if;
if reset = '1' or clear_store = '1' then
-- reset state variables
st_state <= IDLE;
next_write_addr <= 0;
num_entries <= 0;
next_read_addr <= 0;
entry_found.ip <= (others => '0');
entry_found.mac <= (others => '0');
req_entry.ip <= (others => '0');
req_entry.mac <= (others => '0');
mode <= MREAD;
else
-- Next req_state processing
if set_st_state = '1' then
st_state <= next_st_state;
else
st_state <= st_state;
end if;
 
-- mode setting and write request latching
if set_mode = '1' then
mode <= mode_val;
if mode_val = MWRITE then
req_entry <= write_req.entry;
else
req_entry.ip <= read_req.ip;
req_entry.mac <= (others => '0');
end if;
else
mode <= mode;
req_entry <= req_entry;
end if;
-- latch entry found
if set_entry_found = '1' then
entry_found <= arp_entry_val;
else
entry_found <= entry_found;
end if;
 
-- next_write_addr counts and wraps
case set_next_write_addr is
when HOLD => next_write_addr <= next_write_addr;
when RST => next_write_addr <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
end case;
 
-- num_entries counts and holds at max
case set_num_entries is
when HOLD => num_entries <= num_entries;
when RST => num_entries <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
end case;
 
-- next_read_addr counts and wraps
case set_next_read_addr is
when HOLD => next_read_addr <= next_read_addr;
when RST => next_read_addr <= 0;
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
end case;
end if;
end if;
end process;
-- set bus defaults
next_st_state <= IDLE;
mode_val <= MREAD;
write_addr <= next_write_addr;
 
-- set signal defaults
set_st_state <= '0';
set_next_write_addr <= HOLD;
set_num_entries <= HOLD;
set_next_read_addr <= HOLD;
write_ram <= '0';
set_entry_found <= '0';
set_mode <= '0';
 
-- STORE FSM
case st_state is
when IDLE =>
if write_req.req = '1' then
-- need to search to see if this IP already there
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MWRITE;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
elsif read_req.req = '1' then
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MREAD;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
end if;
 
when PAUSE =>
-- wait until read addr is latched and we get first data out of the ram
read_result_int.status <= read_status(BUSY, mode);
set_next_read_addr <= INCR;
next_st_state <= SEARCH;
set_st_state <= '1';
when SEARCH =>
read_result_int.status <= read_status(SEARCHING, mode);
-- check if have a match at this entry
if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
-- found it
set_entry_found <= '1';
next_st_state <= FOUND;
set_st_state <= '1';
elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
-- reached end of entry table
read_result_int.status <= read_status(NOT_FOUND, mode);
next_st_state <= NOT_FOUND;
set_st_state <= '1';
else
-- no match at this entry , go to next
set_next_read_addr <= INCR;
end if;
 
when FOUND =>
read_result_int.status <= read_status(FOUND, mode);
if mode = MWRITE then
write_addr <= next_read_addr - 1;
write_ram <= '1';
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
 
when NOT_FOUND =>
read_result_int.status <= read_status(NOT_FOUND, mode);
if mode = MWRITE then
-- need to write into the next free slot
write_addr <= next_write_addr;
write_ram <= '1';
set_next_write_addr <= INCR;
if num_entries < MAX_ARP_ENTRIES then
-- if not full, count another entry (if full, it just wraps)
set_num_entries <= INCR;
end if;
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
end case;
end process;
 
sequential : process (clk)
begin
if rising_edge(clk) then
-- ram processing
if write_ram = '1' then
ip_ram(write_addr) <= req_entry.ip;
mac_ram(write_addr) <= req_entry.mac;
end if;
if next_read_addr < MAX_ARP_ENTRIES then
arp_entry_val.ip <= ip_ram(next_read_addr);
arp_entry_val.mac <= mac_ram(next_read_addr);
else
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
end if;
 
read_result <= read_result_int;
 
if reset = '1' or clear_store = '1' then
-- reset state variables
st_state <= IDLE;
next_write_addr <= 0;
num_entries <= 0;
next_read_addr <= 0;
entry_found.ip <= (others => '0');
entry_found.mac <= (others => '0');
req_entry.ip <= (others => '0');
req_entry.mac <= (others => '0');
mode <= MREAD;
 
else
-- Next req_state processing
if set_st_state = '1' then
st_state <= next_st_state;
else
st_state <= st_state;
end if;
 
-- mode setting and write request latching
if set_mode = '1' then
mode <= mode_val;
if mode_val = MWRITE then
req_entry <= write_req.entry;
else
req_entry.ip <= read_req.ip;
req_entry.mac <= (others => '0');
end if;
else
mode <= mode;
req_entry <= req_entry;
end if;
 
-- latch entry found
if set_entry_found = '1' then
entry_found <= arp_entry_val;
else
entry_found <= entry_found;
end if;
 
-- next_write_addr counts and wraps
case set_next_write_addr is
when HOLD => next_write_addr <= next_write_addr;
when RST => next_write_addr <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
end case;
 
-- num_entries counts and holds at max
case set_num_entries is
when HOLD => num_entries <= num_entries;
when RST => num_entries <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
end case;
 
-- next_read_addr counts and wraps
case set_next_read_addr is
when HOLD => next_read_addr <= next_read_addr;
when RST => next_read_addr <= 0;
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
end case;
end if;
end if;
end process;
 
end Behavioral;
/rtl/vhdl/arp_REQ.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
9,308 → 9,330
-- Target Devices:
-- Tool versions:
-- Description:
-- handle requests for ARP resolution
-- responds from single entry cache or searches external arp store, or asks to send a request
-- handle requests for ARP resolution
-- responds from single entry cache or searches external arp store, or asks to send a request
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created from arp.vhd 0.2
-- Revision 0.01 - File Created from arp.vhd 0.2
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
 
entity arp_req is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
clk : in std_logic;
reset : in STD_LOGIC
);
entity arp_req is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end arp_req;
 
architecture Behavioral of arp_req is
 
type req_state_t is (IDLE,LOOKUP,WAIT_REPLY,PAUSE1,PAUSE2,PAUSE3);
type set_cntr_t is (HOLD,CLR,INCR);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal req_state : req_state_t;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal arp_entry_cache : arp_entry_t; -- single entry cache for fast response
signal cache_valid : std_logic; -- single entry cache is valid
signal nwk_rx_cntr : unsigned(7 downto 0); -- counts nwk rx pkts that dont satisfy
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
 
-- busses
signal next_req_state : req_state_t;
signal arp_entry_val : arp_entry_t;
-- requester control signals
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal store_arp_cache : std_logic;
signal set_nwk_rx_cntr : set_cntr_t;
signal set_timer : set_cntr_t; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
signal clear_cache_valid : std_logic;
type req_state_t is (IDLE, LOOKUP, WAIT_REPLY, PAUSE1, PAUSE2, PAUSE3);
type set_cntr_t is (HOLD, CLR, INCR);
type set_clr_type is (SET, CLR, HOLD);
 
-- state variables
signal req_state : req_state_t;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal arp_entry_cache : arp_entry_t; -- single entry cache for fast response
signal cache_valid : std_logic; -- single entry cache is valid
signal nwk_rx_cntr : unsigned(7 downto 0); -- counts nwk rx pkts that dont satisfy
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
 
-- busses
signal next_req_state : req_state_t;
signal arp_entry_val : arp_entry_t;
 
-- requester control signals
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal store_arp_cache : std_logic;
signal set_nwk_rx_cntr : set_cntr_t;
signal set_timer : set_cntr_t; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
signal clear_cache_valid : std_logic;
 
signal l_arp_req_req_ip : std_logic_vector(31 downto 0); -- local network IP address for resolution
 
begin
req_combinatorial : process (
-- input signals
arp_req_req, arp_store_result, arp_nwk_result, clear_cache,
-- state variables
req_state, req_ip_addr, arp_entry_cache, cache_valid, nwk_rx_cntr,
freq_scaler, timer, timeout_reg,
-- busses
next_req_state, arp_entry_val,
-- control signals
set_req_state, set_req_ip, store_arp_cache, set_nwk_rx_cntr, clear_cache_valid,
set_timer, timer_enable, set_timeout
)
begin
-- set output followers
arp_req_rslt.got_mac <= '0'; -- set initial value of request result outputs
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
arp_store_req.req <= '0';
arp_store_req.ip <= (others => '0');
arp_nwk_req.req <= '0';
arp_nwk_req.ip <= (others => '0');
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry_cache.ip and cache_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
elsif arp_req_req.lookup_req = '1' then
-- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.got_mac <= '0';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
arp_req_rslt.got_mac <= cache_valid;
arp_req_rslt.mac <= arp_entry_cache.mac;
end if;
if arp_req_req.lookup_req = '1' then
-- ensure any existing error report is killed at the start of a request
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
store_arp_cache <= '0';
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
set_nwk_rx_cntr <= HOLD;
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
clear_cache_valid <= clear_cache;
 
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= CLR;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if arp_req_req.ip = arp_entry_cache.ip and cache_valid = '1' then
-- already have this IP - feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
clear_cache_valid <= '1'; -- remove cache entry
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
end if;
end if;
 
when LOOKUP =>
-- put request on the store
arp_store_req.ip <= req_ip_addr;
arp_store_req.req <= '1';
case arp_store_result.status is
when FOUND =>
-- update the cache
arp_entry_val <= arp_store_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_store_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
when NOT_FOUND =>
-- need to request from the network
set_timer <= CLR;
set_nwk_rx_cntr <= CLR;
arp_nwk_req.req <= '1';
arp_nwk_req.ip <= req_ip_addr;
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when OTHERS =>
-- just keep waiting - no timeout (assumes lookup with either succeed or fail)
end case;
when WAIT_REPLY =>
case arp_nwk_result.status is
when RECEIVED =>
-- store into cache
arp_entry_val <= arp_nwk_result.entry;
store_arp_cache <= '1';
-- and feed output back
if arp_nwk_result.entry.ip = req_ip_addr then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_nwk_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
else
if nwk_rx_cntr > ARP_MAX_PKT_TMO then
set_timeout <= SET;
next_req_state <= IDLE;
set_req_state <= '1';
else
set_nwk_rx_cntr <= INCR;
end if;
end if;
 
when ERROR =>
set_timeout <= SET;
 
when OTHERS =>
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
end case;
 
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
 
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
 
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
 
req_sequential : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
arp_entry_cache.ip <= (others => '0');
arp_entry_cache.mac <= (others => '0');
cache_valid <= '0';
nwk_rx_cntr <= (others => '0');
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
default_GW: if (not no_default_gateway) generate
default_gw_comb_p: process (arp_req_req.ip, nwk_gateway, nwk_mask) is
begin -- process default_gw_comb_p
-- translate IP addresses to local IP address if necessary
if ((nwk_mask and arp_req_req.ip) = (nwk_mask and nwk_gateway)) then
-- on local network
l_arp_req_req_ip <= arp_req_req.ip;
else
-- on remote network
l_arp_req_req_ip <= nwk_gateway;
end if;
end process default_gw_comb_p;
end generate default_GW;
no_default_GW: if (no_default_gateway) generate
no_default_gw_comb_p: process (arp_req_req.ip) is
begin -- process no_default_gw_comb_p
l_arp_req_req_ip <= arp_req_req.ip;
end process no_default_gw_comb_p;
end generate no_default_GW;
 
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= arp_req_req.ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- network received counter
case set_nwk_rx_cntr is
when CLR => nwk_rx_cntr <= (others => '0');
when INCR => nwk_rx_cntr <= nwk_rx_cntr + 1;
when HOLD => nwk_rx_cntr <= nwk_rx_cntr;
end case;
-- set the arp_entry_cache
if clear_cache_valid = '1' then
arp_entry_cache <= arp_entry_cache;
cache_valid <= '0';
elsif store_arp_cache = '1' then
arp_entry_cache <= arp_entry_val;
cache_valid <= '1';
else
arp_entry_cache <= arp_entry_cache;
cache_valid <= cache_valid;
end if;
 
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ,32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when CLR =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
req_combinatorial : process (
arp_entry_cache.ip, arp_entry_cache.mac, arp_nwk_result.entry, arp_nwk_result.entry.ip,
arp_nwk_result.entry.mac, arp_nwk_result.status, arp_req_req.lookup_req,
arp_store_result.entry, arp_store_result.entry.mac, arp_store_result.status, cache_valid,
clear_cache, freq_scaler, l_arp_req_req_ip, nwk_rx_cntr, req_ip_addr, req_state,
timeout_reg, timer)
begin
-- set output followers
arp_req_rslt.got_mac <= '0'; -- set initial value of request result outputs
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
arp_store_req.req <= '0';
arp_store_req.ip <= (others => '0');
arp_nwk_req.req <= '0';
arp_nwk_req.ip <= (others => '0');
 
end if;
end if;
end process;
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
elsif arp_req_req.lookup_req = '1' then
-- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.got_mac <= '0';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
arp_req_rslt.got_mac <= cache_valid;
arp_req_rslt.mac <= arp_entry_cache.mac;
end if;
 
if arp_req_req.lookup_req = '1' then
-- ensure any existing error report is killed at the start of a request
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
 
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
store_arp_cache <= '0';
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
set_nwk_rx_cntr <= HOLD;
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
clear_cache_valid <= clear_cache;
 
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
 
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= CLR;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
-- already have this IP - feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
clear_cache_valid <= '1'; -- remove cache entry
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
end if;
end if;
 
when LOOKUP =>
-- put request on the store
arp_store_req.ip <= req_ip_addr;
arp_store_req.req <= '1';
case arp_store_result.status is
when FOUND =>
-- update the cache
arp_entry_val <= arp_store_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_store_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
when NOT_FOUND =>
-- need to request from the network
set_timer <= CLR;
set_nwk_rx_cntr <= CLR;
arp_nwk_req.req <= '1';
arp_nwk_req.ip <= req_ip_addr;
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when others =>
-- just keep waiting - no timeout (assumes lookup with either succeed or fail)
end case;
when WAIT_REPLY =>
case arp_nwk_result.status is
when RECEIVED =>
if arp_nwk_result.entry.ip = req_ip_addr then
-- store into cache
arp_entry_val <= arp_nwk_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_nwk_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
else
if nwk_rx_cntr > ARP_MAX_PKT_TMO then
set_timeout <= SET;
next_req_state <= IDLE;
set_req_state <= '1';
else
set_nwk_rx_cntr <= INCR;
end if;
end if;
 
when error =>
set_timeout <= SET;
 
when others =>
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
end case;
 
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
 
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
 
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
 
req_sequential : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
arp_entry_cache.ip <= (others => '0');
arp_entry_cache.mac <= (others => '0');
cache_valid <= '0';
nwk_rx_cntr <= (others => '0');
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
 
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= l_arp_req_req_ip;
else
req_ip_addr <= req_ip_addr;
end if;
 
-- network received counter
case set_nwk_rx_cntr is
when CLR => nwk_rx_cntr <= (others => '0');
when INCR => nwk_rx_cntr <= nwk_rx_cntr + 1;
when HOLD => nwk_rx_cntr <= nwk_rx_cntr;
end case;
 
-- set the arp_entry_cache
if clear_cache_valid = '1' then
arp_entry_cache <= arp_entry_cache;
cache_valid <= '0';
elsif store_arp_cache = '1' then
arp_entry_cache <= arp_entry_val;
cache_valid <= '1';
else
arp_entry_cache <= arp_entry_cache;
cache_valid <= cache_valid;
end if;
 
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
else
freq_scaler <= freq_scaler - 1;
end if;
 
-- timer processing
case set_timer is
when CLR =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
 
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
 
end if;
end if;
end process;
 
end Behavioral;
/rtl/vhdl/arpv2.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
9,303 → 9,313
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in 1-deep cache and arp store
-- request cache fill through ARP protocol if required
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- structural decomposition includes
-- arp TX block - encoding of ARP protocol
-- arp RX block - decoding of ARP protocol
-- arp REQ block - sequencing requests for resolution
-- arp STORE block - storing address resolution entries (indexed by IP addr)
-- arp sync block - sync between master RX clock and TX clock domains
-- handle simple IP lookup in 1-deep cache and arp store
-- request cache fill through ARP protocol if required
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- structural decomposition includes
-- arp TX block - encoding of ARP protocol
-- arp RX block - decoding of ARP protocol
-- arp REQ block - sequencing requests for resolution
-- arp STORE block - storing address resolution entries (indexed by IP addr)
-- arp sync block - sync between master RX clock and TX clock domains
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
 
entity arpv2 is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
control : in arp_control_type;
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received
);
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- though a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
nwk_gateway : in std_logic_vector (31 downto 0) := (others => '0'); -- IP address of default gateway
nwk_mask : in std_logic_vector (31 downto 0) := (others => '0'); -- Net mask
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end arpv2;
 
architecture structural of arpv2 is
 
COMPONENT arp_req
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
Port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
clk : in std_logic;
reset : in STD_LOGIC
);
END COMPONENT;
 
COMPONENT arp_tx
PORT(
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in STD_LOGIC_VECTOR (31 downto 0); -- ip target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0);
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
END COMPONENT;
 
COMPONENT arp_rx
PORT(
-- MAC layer RX signals
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
rx_clk : in std_logic;
reset : in STD_LOGIC
);
END COMPONENT;
 
 
COMPONENT arp_store_br
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
Port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in STD_LOGIC
);
END COMPONENT;
 
COMPONENT arp_sync
Port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out STD_LOGIC_VECTOR (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
END COMPONENT;
 
-- interconnect REQ -> ARP_TX
signal arp_nwk_req_int : arp_nwk_request_t; -- tx req from REQ
 
signal send_I_have_int : std_logic;
signal arp_entry_int : arp_entry_t;
signal send_who_has_int : std_logic;
signal ip_entry_int : STD_LOGIC_VECTOR (31 downto 0);
-- interconnect REQ <-> ARP_STORE
signal arp_store_req_int : arp_store_rdrequest_t; -- lookup request
signal arp_store_result_int: arp_store_result_t; -- lookup result
 
-- interconnect ARP_RX -> REQ
signal nwk_result_status_int : arp_nwk_rslt_t; -- response from a TX req
 
-- interconnect ARP_RX -> ARP_STORE
signal recv_I_have_int : std_logic; -- path to store new arp entry
signal arp_entry_for_I_have_int: arp_entry_t;
 
-- interconnect ARP_RX -> ARP_TX
signal recv_who_has_int : std_logic; -- path for reply when we can anser
signal arp_entry_for_who_has_int : arp_entry_t; -- target for who_has msg (ie, who to reply to)
 
begin
 
 
req : arp_req
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO
)
PORT MAP (
-- lookup request signals
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- external arp store signals
arp_store_req => arp_store_req_int,
arp_store_result => arp_store_result_int,
-- network request signals
arp_nwk_req => arp_nwk_req_int,
arp_nwk_result.status => nwk_result_status_int,
arp_nwk_result.entry => arp_entry_for_I_have_int,
-- system signals
clear_cache => control.clear_cache,
clk => data_in_clk,
reset => reset
);
 
sync : arp_sync PORT MAP (
-- REQ to TX
arp_nwk_req => arp_nwk_req_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- RX to TX
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
-- RX to REQ
I_have_received => recv_I_have_int,
nwk_result_status => nwk_result_status_int,
-- system
rx_clk => data_in_clk,
tx_clk => data_out_clk,
reset => reset
);
 
tx : arp_tx PORT MAP (
-- control signals
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- MAC layer TX signals
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system signals
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
tx_clk => data_out_clk,
reset => reset
);
 
rx : arp_rx PORT MAP (
-- MAC layer RX signals
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- ARP output signals
recv_who_has => recv_who_has_int,
arp_entry_for_who_has=> arp_entry_for_who_has_int,
recv_I_have => recv_I_have_int,
arp_entry_for_I_have=> arp_entry_for_I_have_int,
-- control and status signals
req_count => req_count,
-- system signals
our_ip_address => our_ip_address,
rx_clk => data_in_clk,
reset => reset
);
 
store : arp_store_br
generic map (
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
PORT MAP (
-- read signals
read_req => arp_store_req_int,
read_result => arp_store_result_int,
-- write signals
write_req.req => recv_I_have_int,
write_req.entry => arp_entry_for_I_have_int,
-- control and status signals
clear_store => control.clear_cache,
entry_count => open,
-- system signals
clk => data_in_clk,
reset => reset
);
 
component arp_req
generic (
no_default_gateway : boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end component;
 
component arp_tx
port(
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- ip target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end component;
 
component arp_rx
port(
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end component;
 
 
component arp_store_br
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end component;
 
component arp_sync
port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out std_logic_vector (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end component;
 
 
-- interconnect REQ -> ARP_TX
signal arp_nwk_req_int : arp_nwk_request_t; -- tx req from REQ
 
signal send_I_have_int : std_logic;
signal arp_entry_int : arp_entry_t;
signal send_who_has_int : std_logic;
signal ip_entry_int : std_logic_vector (31 downto 0);
 
-- interconnect REQ <-> ARP_STORE
signal arp_store_req_int : arp_store_rdrequest_t; -- lookup request
signal arp_store_result_int : arp_store_result_t; -- lookup result
 
-- interconnect ARP_RX -> REQ
signal nwk_result_status_int : arp_nwk_rslt_t; -- response from a TX req
 
-- interconnect ARP_RX -> ARP_STORE
signal recv_I_have_int : std_logic; -- path to store new arp entry
signal arp_entry_for_I_have_int : arp_entry_t;
 
-- interconnect ARP_RX -> ARP_TX
signal recv_who_has_int : std_logic; -- path for reply when we can anser
signal arp_entry_for_who_has_int : arp_entry_t; -- target for who_has msg (ie, who to reply to)
 
begin
 
 
req : arp_req
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO
)
port map (
-- lookup request signals
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- external arp store signals
arp_store_req => arp_store_req_int,
arp_store_result => arp_store_result_int,
-- network request signals
arp_nwk_req => arp_nwk_req_int,
arp_nwk_result.status => nwk_result_status_int,
arp_nwk_result.entry => arp_entry_for_I_have_int,
-- system signals
clear_cache => control.clear_cache,
nwk_gateway => nwk_gateway,
nwk_mask => nwk_mask,
clk => data_in_clk,
reset => reset
);
 
sync : arp_sync port map (
-- REQ to TX
arp_nwk_req => arp_nwk_req_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- RX to TX
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
-- RX to REQ
I_have_received => recv_I_have_int,
nwk_result_status => nwk_result_status_int,
-- system
rx_clk => data_in_clk,
tx_clk => data_out_clk,
reset => reset
);
 
tx : arp_tx port map (
-- control signals
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- MAC layer TX signals
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system signals
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
tx_clk => data_out_clk,
reset => reset
);
 
rx : arp_rx port map (
-- MAC layer RX signals
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- ARP output signals
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
recv_I_have => recv_I_have_int,
arp_entry_for_I_have => arp_entry_for_I_have_int,
-- control and status signals
req_count => req_count,
-- system signals
our_ip_address => our_ip_address,
rx_clk => data_in_clk,
reset => reset
);
 
store : arp_store_br
generic map (
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map (
-- read signals
read_req => arp_store_req_int,
read_result => arp_store_result_int,
-- write signals
write_req.req => recv_I_have_int,
write_req.entry => arp_entry_for_I_have_int,
-- control and status signals
clear_store => control.clear_cache,
entry_count => open,
-- system signals
clk => data_in_clk,
reset => reset
);
 
 
end structural;
 
/rtl/vhdl/arp_RX.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
9,364 → 9,365
-- Target Devices:
-- Tool versions:
-- Description:
-- handle receipt of arp pkt
-- ignores other types of pkt
--
-- When it receives an ARP pkt that is either addressed to our IP or is a global request,
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along
-- with associated mac or arp entry data.
--
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup
-- on the expectation that we will want to reply to this host.
-- handle receipt of arp pkt
-- ignores other types of pkt
--
-- When it receives an ARP pkt that is either addressed to our IP or is a global request,
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along
-- with associated mac or arp entry data.
--
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup
-- on the expectation that we will want to reply to this host.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored from arp v0.02 module
-- Revision 0.01 - File Created - refactored from arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
 
entity arp_rx is
Port (
-- MAC layer RX signals
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
data_in_last : in STD_LOGIC; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
rx_clk : in std_logic;
reset : in STD_LOGIC
);
port (
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end arp_rx;
 
 
 
architecture Behavioral of arp_rx is
 
type rx_state_t is (IDLE,PARSE,PROCESS_ARP,WAIT_END);
type rx_event_t is (NO_EVENT,DATA);
type count_mode_t is (RST,INCR,HOLD);
type arp_oper_t is (NOP,REQUEST,REPLY);
type rx_state_t is (IDLE, PARSE, PROCESS_ARP, WAIT_END);
type rx_event_t is (NO_EVENT, DATA);
type count_mode_t is (RST, INCR, HOLD);
type arp_oper_t is (NOP, REQUEST, REPLY);
 
type tx_state_type is (IDLE,WAIT_MAC,SEND);
-- state variables
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal rx_state : rx_state_t;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_t;
signal arp_req_count : unsigned (7 downto 0);
signal new_arp_entry : arp_entry_t;
 
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
 
-- rx control signals
signal next_rx_state : rx_state_t;
signal set_rx_state : std_logic;
signal rx_event : rx_event_t;
signal rx_count_mode : count_mode_t;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_t;
signal dataval : std_logic_vector (7 downto 0);
signal count_arp_rcvd : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
type tx_state_type is (IDLE, WAIT_MAC, SEND);
 
-- state variables
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
 
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : STD_LOGIC_VECTOR; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
signal rx_state : rx_state_t;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_t;
signal arp_req_count : unsigned (7 downto 0);
signal new_arp_entry : arp_entry_t;
 
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
 
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
 
 
-- rx control signals
signal next_rx_state : rx_state_t;
signal set_rx_state : std_logic;
signal rx_event : rx_event_t;
signal rx_count_mode : count_mode_t;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_t;
signal dataval : std_logic_vector (7 downto 0);
signal count_arp_rcvd : std_logic;
 
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
 
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
 
 
 
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : std_logic_vector; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
 
begin
 
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval,set_mac5,set_mac4,set_mac3,set_mac2,set_mac1,set_mac0,set_ip3,set_ip2,set_ip1,set_ip0, set_err_data,
count_arp_rcvd
)
begin
-- set output followers
req_count <= STD_LOGIC_VECTOR(arp_req_count);
-- set defaults for combinatorial outputs
recv_who_has <= '0';
arp_entry_for_who_has.ip <= (others => '0');
arp_entry_for_who_has.mac <= (others => '0');
recv_I_have <= '0';
arp_entry_for_I_have.ip <= (others => '0');
arp_entry_for_I_have.mac <= (others => '0');
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
count_arp_rcvd <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval, set_mac5, set_mac4, set_mac3, set_mac2, set_mac1, set_mac0, set_ip3, set_ip2, set_ip1, set_ip0, set_err_data,
count_arp_rcvd
)
begin
-- set output followers
req_count <= std_logic_vector(arp_req_count);
 
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 42 then
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in,rx_count,our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
end if;
end case;
-- set defaults for combinatorial outputs
recv_who_has <= '0';
arp_entry_for_who_has.ip <= (others => '0');
arp_entry_for_who_has.mac <= (others => '0');
recv_I_have <= '0';
arp_entry_for_I_have.ip <= (others => '0');
arp_entry_for_I_have.mac <= (others => '0');
 
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
count_arp_rcvd <= '1';
recv_who_has <= '1';
arp_entry_for_who_has <= new_arp_entry;
-- setting I_Have as well allows us to cache the remote node's entry immediately
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
when REPLY =>
count_arp_rcvd <= '1';
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
end case;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
count_arp_rcvd <= '0';
set_err_data <= '0';
 
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
 
rx_sequential : process (rx_clk)
begin
if rising_edge(rx_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
 
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if count_arp_rcvd = '1' then
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
else
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
--else
end if;
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 41 then -- TB 2013-01-14 15:09:45 was 42
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in, rx_count, our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
-- end if;
end case;
 
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
count_arp_rcvd <= '1';
recv_who_has <= '1';
arp_entry_for_who_has <= new_arp_entry;
-- setting I_Have as well allows us to cache the remote node's entry immediately
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
when REPLY =>
count_arp_rcvd <= '1';
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
end case;
 
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
 
rx_sequential : process (rx_clk)
begin
if rising_edge(rx_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
 
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
 
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
 
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
 
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
 
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
 
-- set arp entry request
if count_arp_rcvd = '1' then
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
else
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
 
end Behavioral;
 
/rtl/vhdl/IPv4_RX.vhd
1,507 → 1,533
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX
-- doesnt handle reassembly
-- checks and filters for IP protocol
-- checks and filters for IP addr
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Revision 0.03 - Added handling of broadcast address
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
entity IPv4_RX is
Port (
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC -- indicates last data in frame
);
end IPv4_RX;
 
architecture Behavioral of IPv4_RX is
 
type rx_state_type is (IDLE, ETH_HDR, IP_HDR, USER_DATA, WAIT_END, ERR);
type rx_event_type is (NO_EVENT,DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX
-- doesnt handle reassembly
-- checks and filters for IP protocol
-- checks and filters for IP addr
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Improved error handling
-- Revision 0.03 - Added handling of broadcast address
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_ip : std_logic_vector (31 downto 0); -- src IP captured from input
signal dst_ip : std_logic_vector (23 downto 0); -- 1st 3 bytes of dst IP captured from input
signal is_broadcast_reg : std_logic;
signal protocol : std_logic_vector (7 downto 0); -- src protocol captured from input
signal data_len : std_logic_vector (15 downto 0); -- src data length captured from input
signal ip_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal frame_err_cnt : unsigned (7 downto 0); -- number of frame errors
signal error_code_reg : std_logic_vector (3 downto 0);
signal rx_pkt_counter : unsigned (7 downto 0); -- number of rx frames received for us
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal set_dst_ip3 : std_logic;
signal set_dst_ip2 : std_logic;
signal set_dst_ip1 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
signal set_protocol : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_ip_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal set_frame_err_cnt: count_mode_type;
signal dataval : std_logic_vector (7 downto 0);
signal rx_count_val : unsigned (15 downto 0);
signal set_error_code : std_logic;
signal error_code_val : std_logic_vector (3 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_data_last : std_logic;
signal dst_ip_rx : std_logic_vector (31 downto 0);
signal set_is_broadcast : set_clr_type;
 
 
entity IPv4_RX is
port (
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
rx_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in std_logic; -- indicates data_in valid on clock
mac_data_in_last : in std_logic -- indicates last data in frame
);
end IPv4_RX;
 
architecture Behavioral of IPv4_RX is
 
type rx_state_type is (IDLE, ETH_HDR, IP_HDR, USER_DATA, WAIT_END, ERR);
 
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
 
 
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal src_ip : std_logic_vector (31 downto 0); -- src IP captured from input
signal dst_ip : std_logic_vector (23 downto 0); -- 1st 3 bytes of dst IP captured from input
signal is_broadcast_reg : std_logic;
signal protocol : std_logic_vector (7 downto 0); -- src protocol captured from input
signal data_len : std_logic_vector (15 downto 0); -- src data length captured from input
signal ip_rx_start_reg : std_logic; -- indicates start of user data
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
signal frame_err_cnt : unsigned (7 downto 0); -- number of frame errors
signal error_code_reg : std_logic_vector (3 downto 0);
signal rx_pkt_counter : unsigned (7 downto 0); -- number of rx frames received for us
 
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal set_dst_ip3 : std_logic;
signal set_dst_ip2 : std_logic;
signal set_dst_ip1 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
signal set_protocol : std_logic;
signal set_len_H : std_logic;
signal set_len_L : std_logic;
signal set_ip_rx_start : set_clr_type;
signal set_hdr_valid : set_clr_type;
signal set_frame_err_cnt : count_mode_type;
signal dataval : std_logic_vector (7 downto 0);
signal rx_count_val : unsigned (15 downto 0);
signal set_error_code : std_logic;
signal error_code_val : std_logic_vector (3 downto 0);
signal set_pkt_cnt : count_mode_type;
signal set_data_last : std_logic;
signal dst_ip_rx : std_logic_vector (31 downto 0);
signal set_is_broadcast : set_clr_type;
 
 
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
 
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
 
rx_combinatorial : process (
-- input signals
mac_data_in, mac_data_in_valid, mac_data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, src_ip, dst_ip, protocol, data_len, ip_rx_start_reg, hdr_valid_reg,
frame_err_cnt, error_code_reg, rx_pkt_counter, is_broadcast_reg,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode,
set_ip3, set_ip2, set_ip1, set_ip0, set_protocol, set_len_H, set_len_L,
set_dst_ip3, set_dst_ip2, set_dst_ip1,
set_ip_rx_start, set_hdr_valid, set_frame_err_cnt, dataval, rx_count_val,
set_error_code, error_code_val, set_pkt_cnt, set_data_last, dst_ip_rx, set_is_broadcast
)
begin
-- set output followers
ip_rx_start <= ip_rx_start_reg;
ip_rx.hdr.is_valid <= hdr_valid_reg;
ip_rx.hdr.protocol <= protocol;
ip_rx.hdr.data_length <= data_len;
ip_rx.hdr.src_ip_addr <= src_ip;
ip_rx.hdr.num_frame_errors <= std_logic_vector(frame_err_cnt);
ip_rx.hdr.last_error_code <= error_code_reg;
ip_rx.hdr.is_broadcast <= is_broadcast_reg;
rx_pkt_count <= STD_LOGIC_VECTOR(rx_pkt_counter);
-- transfer data upstream if in user data phase
if rx_state = USER_DATA then
ip_rx.data.data_in <= mac_data_in;
ip_rx.data.data_in_valid <= mac_data_in_valid;
ip_rx.data.data_in_last <= set_data_last;
else
ip_rx.data.data_in <= (others => '0');
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
end if;
begin
 
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
set_dst_ip3 <= '0';
set_dst_ip2 <= '0';
set_dst_ip1 <= '0';
set_protocol <= '0';
set_len_H <= '0';
set_len_L <= '0';
set_ip_rx_start <= HOLD;
set_hdr_valid <= HOLD;
set_frame_err_cnt <= HOLD;
rx_count_val <= x"0000";
set_error_code <= '0';
error_code_val <= RX_EC_NONE;
set_pkt_cnt <= HOLD;
dataval <= (others => '0');
set_data_last <= '0';
dst_ip_rx <= (others => '0');
set_is_broadcast <= HOLD;
-- determine event (if any)
if mac_data_in_valid = '1' then
rx_event <= DATA;
dataval <= mac_data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
set_hdr_valid <= CLR;
next_rx_state <= ETH_HDR;
set_rx_state <= '1';
end case;
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
 
when ETH_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"000d" then
rx_count_mode <= RST;
next_rx_state <= IP_HDR;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_ETH;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
set_rx_state <= '1';
else
case rx_count is
when x"000c" =>
if mac_data_in /= x"08" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"000d" =>
if mac_data_in /= x"00" then -- ignore pkts that are not type=IP
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when others => -- ignore other bytes in eth header
end case;
end if;
end case;
 
when IP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0013" then
rx_count_val <= x"0001"; -- start counter at 1
rx_count_mode <= SET_VAL;
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_IP;
set_error_code <= '1';
set_frame_err_cnt <= INCR;
set_ip_rx_start <= CLR;
set_data_last <= '1';
next_rx_state <= IDLE;
set_rx_state <= '1';
else
case rx_count is
when x"0000" =>
if mac_data_in /= x"45" then -- ignore pkts that are not v4 with 5 header words
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0002" => set_len_H <= '1';
when x"0003" => set_len_L <= '1';
 
when x"0006" =>
if (mac_data_in(7) = '1') or (mac_data_in (4 downto 0) /= "00000") then
-- ignore pkts that require reassembly (MF=1 or frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when x"0007" =>
if mac_data_in /= x"00" then -- ignore pkts that require reassembly (frag offst /= 0)
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
 
when x"0009" => set_protocol <= '1';
 
when x"000c" => set_ip3 <= '1';
when x"000d" => set_ip2 <= '1';
when x"000e" => set_ip1 <= '1';
when x"000f" => set_ip0 <= '1';
 
when x"0010" => set_dst_ip3 <= '1';
when x"0011" => set_dst_ip2 <= '1';
when x"0012" => set_dst_ip1 <= '1';
when x"0013" =>
-- now have the dst IP addr
dst_ip_rx <= dst_ip & mac_data_in;
if dst_ip_rx = IP_BC_ADDR then
set_is_broadcast <= SET;
else
set_is_broadcast <= CLR;
end if;
set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
if dst_ip_rx = our_ip_address or dst_ip_rx = IP_BC_ADDR then
next_rx_state <= USER_DATA;
set_pkt_cnt <= INCR; -- count another pkt received
set_rx_state <= '1';
set_ip_rx_start <= SET;
else
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
when others => -- ignore other bytes in ip header
end case;
end if;
end case;
when USER_DATA =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data gets transfered upstream as part of "output followers" processing
if rx_count = unsigned(data_len) then
set_ip_rx_start <= CLR;
rx_count_mode <= RST;
set_data_last <= '1';
if mac_data_in_last = '1' then
next_rx_state <= IDLE;
set_ip_rx_start <= CLR;
else
next_rx_state <= WAIT_END;
end if;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
-- check for early frame termination
if mac_data_in_last = '1' then
error_code_val <= RX_EC_ET_USER;