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/udp_ip_stack/trunk/bench/vhdl/arpv2_tb.vhd
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-------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 12:35:50 05/31/2011 |
-- Design Name: |
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/arp1/arp_tb.vhd |
-- Project Name: arp1 |
-- Target Device: |
-- Tool versions: |
-- Description: |
-- |
-- VHDL Test Bench Created by ISE for module: arp |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 0.02 - Added tests for ARP timeout |
-- Additional Comments: |
-- |
-- Notes: |
-- This testbench has been automatically generated using types std_logic and |
-- std_logic_vector for the ports of the unit under test. Xilinx recommends |
-- that these types always be used for the top-level I/O of a design in order |
-- to guarantee that the testbench will bind correctly to the post-implementation |
-- simulation model. |
-------------------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
use work.arp_types.all; |
|
ENTITY arpv2_tb IS |
END arpv2_tb; |
|
ARCHITECTURE behavior OF arpv2_tb IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT arpv2 |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store |
); |
Port ( |
-- lookup request signals |
arp_req_req : in arp_req_req_type; |
arp_req_rslt : out arp_req_rslt_type; |
-- MAC layer RX signals |
data_in_clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock |
data_in_last : in STD_LOGIC; -- indicates last data in frame |
-- MAC layer TX signals |
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx) |
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted |
data_out_clk : in std_logic; |
data_out_ready : in std_logic; -- indicates system ready to consume data |
data_out_valid : out std_logic; -- indicates data out is valid |
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame |
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame |
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
-- system signals |
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
control : in arp_control_type; |
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received |
); |
END COMPONENT; |
|
|
--Inputs |
signal clk : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal data_in : std_logic_vector(7 downto 0) := (others => '0'); |
signal data_in_valid : std_logic := '0'; |
signal data_in_last : std_logic := '0'; |
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0'); |
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0'); |
signal data_out_ready : std_logic; |
signal data_out_valid : std_logic; |
signal data_out_first : std_logic; |
signal data_out_last : std_logic; |
signal data_out : std_logic_vector (7 downto 0); |
signal req_count : STD_LOGIC_VECTOR(7 downto 0); |
signal arp_req_req : arp_req_req_type; |
signal arp_req_rslt : arp_req_rslt_type; |
signal mac_tx_req : std_logic; |
signal mac_tx_granted : std_logic; |
signal control : arp_control_type; |
|
|
-- Clock period definitions |
constant clk_period : time := 8 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: arpv2 |
generic map ( |
CLOCK_FREQ => 10, -- artificially low count to enable pragmatic testing |
ARP_TIMEOUT => 20 |
) |
PORT MAP ( |
-- lookup request mappings |
arp_req_req => arp_req_req, |
arp_req_rslt => arp_req_rslt, |
-- rx mappings |
data_in_clk => clk, |
reset => reset, |
data_in => data_in, |
data_in_valid => data_in_valid, |
data_in_last => data_in_last, |
-- tx mappings |
mac_tx_req => mac_tx_req, |
mac_tx_granted => mac_tx_granted, |
data_out_clk => clk, |
data_out_ready => data_out_ready, |
data_out_valid => data_out_valid, |
data_out_first => data_out_first, |
data_out_last => data_out_last, |
data_out => data_out, |
-- system mappings |
our_mac_address => our_mac_address, |
our_ip_address => our_ip_address, |
control => control, |
req_count => req_count |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
-- hold reset state for 100 ns. |
wait for 100 ns; |
|
our_ip_address <= x"c0a80509"; -- 192.168.5.9 |
our_mac_address <= x"002320212223"; |
mac_tx_granted <= '1'; -- FIXME 0 |
control.clear_cache <= '0'; |
|
reset <= '1'; |
wait for clk_period*10; |
reset <= '0'; |
wait for clk_period*5; |
|
assert mac_tx_req = '0' report "mac_tx_req asserted on reset"; |
|
-- insert stimulus here |
arp_req_req.lookup_req <= '0'; |
arp_req_req.ip <= (others => '0'); |
data_out_ready <= '1'; |
|
report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1"; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"18"; wait for clk_period; |
data_in <= x"29"; wait for clk_period; |
data_in <= x"26"; wait for clk_period; |
data_in <= x"7c"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Sender MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"18"; wait for clk_period; |
data_in <= x"29"; wait for clk_period; |
data_in <= x"26"; wait for clk_period; |
data_in <= x"7c"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
|
report "T1: Expect that we send an 'I have 192.168.5.9' msg"; |
|
-- check tx arbitration signals |
|
report "T1: waiting for tx req"; |
wait until mac_tx_req = '1'; |
|
-- ready to tx |
data_out_ready <= '1'; |
mac_tx_granted <= '1'; |
report "T1: waiting for data_out_valid"; |
wait until data_out_valid = '1'; |
report "T1: got data_out_valid"; |
wait for clk_period*10; |
data_out_ready <= '0'; |
wait for clk_period*2; |
data_out_ready <= '1'; |
wait for clk_period*12; |
assert data_out = x"02" report "T1: expected opcode = 02 for reply 'I have'"; |
-- expect our mac 00 23 20 21 22 23 |
wait for clk_period; |
assert data_out = x"00" report "T1: incorrect our mac.0"; |
wait for clk_period; |
assert data_out = x"23" report "T1: incorrect our mac.1"; |
wait for clk_period; |
assert data_out = x"20" report "T1: incorrect our mac.2"; |
wait for clk_period; |
assert data_out = x"21" report "T1: incorrect our mac.3"; |
wait for clk_period; |
assert data_out = x"22" report "T1: incorrect our mac.4"; |
wait for clk_period; |
assert data_out = x"23" report "T1: incorrect our mac.5"; |
-- expect our IP c0 a8 05 05 |
wait for clk_period; |
assert data_out = x"c0" report "T1: incorrect our IP.0"; |
wait for clk_period; |
assert data_out = x"a8" report "T1: incorrect our IP.1"; |
wait for clk_period; |
assert data_out = x"05" report "T1: incorrect our IP.2"; |
wait for clk_period; |
assert data_out = x"09" report "T1: incorrect our IP.3"; |
|
-- expect target mac 00 23 18 29 26 7c |
wait for clk_period; |
assert data_out = x"00" report "T1: incorrect target mac.0"; |
wait for clk_period; |
assert data_out = x"23" report "T1: incorrect target mac.1"; |
wait for clk_period; |
assert data_out = x"18" report "T1: incorrect target mac.2"; |
wait for clk_period; |
assert data_out = x"29" report "T1: incorrect target mac.3"; |
wait for clk_period; |
assert data_out = x"26" report "T1: incorrect target mac.4"; |
wait for clk_period; |
assert data_out = x"7c" report "T1: incorrect target mac.5"; |
-- expect target IP c0 a8 05 01 |
wait for clk_period; |
assert data_out = x"c0" report "T1: incorrect target IP.0"; |
wait for clk_period; |
assert data_out = x"a8" report "T1: incorrect target IP.1"; |
wait for clk_period; |
assert data_out = x"05" report "T1: incorrect target IP.2"; |
assert data_out_last = '0' report "T1: data out last incorrectly set on target IP.2 byte"; |
wait for clk_period; |
assert data_out = x"01" report "T1: incorrect target IP.3"; |
assert data_out_last = '1' report "T1: data out last should be set"; |
|
wait for clk_period*10; |
|
report "T2: Send another ARP request: who has 192.168.5.8? Tell 192.168.5.1, holding off transmitter"; |
data_out_ready <= '0'; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"18"; wait for clk_period; |
data_in <= x"29"; wait for clk_period; |
data_in <= x"26"; wait for clk_period; |
data_in <= x"7c"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Sender MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"18"; wait for clk_period; |
data_in <= x"29"; wait for clk_period; |
data_in <= x"26"; wait for clk_period; |
data_in <= x"7c"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
|
-- ready to tx |
wait for clk_period*10; |
data_out_ready <= '1'; |
|
wait for clk_period*50; |
|
report "T3: Send a request for the IP that is already in the store"; |
arp_req_req.ip <= x"c0a80501"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
report "T3: wait for reply from store"; |
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1'; |
assert arp_req_rslt.got_mac = '1' report "T3: expected got mac"; |
assert arp_req_rslt.got_err = '0' report "T3: expected got err = 0"; |
assert arp_req_rslt.mac = x"00231829267c" report "T3: wrong mac value"; |
wait for clk_period*2; |
|
-- the entry that was in the store should now be in the cache - check it |
report "T4: Send a request for the IP that is already in the cache"; |
arp_req_req.ip <= x"c0a80501"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
assert arp_req_rslt.got_mac = '1' report "T4: expected got mac"; |
assert arp_req_rslt.got_err = '0' report "T4: expected got err = 0"; |
assert arp_req_rslt.mac = x"00231829267c" report "T4: wrong mac value"; |
|
wait for clk_period*50; |
|
report "T5 - Send a request for the IP that is not cached or in the store"; |
arp_req_req.ip <= x"c0a80503"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
report "T5: waiting for data_out_valid"; |
wait until data_out_valid = '1'; |
report "T5: got data_out_valid"; |
wait for clk_period*10; |
data_out_ready <= '0'; |
wait for clk_period*2; |
data_out_ready <= '1'; |
wait for clk_period*12; |
assert data_out = x"01" report "T5: expected opcode = 01 for request 'who has'"; |
-- expect our mac 00 23 20 21 22 23 |
wait for clk_period; |
assert data_out = x"00" report "T5: incorrect our mac.0"; |
wait for clk_period; |
assert data_out = x"23" report "T5: incorrect our mac.1"; |
wait for clk_period; |
assert data_out = x"20" report "T5: incorrect our mac.2"; |
wait for clk_period; |
assert data_out = x"21" report "T5: incorrect our mac.3"; |
wait for clk_period; |
assert data_out = x"22" report "T5: incorrect our mac.4"; |
wait for clk_period; |
assert data_out = x"23" report "T5: incorrect our mac.5"; |
-- expect our IP c0 a8 05 05 |
wait for clk_period; |
assert data_out = x"c0" report "T5: incorrect our IP.0"; |
wait for clk_period; |
assert data_out = x"a8" report "T5: incorrect our IP.1"; |
wait for clk_period; |
assert data_out = x"05" report "T5: incorrect our IP.2"; |
wait for clk_period; |
assert data_out = x"09" report "T5: incorrect our IP.3"; |
|
-- expect empty target mac |
wait for clk_period; |
assert data_out = x"00" report "T5: incorrect target mac.0"; |
wait for clk_period; |
assert data_out = x"00" report "T5: incorrect target mac.1"; |
wait for clk_period; |
assert data_out = x"00" report "T5: incorrect target mac.2"; |
wait for clk_period; |
assert data_out = x"00" report "T5: incorrect target mac.3"; |
wait for clk_period; |
assert data_out = x"00" report "T5: incorrect target mac.4"; |
wait for clk_period; |
assert data_out = x"00" report "T5: incorrect target mac.5"; |
-- expect target IP c0 a8 05 01 |
wait for clk_period; |
assert data_out = x"c0" report "T5: incorrect target IP.0"; |
wait for clk_period; |
assert data_out = x"a8" report "T5: incorrect target IP.1"; |
wait for clk_period; |
assert data_out = x"05" report "T5: incorrect target IP.2"; |
assert data_out_last = '0' report "T5: data out last incorrectly set on target IP.2 byte"; |
wait for clk_period; |
assert data_out = x"03" report "T5: incorrect target IP.3"; |
assert data_out_last = '1' report "T5: data out last should be set"; |
|
wait for clk_period*10; |
|
-- Send the reply |
data_out_ready <= '1'; |
|
report "T5.2: Send an ARP reply: 192.168.5.3 has mac 02:12:03:23:04:54"; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"12"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"02"; wait for clk_period; |
-- Sender MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"12"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"20"; wait for clk_period; |
data_in <= x"21"; wait for clk_period; |
data_in <= x"22"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T5.2: expected got mac"; |
assert arp_req_rslt.got_err = '0' report "T5.2: expected got err = 0"; |
assert arp_req_rslt.mac = x"021203230454" report "T5.2: wrong mac value"; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
wait for clk_period*4; |
|
report "T6: check that both these IPs remain in the store"; |
arp_req_req.ip <= x"c0a80501"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
wait for clk_period; |
report "T6.1: wait for reply from store"; |
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1'; |
assert arp_req_rslt.got_mac = '1' report "T6.1: expected got mac"; |
assert arp_req_rslt.got_err = '0' report "T6.1: expected got err = 0"; |
assert arp_req_rslt.mac = x"00231829267c" report "T6.1: wrong mac value"; |
wait for clk_period*2; |
|
arp_req_req.ip <= x"c0a80503"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
wait for clk_period; |
report "T6.2: wait for reply from store"; |
wait until arp_req_rslt.got_mac = '1' or arp_req_rslt.got_err = '1'; |
assert arp_req_rslt.got_mac = '1' report "T6.2: expected got mac"; |
assert arp_req_rslt.got_err = '0' report "T6.2: expected got err = 0"; |
assert arp_req_rslt.mac = x"021203230454" report "T6.2: wrong mac value"; |
wait for clk_period*2; |
|
report "T7 - test that receipt of wrong I Have does not satisfy a current req"; |
arp_req_req.ip <= x"c0a8050e"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
report "T7: waiting for data_out_valid"; |
wait until data_out_valid = '1'; |
report "T7: got data_out_valid"; |
wait for clk_period*10; |
data_out_ready <= '0'; |
wait for clk_period*2; |
data_out_ready <= '1'; |
wait for clk_period*12; |
assert data_out = x"01" report "T7: expected opcode = 01 for request 'who has'"; |
-- expect our mac 00 23 20 21 22 23 |
wait for clk_period; |
assert data_out = x"00" report "T7: incorrect our mac.0"; |
wait for clk_period; |
assert data_out = x"23" report "T7: incorrect our mac.1"; |
wait for clk_period; |
assert data_out = x"20" report "T7: incorrect our mac.2"; |
wait for clk_period; |
assert data_out = x"21" report "T7: incorrect our mac.3"; |
wait for clk_period; |
assert data_out = x"22" report "T7: incorrect our mac.4"; |
wait for clk_period; |
assert data_out = x"23" report "T7: incorrect our mac.5"; |
-- expect our IP c0 a8 05 05 |
wait for clk_period; |
assert data_out = x"c0" report "T7: incorrect our IP.0"; |
wait for clk_period; |
assert data_out = x"a8" report "T7: incorrect our IP.1"; |
wait for clk_period; |
assert data_out = x"05" report "T7: incorrect our IP.2"; |
wait for clk_period; |
assert data_out = x"09" report "T7: incorrect our IP.3"; |
|
-- expect empty target mac |
wait for clk_period; |
assert data_out = x"00" report "T7: incorrect target mac.0"; |
wait for clk_period; |
assert data_out = x"00" report "T7: incorrect target mac.1"; |
wait for clk_period; |
assert data_out = x"00" report "T7: incorrect target mac.2"; |
wait for clk_period; |
assert data_out = x"00" report "T7: incorrect target mac.3"; |
wait for clk_period; |
assert data_out = x"00" report "T7: incorrect target mac.4"; |
wait for clk_period; |
assert data_out = x"00" report "T7: incorrect target mac.5"; |
-- expect target IP c0 a8 05 0e |
wait for clk_period; |
assert data_out = x"c0" report "T7: incorrect target IP.0"; |
wait for clk_period; |
assert data_out = x"a8" report "T7: incorrect target IP.1"; |
wait for clk_period; |
assert data_out = x"05" report "T7: incorrect target IP.2"; |
assert data_out_last = '0' report "T7: data out last incorrectly set on target IP.2 byte"; |
wait for clk_period; |
assert data_out = x"0e" report "T7: incorrect target IP.3"; |
assert data_out_last = '1' report "T7: data out last should be set"; |
|
wait for clk_period*10; |
|
-- Send the reply |
data_out_ready <= '1'; |
|
report "T7.2: Send an arbitrary unwanted ARP reply: 192.168.7.3 has mac 57:12:34:19:23:9a"; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"57"; wait for clk_period; |
data_in <= x"12"; wait for clk_period; |
data_in <= x"34"; wait for clk_period; |
data_in <= x"19"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"9a"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"02"; wait for clk_period; |
-- Sender MAC |
data_in <= x"57"; wait for clk_period; |
data_in <= x"12"; wait for clk_period; |
data_in <= x"34"; wait for clk_period; |
data_in <= x"19"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"9a"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"07"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"20"; wait for clk_period; |
data_in <= x"21"; wait for clk_period; |
data_in <= x"22"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
assert arp_req_rslt.got_mac = '0' report "T7.2: expected got mac = 0"; |
assert arp_req_rslt.got_err = '0' report "T7.2: expected got err = 0"; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
wait for clk_period*4; |
|
-- Send the reply |
data_out_ready <= '1'; |
|
report "T7.3: Send a wanted ARP reply: 192.168.5.e has mac 76:34:98:55:aa:37"; |
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"76"; wait for clk_period; |
data_in <= x"34"; wait for clk_period; |
data_in <= x"98"; wait for clk_period; |
data_in <= x"55"; wait for clk_period; |
data_in <= x"aa"; wait for clk_period; |
data_in <= x"37"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"02"; wait for clk_period; |
-- Sender MAC |
data_in <= x"76"; wait for clk_period; |
data_in <= x"34"; wait for clk_period; |
data_in <= x"98"; wait for clk_period; |
data_in <= x"55"; wait for clk_period; |
data_in <= x"aa"; wait for clk_period; |
data_in <= x"37"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"0e"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"20"; wait for clk_period; |
data_in <= x"21"; wait for clk_period; |
data_in <= x"22"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T7.3: expected got mac"; |
assert arp_req_rslt.got_err = '0' report "T7.3: expected got err = 0"; |
assert arp_req_rslt.mac = x"76349855aa37" report "T7.3: wrong mac value"; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
wait for clk_period*4; |
|
|
report "T8: Request 192.168.5.4 (not cached), dont send a reply and wait for timeout"; |
arp_req_req.ip <= x"c0a80504"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
assert mac_tx_req = '1' report "T8: should be requesting TX channel"; |
wait for clk_period*220; |
assert arp_req_rslt.got_mac = '0' report "T8: should not have got mac"; |
assert arp_req_rslt.got_err = '1' report "T8: should have got err"; |
|
report "T9: Request 192.168.5.7 (not cached= and Send an ARP reply: 192.168.5.7 has mac 02:15:03:23:04:54"; |
arp_req_req.ip <= x"c0a80507"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '0' report "T9: should not yet have mac"; |
assert arp_req_rslt.got_err = '0' report "T9: should not have got err"; |
|
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
assert mac_tx_req = '1' report "T9: should be requesting TX channel"; |
wait for clk_period*50; |
-- Send the reply |
data_out_ready <= '1'; |
|
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"02"; wait for clk_period; |
-- Sender MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"07"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"20"; wait for clk_period; |
data_in <= x"21"; wait for clk_period; |
data_in <= x"22"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T9: should have got mac"; |
assert arp_req_rslt.mac = x"021503230454" report "T9: incorrect mac"; |
assert arp_req_rslt.got_err = '0' report "T9: should not have got err"; |
wait for clk_period*10; |
|
report "T10: Request 192.168.5.7 again an expect it to be in the cache"; |
arp_req_req.ip <= x"c0a80507"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T10: should have mac"; |
assert arp_req_rslt.got_err = '0' report "T10: should not have got err"; |
|
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
|
report "T11: Clear the cache, Request 192.168.5.7 again an expect a 'who has' to be sent"; |
control.clear_cache <= '1'; |
wait for clk_period; |
control.clear_cache <= '0'; |
wait for clk_period; |
|
arp_req_req.ip <= x"c0a80507"; |
arp_req_req.lookup_req <= '1'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '0' report "T11: should not yet have mac"; |
assert arp_req_rslt.got_err = '0' report "T11: should not have got err"; |
|
arp_req_req.lookup_req <= '0'; |
wait for clk_period*20; |
|
|
assert mac_tx_req = '1' report "T11: should be requesting TX channel"; |
wait for clk_period*50; |
-- Send the reply |
data_out_ready <= '1'; |
|
data_in_valid <= '1'; |
-- dst MAC (bc) |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
data_in <= x"ff"; wait for clk_period; |
-- src MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"04"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"06"; wait for clk_period; |
-- HW type |
data_in <= x"00"; wait for clk_period; |
data_in <= x"01"; wait for clk_period; |
-- Protocol type |
data_in <= x"08"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
-- HW size |
data_in <= x"06"; wait for clk_period; |
-- protocol size |
data_in <= x"04"; wait for clk_period; |
-- Opcode |
data_in <= x"00"; wait for clk_period; |
data_in <= x"02"; wait for clk_period; |
-- Sender MAC |
data_in <= x"02"; wait for clk_period; |
data_in <= x"15"; wait for clk_period; |
data_in <= x"03"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"55"; wait for clk_period; |
data_in <= x"54"; wait for clk_period; |
-- Sender IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"07"; wait for clk_period; |
-- Target MAC |
data_in <= x"00"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
data_in <= x"20"; wait for clk_period; |
data_in <= x"21"; wait for clk_period; |
data_in <= x"22"; wait for clk_period; |
data_in <= x"23"; wait for clk_period; |
-- Target IP |
data_in <= x"c0"; wait for clk_period; |
data_in <= x"a8"; wait for clk_period; |
data_in <= x"05"; wait for clk_period; |
data_in <= x"09"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '1'; |
data_in <= x"00"; wait for clk_period; |
data_in_last <= '0'; |
data_in_valid <= '0'; |
wait for clk_period; |
assert arp_req_rslt.got_mac = '1' report "T11: should have got mac"; |
assert arp_req_rslt.mac = x"021503235554" report "T11: incorrect mac"; |
assert arp_req_rslt.got_err = '0' report "T11: should not have got err"; |
wait for clk_period*10; |
|
report "--- end of tests ---"; |
wait; |
end process; |
|
END; |
/udp_ip_stack/trunk/bench/vhdl/IP_complete_nomac_tb.vhd
282,11 → 282,11
|
ip_tx_start <= '0'; wait for clk_period; |
|
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING"; |
assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING"; |
|
wait for clk_period*2; |
|
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early"; |
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early"; |
|
-- need to wait for ARP tx to complete |
|
376,7 → 376,7
ip_tx.data.data_out_last <= '1'; |
wait for clk_period; |
|
assert mac_tx_tlast = '1' report "T1: mac_tx_tlast not set on last byte"; |
assert mac_tx_tlast = '1' report "T2: mac_tx_tlast not set on last byte"; |
|
wait for clk_period; |
|
384,10 → 384,52
ip_tx.data.data_out_last <= '0'; |
wait for clk_period*2; |
|
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be SENT"; |
wait for clk_period*2; |
assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be SENT"; |
wait for clk_period*10; |
|
------------ |
-- TEST 3 -- Check that sending to the same IP addr doesnt cause an ARP req as the addr is cached |
------------ |
|
report "T3: Send 2nd IP TX to same IP addr - should not need to do ARP tx/rx"; |
ip_tx.hdr.protocol <= x"35"; |
ip_tx.hdr.data_length <= x"0006"; |
ip_tx.hdr.dst_ip_addr <= x"c0123478"; |
ip_tx.data.data_out_valid <= '0'; |
ip_tx.data.data_out_last <= '0'; |
wait for clk_period; |
ip_tx_start <= '1'; wait for clk_period; |
ip_tx_start <= '0'; wait for clk_period; |
assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING"; |
wait for clk_period*2; |
assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early"; |
wait until ip_tx_data_out_ready = '1'; |
|
-- start to tx IP data |
ip_tx.data.data_out_valid <= '1'; |
ip_tx.data.data_out <= x"81"; wait for clk_period; |
ip_tx.data.data_out <= x"83"; wait for clk_period; |
ip_tx.data.data_out <= x"85"; wait for clk_period; |
ip_tx.data.data_out <= x"87"; wait for clk_period; |
ip_tx.data.data_out <= x"89"; wait for clk_period; |
|
ip_tx.data.data_out <= x"8b"; |
ip_tx.data.data_out_last <= '1'; |
wait for clk_period; |
|
assert mac_tx_tlast = '1' report "T3: mac_tx_tlast not set on last byte"; |
|
wait for clk_period; |
|
ip_tx.data.data_out_valid <= '0'; |
ip_tx.data.data_out_last <= '0'; |
wait for clk_period*2; |
|
assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be SENT"; |
wait for clk_period*2; |
|
|
|
report "-- end of tests --"; |
|
wait; |
/udp_ip_stack/trunk/bench/vhdl/arp_STORE_tb.vhd
0,0 → 1,384
-------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 07:38:43 02/13/2012 |
-- Design Name: |
-- Module Name: arp_STORE_tb.vhd |
-- Project Name: udp3 |
-- Target Device: |
-- Tool versions: |
-- Description: |
-- |
-- VHDL Test Bench Created by ISE for module: arp_STORE_br |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
-- Notes: |
-- This testbench has been automatically generated using types std_logic and |
-- std_logic_vector for the ports of the unit under test. Xilinx recommends |
-- that these types always be used for the top-level I/O of a design in order |
-- to guarantee that the testbench will bind correctly to the post-implementation |
-- simulation model. |
-------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use ieee.std_logic_unsigned.all; |
use work.arp_types.all; |
|
ENTITY arp_STORE_tb IS |
END arp_STORE_tb; |
|
ARCHITECTURE behavior OF arp_STORE_tb IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT arp_STORE_br |
generic ( |
MAX_ARP_ENTRIES : integer := 256 -- max entries in the store |
); |
PORT( |
-- read signals |
read_req : in arp_store_rdrequest_t; -- requesting a '1' or store |
read_result : out arp_store_result_t; -- the result |
-- write signals |
write_req : in arp_store_wrrequest_t; -- requesting a '1' or store |
-- control and status signals |
clear_store : in std_logic; -- erase all entries |
entry_count : out unsigned(7 downto 0); -- how many entries currently in store |
-- system signals |
clk : in std_logic; |
reset : in STD_LOGIC |
); |
END COMPONENT; |
|
|
--Inputs |
signal read_req : arp_store_rdrequest_t; |
signal write_req : arp_store_wrrequest_t; |
signal clear_store : std_logic := '0'; |
signal clk : std_logic := '0'; |
signal reset : std_logic := '0'; |
|
--Outputs |
signal read_result : arp_store_result_t; |
signal entry_count : unsigned(7 downto 0); -- how many entries currently in store |
|
-- Clock period definitions |
constant clk_period : time := 8 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: arp_STORE_br |
generic map ( |
MAX_ARP_ENTRIES => 4 |
) |
PORT MAP ( |
read_req => read_req, |
read_result => read_result, |
write_req => write_req, |
clear_store => clear_store, |
entry_count => entry_count, |
clk => clk, |
reset => reset |
); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
read_req.req <= '0'; |
read_req.ip <= (others => '0'); |
write_req.req <= '0'; |
write_req.entry.ip <= (others => '0'); |
write_req.entry.mac <= (others => '0'); |
reset <= '1'; |
-- hold reset state |
wait for clk_period*10; |
reset <= '0'; |
|
-- insert stimulus here |
report "T1 - look for something when store is empty"; |
read_req.ip <= x"12345678"; |
read_req.req <= '1'; |
wait for clk_period*4; |
assert read_result.status = NOT_FOUND report "T1: expected NOT_FOUND"; |
wait for clk_period; |
read_req.req <= '0'; |
wait for clk_period; |
assert read_result.status = IDLE report "T1: expected IDLE"; |
assert entry_count = x"00" report "T1: wrong entry count"; |
|
report "T2 - insert first entry into store"; |
write_req.entry.ip <= x"12345678"; |
write_req.entry.mac <= x"002398127645"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
assert entry_count = x"01" report "T2: wrong entry count"; |
|
report "T3 - check if can find this single entry"; |
read_req.ip <= x"12345678"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T3: expected FOUND"; |
assert read_result.entry.ip = x"12345678" report "T3: wrong ip addr"; |
assert read_result.entry.mac = x"002398127645" report "T3: wrong mac addr"; |
wait for clk_period; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T3: expected IDLE"; |
|
report "T4 - check unable to find missing entry with one entry in store"; |
read_req.ip <= x"12345679"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = NOT_FOUND report "T4: expected NOT_FOUND"; |
wait for clk_period; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T4: expected IDLE"; |
|
report "T5 - insert 2nd entry into store and check can find both entries"; |
write_req.entry.ip <= x"12345679"; |
write_req.entry.mac <= x"101202303404"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
assert entry_count = x"02" report "T4: wrong entry count"; |
read_req.ip <= x"12345678"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T5.1: expected FOUND"; |
assert read_result.entry.ip = x"12345678" report "T5.1: wrong ip addr"; |
assert read_result.entry.mac = x"002398127645" report "T5.1: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T5.1: expected IDLE"; |
read_req.ip <= x"12345679"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T5.2: expected FOUND"; |
assert read_result.entry.ip = x"12345679" report "T5.2: wrong ip addr"; |
assert read_result.entry.mac = x"101202303404" report "T5.2: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T5.2: expected IDLE"; |
|
report "T6 - insert 2 more entries so that the store is full. check can find all"; |
write_req.entry.ip <= x"1234567a"; |
write_req.entry.mac <= x"10120230340a"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
write_req.entry.ip <= x"1234567b"; |
write_req.entry.mac <= x"10120230340b"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
assert entry_count = x"04" report "T6: wrong entry count"; |
read_req.ip <= x"12345678"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T6.1: expected FOUND"; |
assert read_result.entry.ip = x"12345678" report "T6.1: wrong ip addr"; |
assert read_result.entry.mac = x"002398127645" report "T6.1: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T6.1: expected IDLE"; |
read_req.ip <= x"12345679"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T6.2: expected FOUND"; |
assert read_result.entry.ip = x"12345679" report "T6.2: wrong ip addr"; |
assert read_result.entry.mac = x"101202303404" report "T6.2: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T6.2: expected IDLE"; |
read_req.ip <= x"1234567a"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T6.3: expected FOUND"; |
assert read_result.entry.ip = x"1234567a" report "T6.3: wrong ip addr"; |
assert read_result.entry.mac = x"10120230340a" report "T6.3: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T6.3: expected IDLE"; |
read_req.ip <= x"1234567b"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T6.4: expected FOUND"; |
assert read_result.entry.ip = x"1234567b" report "T6.4: wrong ip addr"; |
assert read_result.entry.mac = x"10120230340b" report "T6.4: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T6.4: expected IDLE"; |
|
report "T7 - with store full, check that we dont find missing item"; |
read_req.ip <= x"1233367b"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = NOT_FOUND report "T7: expected NOT_FOUND"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T7: expected IDLE"; |
|
report "T8 - insert additional entry into store - will erase one of the others"; |
write_req.entry.ip <= x"12345699"; |
write_req.entry.mac <= x"992398127699"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
assert entry_count = x"04" report "T8: wrong entry count"; |
read_req.ip <= x"12345699"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T8: expected FOUND"; |
assert read_result.entry.ip = x"12345699" report "T8: wrong ip addr"; |
assert read_result.entry.mac = x"992398127699" report "T8: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T8: expected IDLE"; |
|
report "T9 - clear the store and ensure cant find something that was there"; |
clear_store <= '1'; |
wait for clk_period; |
clear_store <= '0'; |
wait for clk_period; |
assert entry_count = x"00" report "T9: wrong entry count"; |
read_req.ip <= x"12345699"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = NOT_FOUND report "T9: expected NOT_FOUND"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T9: expected IDLE"; |
|
report "T10 - refill the store with three entries"; |
write_req.entry.ip <= x"12345675"; |
write_req.entry.mac <= x"10120230340a"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
write_req.entry.ip <= x"12345676"; |
write_req.entry.mac <= x"10120230340b"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
write_req.entry.ip <= x"12345677"; |
write_req.entry.mac <= x"10120230340c"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
assert entry_count = x"03" report "T10: wrong entry count"; |
|
report "T11 - check middle entry, then change it and check again"; |
read_req.ip <= x"12345676"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T11.1: expected FOUND"; |
assert read_result.entry.ip = x"12345676" report "T11.1: wrong ip addr"; |
assert read_result.entry.mac = x"10120230340b" report "T11.1: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T11.1: expected IDLE"; |
write_req.entry.ip <= x"12345676"; |
write_req.entry.mac <= x"10120990340b"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait for clk_period; |
assert entry_count = x"03" report "T11: wrong entry count"; |
read_req.ip <= x"12345676"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T11.2: expected FOUND"; |
assert read_result.entry.ip = x"12345676" report "T11.2: wrong ip addr"; |
assert read_result.entry.mac = x"10120990340b" report "T11.2: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T11.2: expected IDLE"; |
|
report "T12 - check 2nd write at beginning"; |
-- clear store, write 1st entry, overwrite the entry, and check |
clear_store <= '1'; |
wait for clk_period; |
clear_store <= '0'; |
wait for clk_period; |
assert entry_count = x"00" report "T12.1: wrong entry count"; |
write_req.entry.ip <= x"12345678"; |
write_req.entry.mac <= x"002398127645"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
assert entry_count = x"01" report "T12.2: wrong entry count"; |
write_req.entry.ip <= x"12345678"; |
write_req.entry.mac <= x"002398127647"; |
write_req.req <= '1'; |
wait for clk_period; |
write_req.req <= '0'; |
wait until read_result.status = IDLE; |
wait for clk_period; |
assert entry_count = x"01" report "T12.3: wrong entry count"; |
read_req.ip <= x"12345678"; |
read_req.req <= '1'; |
wait until read_result.status = FOUND or read_result.status = NOT_FOUND; |
wait for clk_period; |
assert read_result.status = FOUND report "T12.4: expected FOUND"; |
assert read_result.entry.ip = x"12345678" report "T12.4: wrong ip addr"; |
assert read_result.entry.mac = x"002398127647" report "T12.4: wrong mac addr"; |
read_req.req <= '0'; |
wait for clk_period*2; |
assert read_result.status = IDLE report "T12.5: expected IDLE"; |
|
report "--- end of tests ---"; |
wait; |
end process; |
|
END; |
/udp_ip_stack/trunk/rtl/vhdl/UDP_TX.vhd
15,6 → 15,7
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 0.02 - Added abort of tx when receive last from upstream |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
215,6 → 216,7
if udp_txi.data.data_out_valid = '1' or tx_count = x"000" then |
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast |
if unsigned(tx_count) = unsigned(udp_txi.hdr.data_length) then |
-- TX terminated due to count - end normally |
set_last <= '1'; |
tx_data <= udp_txi.data.data_out; |
next_tx_result <= UDPTX_RESULT_SENT; |
222,7 → 224,17
set_tx_result <= '1'; |
next_tx_state <= IDLE; |
set_tx_state <= '1'; |
elsif udp_txi.data.data_out_last = '1' then |
-- terminate tx with error as got last from upstream before exhausting count |
set_last <= '1'; |
tx_data <= udp_txi.data.data_out; |
next_tx_result <= UDPTX_RESULT_ERR; |
set_ip_tx_start <= CLR; |
set_tx_result <= '1'; |
next_tx_state <= IDLE; |
set_tx_state <= '1'; |
else |
-- TX continues |
tx_count_mode <= INCR; |
tx_data <= udp_txi.data.data_out; |
end if; |
/udp_ip_stack/trunk/rtl/vhdl/arp_types.vhd
5,7 → 5,8
-- constants, and functions |
-- |
-- To use any of the example code shown below, uncomment the lines and modify as necessary |
-- |
-- |
-- Revision 0.02 - Added type definitions (store and network) for arpv2 |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
12,12 → 13,15
|
package arp_types is |
|
|
-- arp lookup types |
|
type arp_req_req_type is |
record |
lookup_req : std_logic; -- set high when wanting mac adr for the requested IP |
ip : std_logic_vector (31 downto 0); |
end record; |
|
|
type arp_req_rslt_type is |
record |
got_mac : std_logic; -- indicates that we got the mac |
24,10 → 28,54
mac : std_logic_vector (47 downto 0); |
got_err : std_logic; -- indicates that we got an error (prob a timeout) |
end record; |
|
type arp_entry_t is record |
ip : std_logic_vector (31 downto 0); |
mac : std_logic_vector (47 downto 0); |
end record; |
|
type arp_control_type is |
record |
clear_cache : std_logic; |
end record; |
|
type arp_control_type is |
record |
clear_cache : std_logic; |
end record; |
|
-- arp store types |
|
type arp_store_rslt_t is (IDLE,BUSY,SEARCHING,FOUND,NOT_FOUND); |
|
type arp_store_rdrequest_t is |
record |
req : std_logic; -- request to lookup |
ip : std_logic_vector(31 downto 0); -- contains ip to lookup |
end record; |
|
type arp_store_wrrequest_t is |
record |
req : std_logic; -- request to store |
entry : arp_entry_t; -- ip,mac to store |
end record; |
|
type arp_store_result_t is |
record |
status : arp_store_rslt_t; -- status of the request |
entry : arp_entry_t; -- contains ip,mac if found |
end record; |
|
-- arp network types |
|
type arp_nwk_rslt_t is (IDLE,REQUESTING,RECEIVED,ERROR); |
|
type arp_nwk_request_t is |
record |
req : std_logic; -- request to resolve IP addr |
ip : std_logic_vector(31 downto 0); -- IP to request |
end record; |
|
type arp_nwk_result_t is |
record |
status : arp_nwk_rslt_t; -- status of request |
entry : arp_entry_t; -- the result |
end record; |
|
|
end arp_types; |
/udp_ip_stack/trunk/rtl/vhdl/IP_complete_nomac.vhd
25,11 → 25,15
use work.axi.all; |
use work.ipv4_types.all; |
use work.arp_types.all; |
use work.arp; |
use work.arpv2; |
|
entity IP_complete_nomac is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- IP Layer signals |
63,6 → 67,7
); |
end IP_complete_nomac; |
|
|
architecture structural of IP_complete_nomac is |
|
COMPONENT IPv4 |
103,7 → 108,9
COMPONENT arp |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl) |
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl) |
); |
Port ( |
-- lookup request signals |
158,6 → 165,20
); |
END COMPONENT; |
|
|
------------------- |
-- Configuration |
-- |
-- Enable one of the following to specify which |
-- implementation of the ARP layer to use |
------------------- |
|
|
-- for arp_layer : arp use entity work.arp; -- single slot arbitrator |
for arp_layer : arp use entity work.arpv2; -- multislot arbitrator |
|
|
|
--------------------------- |
-- Signals |
--------------------------- |
238,7 → 259,9
arp_layer : arp |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
Port map( |
-- request signals |
297,3 → 320,5
|
end structural; |
|
|
|
/udp_ip_stack/trunk/rtl/vhdl/arp_SYNC.vhd
0,0 → 1,163
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 14:09:01 02/20/2012 |
-- Design Name: |
-- Module Name: arp_SYNC - Behavioral - synchronises between rx and tx clock domains |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.arp_types.all; |
|
entity arp_SYNC is |
Port ( |
-- REQ to TX |
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC |
send_who_has : out std_logic; |
ip_entry : out STD_LOGIC_VECTOR (31 downto 0); |
-- RX to TX |
recv_who_has : in std_logic; -- this is for us, we will respond |
arp_entry_for_who_has : in arp_entry_t; |
send_I_have : out std_logic; |
arp_entry : out arp_entry_t; |
-- RX to REQ |
I_have_received : in std_logic; |
nwk_result_status : out arp_nwk_rslt_t; |
-- System Signals |
rx_clk : in std_logic; |
tx_clk : in std_logic; |
reset : in std_logic |
); |
end arp_SYNC; |
|
architecture Behavioral of arp_SYNC is |
|
type sync_state_t is (IDLE,HOLD1, HOLD2); |
|
-- state registers |
signal ip_entry_state : sync_state_t; |
signal arp_entry_state : sync_state_t; |
signal ip_entry_reg : STD_LOGIC_VECTOR (31 downto 0); |
signal arp_entry_reg : arp_entry_t; |
|
-- synchronisation registers |
signal send_who_has_r1 : std_logic; |
signal send_who_has_r2 : std_logic; |
signal send_I_have_r1 : std_logic; |
signal send_I_have_r2 : std_logic; |
|
begin |
|
combinatorial : process ( |
-- input signals |
arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset, |
-- state |
ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg, |
-- synchronisation registers |
send_who_has_r1, send_who_has_r2, |
send_I_have_r1, send_I_have_r2 |
) |
begin |
-- set output followers |
send_who_has <= send_who_has_r2; |
ip_entry <= ip_entry_reg; |
send_I_have <= send_I_have_r2; |
arp_entry <= arp_entry_reg; |
|
-- combinaltorial outputs |
if I_have_received = '1' then |
nwk_result_status <= RECEIVED; |
else |
nwk_result_status <= IDLE; |
end if; |
end process; |
|
-- process for stablisising RX clock domain data registers |
-- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles |
-- during transfer to TX clk domain |
rx_sequential : process (tx_clk) |
begin |
if rising_edge(tx_clk) then |
if reset = '1' then |
-- reset state variables |
ip_entry_reg <= (others => '0'); |
arp_entry_reg.ip <= (others => '0'); |
arp_entry_reg.mac <= (others => '0'); |
else |
-- normal (non reset) processing |
case ip_entry_state is |
when IDLE => |
if arp_nwk_req.req = '1' then |
ip_entry_reg <= arp_nwk_req.ip; |
ip_entry_state <= HOLD1; |
else |
ip_entry_reg <= ip_entry_reg; |
ip_entry_state <= IDLE; |
end if; |
when HOLD1 => |
ip_entry_reg <= ip_entry_reg; |
ip_entry_state <= HOLD2; |
when HOLD2 => |
ip_entry_reg <= ip_entry_reg; |
ip_entry_state <= IDLE; |
end case; |
|
case arp_entry_state is |
when IDLE => |
if recv_who_has = '1' then |
arp_entry_reg <= arp_entry_for_who_has; |
arp_entry_state <= HOLD1; |
else |
arp_entry_reg <= arp_entry_reg; |
arp_entry_state <= IDLE; |
end if; |
when HOLD1 => |
arp_entry_reg <= arp_entry_reg; |
arp_entry_state <= HOLD2; |
when HOLD2 => |
arp_entry_reg <= arp_entry_reg; |
arp_entry_state <= IDLE; |
end case; |
end if; |
end if; |
end process; |
|
-- process for syncing to the TX clock domain |
-- clocks control signals through 2 layers of tx clocking |
tx_sequential : process (tx_clk) |
begin |
if rising_edge(tx_clk) then |
if reset = '1' then |
-- reset state variables |
send_who_has_r1 <= '0'; |
send_who_has_r2 <= '0'; |
send_I_have_r1 <= '0'; |
send_I_have_r2 <= '0'; |
else |
-- normal (non reset) processing |
|
send_who_has_r1 <= arp_nwk_req.req; |
send_who_has_r2 <= send_who_has_r1; |
|
send_I_have_r1 <= recv_who_has; |
send_I_have_r2 <= send_I_have_r1; |
end if; |
end if; |
end process; |
|
|
end Behavioral; |
|
/udp_ip_stack/trunk/rtl/vhdl/arp_STORE_br.vhd
0,0 → 1,296
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Peter Fall |
-- |
-- Create Date: 12:00:04 05/31/2011 |
-- Design Name: |
-- Module Name: arp_STORE_br - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- ARP storage table using block ram with lookup based on IP address |
-- implements upto 255 entries with sequential search |
-- uses round robin overwrite when full (LRU would be better, but ...) |
-- |
-- store may take a number of cycles and the request is latched |
-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use ieee.std_logic_unsigned.all; |
use work.arp_types.all; |
|
entity arp_STORE_br is |
generic ( |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store |
); |
Port ( |
-- read signals |
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store |
read_result : out arp_store_result_t; -- the result |
-- write signals |
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store |
-- control and status signals |
clear_store : in std_logic; -- erase all entries |
entry_count : out unsigned(7 downto 0); -- how many entries currently in store |
-- system signals |
clk : in std_logic; |
reset : in STD_LOGIC |
); |
end arp_STORE_br; |
|
architecture Behavioral of arp_STORE_br is |
|
type st_state_t is (IDLE,PAUSE,SEARCH,FOUND,NOT_FOUND); |
|
type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0); |
type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0); |
subtype addr_t is integer range 0 to MAX_ARP_ENTRIES; |
|
type count_mode_t is (RST,INCR,HOLD); |
|
type mode_t is (MREAD,MWRITE); |
|
-- state variables |
signal ip_ram : ip_ram_t; -- will be implemented as block ram |
signal mac_ram : mac_ram_t; -- will be implemented as block ram |
signal st_state : st_state_t; |
signal next_write_addr : addr_t; -- where to make the next write |
signal num_entries : addr_t; -- number of entries in the store |
signal next_read_addr : addr_t; -- next addr to read from |
signal entry_found : arp_entry_t; -- entry found in search |
signal mode : mode_t; -- are we writing or reading? |
signal req_entry : arp_entry_t; -- entry latched from req |
|
-- busses |
signal next_st_state : st_state_t; |
signal arp_entry_val : arp_entry_t; |
signal mode_val : mode_t; |
signal write_addr : addr_t; -- actual write address to use |
|
-- control signals |
signal set_st_state : std_logic; |
signal set_next_write_addr : count_mode_t; |
signal set_num_entries : count_mode_t; |
signal set_next_read_addr : count_mode_t; |
signal write_ram : std_logic; |
signal set_entry_found : std_logic; |
signal set_mode : std_logic; |
|
function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is |
variable ret : arp_store_rslt_t; |
begin |
case status is |
when IDLE => |
ret := status; |
when others => |
if mode = MWRITE then |
ret := BUSY; |
else |
ret := status; |
end if; |
end case; |
return ret; |
end read_status; |
|
begin |
combinatorial : process ( |
-- input signals |
read_req, write_req, clear_store, reset, |
-- state variables |
ip_ram, mac_ram, st_state, next_write_addr, num_entries, |
next_read_addr, entry_found, mode, req_entry, |
-- busses |
next_st_state, arp_entry_val, mode_val, write_addr, |
-- control signals |
set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found, |
write_ram, set_mode |
) |
begin |
-- set output followers |
read_result.status <= IDLE; |
read_result.entry <= entry_found; |
entry_count <= to_unsigned(num_entries,8); |
|
-- set bus defaults |
next_st_state <= IDLE; |
mode_val <= MREAD; |
write_addr <= next_write_addr; |
|
-- set signal defaults |
set_st_state <= '0'; |
set_next_write_addr <= HOLD; |
set_num_entries <= HOLD; |
set_next_read_addr <= HOLD; |
write_ram <= '0'; |
set_entry_found <= '0'; |
set_mode <= '0'; |
|
-- STORE FSM |
case st_state is |
when IDLE => |
if write_req.req = '1' then |
-- need to search to see if this IP already there |
set_next_read_addr <= RST; -- start lookup from beginning |
mode_val <= MWRITE; |
set_mode <= '1'; |
next_st_state <= PAUSE; |
set_st_state <= '1'; |
elsif read_req.req = '1' then |
set_next_read_addr <= RST; -- start lookup from beginning |
mode_val <= MREAD; |
set_mode <= '1'; |
next_st_state <= PAUSE; |
set_st_state <= '1'; |
end if; |
|
when PAUSE => |
-- wait until read addr is latched and we get first data out of the ram |
read_result.status <= read_status(BUSY,mode); |
set_next_read_addr <= INCR; |
next_st_state <= SEARCH; |
set_st_state <= '1'; |
|
when SEARCH => |
read_result.status <= read_status(SEARCHING,mode); |
-- check if have a match at this entry |
if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then |
-- found it |
set_entry_found <= '1'; |
next_st_state <= FOUND; |
set_st_state <= '1'; |
elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then |
-- reached end of entry table |
read_result.status <= read_status(NOT_FOUND,mode); |
next_st_state <= NOT_FOUND; |
set_st_state <= '1'; |
else |
-- no match at this entry , go to next |
set_next_read_addr <= INCR; |
end if; |
|
when FOUND => |
read_result.status <= read_status(FOUND,mode); |
if mode = MWRITE then |
write_addr <= next_read_addr - 1; |
write_ram <= '1'; |
next_st_state <= IDLE; |
set_st_state <= '1'; |
elsif read_req.req = '0' then -- wait in this state until request de-asserted |
next_st_state <= IDLE; |
set_st_state <= '1'; |
end if; |
|
when NOT_FOUND => |
read_result.status <= read_status(NOT_FOUND,mode); |
if mode = MWRITE then |
-- need to write into the next free slot |
write_addr <= next_write_addr; |
write_ram <= '1'; |
set_next_write_addr <= INCR; |
if num_entries < MAX_ARP_ENTRIES then |
-- if not full, count another entry (if full, it just wraps) |
set_num_entries <= INCR; |
end if; |
next_st_state <= IDLE; |
set_st_state <= '1'; |
elsif read_req.req = '0' then -- wait in this state until request de-asserted |
next_st_state <= IDLE; |
set_st_state <= '1'; |
end if; |
|
end case; |
end process; |
|
sequential : process (clk) |
begin |
if rising_edge(clk) then |
-- ram processing |
if write_ram = '1' then |
ip_ram(write_addr) <= req_entry.ip; |
mac_ram(write_addr) <= req_entry.mac; |
end if; |
if next_read_addr < MAX_ARP_ENTRIES then |
arp_entry_val.ip <= ip_ram(next_read_addr); |
arp_entry_val.mac <= mac_ram(next_read_addr); |
else |
arp_entry_val.ip <= (others => '0'); |
arp_entry_val.mac <= (others => '0'); |
end if; |
|
if reset = '1' or clear_store = '1' then |
-- reset state variables |
st_state <= IDLE; |
next_write_addr <= 0; |
num_entries <= 0; |
next_read_addr <= 0; |
entry_found.ip <= (others => '0'); |
entry_found.mac <= (others => '0'); |
req_entry.ip <= (others => '0'); |
req_entry.mac <= (others => '0'); |
mode <= MREAD; |
|
else |
-- Next req_state processing |
if set_st_state = '1' then |
st_state <= next_st_state; |
else |
st_state <= st_state; |
end if; |
|
-- mode setting and write request latching |
if set_mode = '1' then |
mode <= mode_val; |
if mode_val = MWRITE then |
req_entry <= write_req.entry; |
else |
req_entry.ip <= read_req.ip; |
req_entry.mac <= (others => '0'); |
end if; |
else |
mode <= mode; |
req_entry <= req_entry; |
end if; |
|
-- latch entry found |
if set_entry_found = '1' then |
entry_found <= arp_entry_val; |
else |
entry_found <= entry_found; |
end if; |
|
-- next_write_addr counts and wraps |
case set_next_write_addr is |
when HOLD => next_write_addr <= next_write_addr; |
when RST => next_write_addr <= 0; |
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if; |
end case; |
|
-- num_entries counts and holds at max |
case set_num_entries is |
when HOLD => num_entries <= num_entries; |
when RST => num_entries <= 0; |
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if; |
end case; |
|
-- next_read_addr counts and wraps |
case set_next_read_addr is |
when HOLD => next_read_addr <= next_read_addr; |
when RST => next_read_addr <= 0; |
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if; |
end case; |
|
end if; |
end if; |
end process; |
|
end Behavioral; |
/udp_ip_stack/trunk/rtl/vhdl/arp.vhd
36,7 → 36,9
entity arp is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 1; -- (added for compatibility with arpv2. this value not used in this impl) |
MAX_ARP_ENTRIES : integer := 1 -- (added for compatibility with arpv2. this value not used in this impl) |
); |
Port ( |
-- lookup request signals |
/udp_ip_stack/trunk/rtl/vhdl/ml605/IP_complete.vhd
27,7 → 27,9
entity IP_complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- IP Layer signals |
73,7 → 75,9
COMPONENT IP_complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- IP Layer signals |
111,7 → 115,7
------------------------------------------------------------------------------ |
-- Component Declaration for the MAC layer |
------------------------------------------------------------------------------ |
component mac_layer |
component mac_layer_v2_1 |
port ( |
-- System controls |
------------------ |
184,8 → 188,10
IP_layer : IP_complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
) |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
PORT MAP ( |
-- IP Layer signals |
ip_tx_start => ip_tx_start, |
221,7 → 227,7
------------------------------------------------------------------------------ |
-- Instantiate the MAC layer |
------------------------------------------------------------------------------ |
mac_block : mac_layer |
mac_block : mac_layer_v2_1 |
Port map( |
-- System controls |
------------------ |
/udp_ip_stack/trunk/rtl/vhdl/ml605/UDP_Complete.vhd
28,7 → 28,9
entity UDP_Complete is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- UDP TX signals |
68,6 → 70,9
); |
end UDP_Complete; |
|
|
|
|
architecture structural of UDP_Complete is |
|
------------------------------------------------------------------------------ |
77,7 → 82,9
COMPONENT UDP_Complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- UDP TX signals |
118,7 → 125,8
------------------------------------------------------------------------------ |
-- Component Declaration for the MAC layer |
------------------------------------------------------------------------------ |
component mac_layer |
component mac_v2_2 |
-- component xv6mac_straight |
port ( |
-- System controls |
------------------ |
196,11 → 204,13
------------------------------------------------------------------------------ |
|
udp_block: UDP_Complete_nomac |
generic map ( |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
PORT MAP ( |
PORT MAP ( |
-- UDP TX signals |
udp_tx_start => udp_tx_start, |
udp_txi => udp_txi, |
238,7 → 248,8
------------------------------------------------------------------------------ |
-- Instantiate the MAC layer |
------------------------------------------------------------------------------ |
mac_block : mac_layer |
mac_block : mac_v2_2 |
-- mac_block : xv6mac_straight |
Port map( |
-- System controls |
------------------ |
282,3 → 293,4
|
end structural; |
|
|
/udp_ip_stack/trunk/rtl/vhdl/ml605/UDP_integration_example.vhd
35,6 → 35,8
-- System controls |
------------------ |
PBTX : in std_logic; |
PB_DO_SECOND_TX : in std_logic; |
DO_SECOND_TX_LED : out std_logic; |
UDP_RX : out std_logic; |
UDP_Start : out std_logic; |
PBTX_LED : out std_logic; |
64,13 → 66,16
|
architecture Behavioral of UDP_integration_example is |
|
|
------------------------------------------------------------------------------ |
-- Component Declaration for the complete IP layer |
-- Component Declaration for the complete UDP layer |
------------------------------------------------------------------------------ |
component UDP_Complete |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- UDP TX signals |
110,10 → 115,13
); |
end component; |
|
-- for UDP_block : UDP_Complete use configuration work.UDP_Complete.udpc_multi_slot_arp; |
|
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT); |
|
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR); |
type count_mode_type is (RST, INCR, HOLD); |
type set_clr_type is (SET, CLR, HOLD); |
type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD); |
|
-- system signals |
signal clk_int : std_logic; |
136,7 → 144,9
signal tx_start_reg : std_logic; |
signal tx_started_reg : std_logic; |
signal tx_fin_reg : std_logic; |
|
signal prime_second_tx : std_logic; -- if want to do a 2nd tx after the first |
signal do_second_tx : std_logic; -- if need to do a 2nd tx as next tx |
|
-- control signals |
signal next_state : state_type; |
signal set_state : std_logic; |
148,6 → 158,7
signal set_tx_fin : set_clr_type; |
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0); |
signal control_int : udp_control_type; |
signal set_second_tx : sec_tx_ctrl_type; |
|
begin |
|
154,11 → 165,12
process ( |
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, |
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int, |
reset, tx_started_reg, tx_fin_reg, tx_start_reg |
reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx, |
PB_DO_SECOND_TX, do_second_tx |
) |
begin |
-- set up our local addresses and default controls |
our_ip <= x"c0a80509"; -- 192.168.5.9 |
our_ip <= x"c0a80019"; -- 192.168.0.25 |
our_mac <= x"002320212223"; |
control_int.ip_controls.arp_controls.clear_cache <= '0'; |
|
174,6 → 186,7
TX_Completed <= tx_fin_reg; |
TX_RSLT_0 <= udp_tx_result_int(0); |
TX_RSLT_1 <= udp_tx_result_int(1); |
DO_SECOND_TX_LED <= prime_second_tx; |
|
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0 |
display (7 downto 4) <= ip_pkt_count_int (3 downto 0); |
183,6 → 196,9
when IDLE => display (3 downto 0) <= "0001"; |
when WAIT_RX_DONE => display (3 downto 0) <= "0010"; |
when DATA_OUT => display (3 downto 0) <= "0011"; |
when PAUSE => display (3 downto 0) <= "0100"; |
when CHECK_SECOND_TX => display (3 downto 0) <= "0101"; |
when SET_SEC_HDR => display (3 downto 0) <= "0110"; |
end case; |
|
end process; |
193,12 → 209,12
tx_proc_combinatorial: process( |
-- inputs |
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int, |
udp_tx_int.data.data_out_valid, PBTX, |
udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX, |
-- state |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx, |
-- controls |
next_state, set_state, set_count, set_hdr, set_tx_start, set_last, |
set_tx_started, set_tx_fin, first_byte_rx |
set_tx_started, set_tx_fin, first_byte_rx, set_second_tx |
) |
begin |
-- set output_followers |
218,7 → 234,12
first_byte_rx <= (others => '0'); |
udp_tx_int.data.data_out <= (others => '0'); |
udp_tx_int.data.data_out_valid <= '0'; |
set_second_tx <= HOLD; |
|
if PB_DO_SECOND_TX = '1' then |
set_second_tx <= PRIME; |
end if; |
|
-- FSM |
case state is |
|
259,6 → 280,7
set_tx_start <= CLR; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
set_second_tx <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
else |
276,7 → 298,7
set_last <= '1'; |
set_tx_fin <= SET; |
set_tx_started <= CLR; |
next_state <= IDLE; |
next_state <= PAUSE; |
set_state <= '1'; |
else |
set_count <= INCR; |
283,7 → 305,30
end if; |
end if; |
end if; |
|
when PAUSE => |
next_state <= CHECK_SECOND_TX; |
set_state <= '1'; |
|
|
when CHECK_SECOND_TX => |
if prime_second_tx = '1' then |
set_second_tx <= DO; |
next_state <= SET_SEC_HDR; |
set_state <= '1'; |
else |
set_second_tx <= CLR; |
next_state <= IDLE; |
set_state <= '1'; |
end if; |
|
when SET_SEC_HDR => |
set_hdr <= '1'; |
set_tx_started <= SET; |
set_tx_start <= SET; |
next_state <= DATA_OUT; |
set_state <= '1'; |
|
end case; |
end process; |
|
306,6 → 351,8
tx_started_reg <= '0'; |
tx_fin_reg <= '0'; |
PBTX_LED <= '0'; |
do_second_tx <= '0'; |
prime_second_tx <= '0'; |
else |
PBTX_LED <= PBTX; |
|
325,11 → 372,21
|
-- set tx hdr |
if set_hdr = '1' then |
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP |
if first_byte_rx = x"42" then |
-- select the dst addr of the tx: |
-- if do_second_tx, to solaris box |
-- otherwise control according to first byte of received data: |
-- B = broadcast |
-- C = to dummy address to test timeout |
-- D to solaris box |
-- otherwise, direct to sender |
if do_second_tx = '1' then |
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5 |
elsif first_byte_rx = x"42" then |
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr |
elsif first_byte_rx = x"43" then |
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout |
elsif first_byte_rx = x"44" then |
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5 |
else |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender |
end if; |
361,8 → 418,22
when CLR => tx_fin_reg <= '0'; |
when HOLD => tx_fin_reg <= tx_fin_reg; |
end case; |
|
-- set do_second_tx |
case set_second_tx is |
when PRIME => |
prime_second_tx <= '1'; |
when DO => |
prime_second_tx <= '0'; |
do_second_tx <= '1'; |
when CLR => |
prime_second_tx <= '0'; |
do_second_tx <= '0'; |
when HOLD => |
prime_second_tx <= prime_second_tx; |
do_second_tx <= do_second_tx; |
end case; |
|
|
end if; |
end if; |
|
375,7 → 446,7
------------------------------------------------------------------------------ |
UDP_block : UDP_Complete |
generic map ( |
ARP_TIMEOUT => 30 -- timeout in seconds |
ARP_TIMEOUT => 10 -- timeout in seconds |
) |
PORT MAP ( |
-- UDP interface |
/udp_ip_stack/trunk/rtl/vhdl/ml605/xv6mac_straight.vhd
0,0 → 1,463
-------------------------------------------------------------------------------- |
-- Project : low latency UDP |
-- File : xv6mac_straight |
-- Version : 0.0 |
------------------------------------------------------------------------------- |
-- |
-- |
-- Description: This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs |
-- |
-- |
-- |
-- --------------------------------------------------------------------- |
-- | EXAMPLE DESIGN WRAPPER | |
-- | --------------------------------------------------------| |
-- | |FIFO BLOCK WRAPPER | |
-- | | | |
-- | | | |
-- | | -----------------------------------------| |
-- | | | BLOCK LEVEL WRAPPER | |
-- | | | --------------------- | |
-- | | | | V6 EMAC CORE | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | |
-- | | | | | | | --------- | |
-- | | |->|->----------->|--|--->| Tx Tx |--| |--->| |
-- | | | | | | AXI-S PHY | | | | |
-- | | | | | | I/F I/F | | | | |
-- | | | | | | | | PHY | | |
-- | | | | | | | | I/F | | |
-- | | | | | | | | | | |
-- | | | | | | Rx Rx | | | | |
-- | | | | | | AX)-S PHY | | | | |
-- | | |<-|<-------------|----| I/F I/F |<-| |<---| |
-- | | | | | | | --------- | |
-- | -------- | | --------------------- | |
-- | | | | |
-- | | -----------------------------------------| |
-- | --------------------------------------------------------| |
-- --------------------------------------------------------------------- |
-- |
-------------------------------------------------------------------------------- |
|
library unisim; |
use unisim.vcomponents.all; |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
|
entity xv6mac_straight is |
port ( |
-- System controls |
------------------ |
glbl_rst : in std_logic; -- asynchronous reset |
mac_reset : in std_logic; -- reset mac layer |
clk_in_p : in std_logic; -- 200MHz clock input from board |
clk_in_n : in std_logic; |
|
-- MAC Transmitter (AXI-S) Interface |
--------------------------------------------- |
mac_tx_clock : out std_logic; -- data sampled on rising edge |
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx |
mac_tx_tvalid : in std_logic; -- tdata is valid |
mac_tx_tready : out std_logic; -- mac is ready to accept data |
mac_tx_tlast : in std_logic; -- indicates last byte of frame |
|
-- MAC Receiver (AXI-S) Interface |
------------------------------------------ |
mac_rx_clock : out std_logic; -- data valid on rising edge |
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received |
mac_rx_tvalid : out std_logic; -- indicates tdata is valid |
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data |
mac_rx_tlast : out std_logic; -- indicates last byte of the trame |
|
-- GMII Interface |
----------------- |
phy_resetn : out std_logic; |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
gmii_col : in std_logic; |
gmii_crs : in std_logic; |
mii_tx_clk : in std_logic |
); |
end xv6mac_straight; |
|
architecture wrapper of xv6mac_straight is |
|
------------------------------------------------------------------------------ |
-- Component declaration for the internal mac layer |
------------------------------------------------------------------------------ |
component mac_layer_v2_2_block |
port( |
gtx_clk : in std_logic; |
|
-- Receiver Interface |
---------------------------- |
rx_statistics_vector : out std_logic_vector(27 downto 0); |
rx_statistics_valid : out std_logic; |
|
rx_mac_aclk : out std_logic; |
rx_reset : out std_logic; |
rx_axis_mac_tdata : out std_logic_vector(7 downto 0); |
rx_axis_mac_tvalid : out std_logic; |
rx_axis_mac_tlast : out std_logic; |
rx_axis_mac_tuser : out std_logic; |
|
-- Transmitter Interface |
------------------------------- |
tx_ifg_delay : in std_logic_vector(7 downto 0); |
tx_statistics_vector : out std_logic_vector(31 downto 0); |
tx_statistics_valid : out std_logic; |
|
tx_reset : out std_logic; |
tx_axis_mac_tdata : in std_logic_vector(7 downto 0); |
tx_axis_mac_tvalid : in std_logic; |
tx_axis_mac_tlast : in std_logic; |
tx_axis_mac_tuser : in std_logic; |
tx_axis_mac_tready : out std_logic; |
tx_collision : out std_logic; |
tx_retransmit : out std_logic; |
|
-- MAC Control Interface |
------------------------ |
pause_req : in std_logic; |
pause_val : in std_logic_vector(15 downto 0); |
|
-- Reference clock for IDELAYCTRL's |
refclk : in std_logic; |
|
-- GMII Interface |
----------------- |
gmii_txd : out std_logic_vector(7 downto 0); |
gmii_tx_en : out std_logic; |
gmii_tx_er : out std_logic; |
gmii_tx_clk : out std_logic; |
gmii_rxd : in std_logic_vector(7 downto 0); |
gmii_rx_dv : in std_logic; |
gmii_rx_er : in std_logic; |
gmii_rx_clk : in std_logic; |
|
-- asynchronous reset |
----------------- |
glbl_rstn : in std_logic; |
rx_axi_rstn : in std_logic; |
tx_axi_rstn : in std_logic |
|
); |
end component; |
|
|
------------------------------------------------------------------------------ |
-- Component Declaration for the Clock generator |
------------------------------------------------------------------------------ |
|
component clk_wiz_v2_2 |
port ( |
-- Clock in ports |
CLK_IN1_P : in std_logic; |
CLK_IN1_N : in std_logic; |
-- Clock out ports |
CLK_OUT1 : out std_logic; |
CLK_OUT2 : out std_logic; |
CLK_OUT3 : out std_logic; |
-- Status and control signals |
RESET : in std_logic; |
LOCKED : out std_logic |
); |
end component; |
|
|
------------------------------------------------------------------------------ |
-- Component declaration for the reset synchroniser |
------------------------------------------------------------------------------ |
component reset_sync_v2_2 |
port ( |
reset_in : in std_logic; -- Active high asynchronous reset |
enable : in std_logic; |
clk : in std_logic; -- clock to be sync'ed to |
reset_out : out std_logic -- "Synchronised" reset signal |
); |
end component; |
|
------------------------------------------------------------------------------ |
-- Component declaration for the synchroniser |
------------------------------------------------------------------------------ |
component sync_block_v2_2 |
port ( |
clk : in std_logic; |
data_in : in std_logic; |
data_out : out std_logic |
); |
end component; |
|
------------------------------------------------------------------------------ |
-- Constants used in this top level wrapper. |
------------------------------------------------------------------------------ |
constant BOARD_PHY_ADDR : std_logic_vector(7 downto 0) := "00000111"; |
|
|
------------------------------------------------------------------------------ |
-- internal signals used in this top level wrapper. |
------------------------------------------------------------------------------ |
|
-- example design clocks |
signal gtx_clk_bufg : std_logic; |
signal refclk_bufg : std_logic; |
signal rx_mac_aclk : std_logic; |
|
-- tx handshaking |
signal mac_tx_tready_int : std_logic; |
signal tx_full_reg : std_logic; |
signal tx_full_val : std_logic; |
signal tx_data_reg : std_logic_vector(7 downto 0); |
signal tx_last_reg : std_logic; |
signal set_tx_reg : std_logic; |
|
signal phy_resetn_int : std_logic; |
|
-- resets (and reset generation) |
signal local_chk_reset : std_logic; |
signal chk_reset_int : std_logic; |
signal chk_pre_resetn : std_logic := '0'; |
signal chk_resetn : std_logic := '0'; |
signal dcm_locked : std_logic; |
|
signal glbl_rst_int : std_logic; |
signal phy_reset_count : unsigned(5 downto 0); |
signal glbl_rst_intn : std_logic; |
|
-- pipeline register for RX signals |
signal rx_data_val : std_logic_vector(7 downto 0); |
signal rx_tvalid_val : std_logic; |
signal rx_tlast_val : std_logic; |
signal rx_data_reg : std_logic_vector(7 downto 0); |
signal rx_tvalid_reg : std_logic; |
signal rx_tlast_reg : std_logic; |
|
attribute keep : string; |
attribute keep of gtx_clk_bufg : signal is "true"; |
attribute keep of refclk_bufg : signal is "true"; |
attribute keep of mac_tx_tready_int : signal is "true"; |
attribute keep of tx_full_reg : signal is "true"; |
|
|
------------------------------------------------------------------------------ |
-- Begin architecture |
------------------------------------------------------------------------------ |
|
begin |
|
combinatorial: process ( |
rx_data_reg, rx_tvalid_reg, rx_tlast_reg, |
mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg |
) |
begin |
-- output followers |
mac_rx_tdata <= rx_data_reg; |
mac_rx_tvalid <= rx_tvalid_reg; |
mac_rx_tlast <= rx_tlast_reg; |
mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int); -- if not full, we are ready to accept |
|
-- control defaults |
tx_full_val <= tx_full_reg; |
set_tx_reg <= '0'; |
|
-- tx handshaking logic |
if mac_tx_tvalid = '1' then |
tx_full_val <= '1'; |
set_tx_reg <= '1'; |
elsif mac_tx_tready_int = '1' then |
tx_full_val <= '0'; |
end if; |
|
end process; |
|
sequential: process(gtx_clk_bufg) |
begin |
if rising_edge(gtx_clk_bufg) then |
if chk_resetn = '0' then |
-- reset state variables |
rx_data_reg <= (others => '0'); |
rx_tvalid_reg <= '0'; |
rx_tlast_reg <= '0'; |
tx_full_reg <= '0'; |
tx_data_reg <= (others => '0'); |
tx_last_reg <= '0'; |
else |
-- register rx data |
rx_data_reg <= rx_data_val; |
rx_tvalid_reg <= rx_tvalid_val; |
rx_tlast_reg <= rx_tlast_val; |
|
-- process tx tvalid and tready |
tx_full_reg <= tx_full_val; |
if set_tx_reg = '1' then |
tx_data_reg <= mac_tx_tdata; |
tx_last_reg <= mac_tx_tlast; |
else |
tx_data_reg <= tx_data_reg; |
tx_last_reg <= tx_last_reg; |
end if; |
end if; |
end if; |
end process; |
|
------------------------------------------------------------------------------ |
-- Instantiate the Tri-Mode EMAC Block wrapper |
------------------------------------------------------------------------------ |
v6emac_block : mac_layer_v2_2_block |
port map( |
gtx_clk => gtx_clk_bufg, |
|
-- Client Receiver Interface |
rx_statistics_vector => open, |
rx_statistics_valid => open, |
|
rx_mac_aclk => open, |
rx_reset => open, |
rx_axis_mac_tdata => rx_data_val, |
rx_axis_mac_tvalid => rx_tvalid_val, |
rx_axis_mac_tlast => rx_tlast_val, |
rx_axis_mac_tuser => open, |
|
-- Client Transmitter Interface |
tx_ifg_delay => x"00", |
tx_statistics_vector => open, |
tx_statistics_valid => open, |
|
tx_reset => open, |
tx_axis_mac_tdata => tx_data_reg, |
tx_axis_mac_tvalid => tx_full_reg, |
tx_axis_mac_tlast => tx_last_reg, |
tx_axis_mac_tuser => '0', |
tx_axis_mac_tready => mac_tx_tready_int, |
tx_collision => open, |
tx_retransmit => open, |
|
-- Flow Control |
pause_req => '0', |
pause_val => x"0000", |
|
-- Reference clock for IDELAYCTRL's |
refclk => refclk_bufg, |
|
-- GMII Interface |
gmii_txd => gmii_txd, |
gmii_tx_en => gmii_tx_en, |
gmii_tx_er => gmii_tx_er, |
gmii_tx_clk => gmii_tx_clk, |
gmii_rxd => gmii_rxd, |
gmii_rx_dv => gmii_rx_dv, |
gmii_rx_er => gmii_rx_er, |
gmii_rx_clk => gmii_rx_clk, |
|
-- asynchronous reset |
glbl_rstn => chk_resetn, |
rx_axi_rstn => '1', |
tx_axi_rstn => '1' |
); |
|
|
|
------------------------------------------------------------------------------ |
-- Clock logic to generate required clocks from the 200MHz on board |
-- if 125MHz is available directly this can be removed |
------------------------------------------------------------------------------ |
clock_generator : clk_wiz_v2_2 |
port map ( |
-- Clock in ports |
CLK_IN1_P => clk_in_p, |
CLK_IN1_N => clk_in_n, |
-- Clock out ports |
CLK_OUT1 => gtx_clk_bufg, |
CLK_OUT2 => open, |
CLK_OUT3 => refclk_bufg, |
-- Status and control signals |
RESET => glbl_rst, |
LOCKED => dcm_locked |
); |
|
----------------- |
-- global reset |
glbl_reset_gen : reset_sync_v2_2 |
port map ( |
clk => gtx_clk_bufg, |
enable => dcm_locked, |
reset_in => glbl_rst, |
reset_out => glbl_rst_int |
); |
|
glbl_rst_intn <= not glbl_rst_int; |
|
-- generate the user side clocks |
mac_tx_clock <= gtx_clk_bufg; |
mac_rx_clock <= gtx_clk_bufg; |
|
------------------------------------------------------------------------------ |
-- Generate resets |
------------------------------------------------------------------------------ |
-- in each case the async reset is first captured and then synchronised |
|
|
local_chk_reset <= glbl_rst or mac_reset; |
|
----------------- |
-- data check reset |
chk_reset_gen : reset_sync_v2_2 |
port map ( |
clk => gtx_clk_bufg, |
enable => dcm_locked, |
reset_in => local_chk_reset, |
reset_out => chk_reset_int |
); |
|
-- Create fully synchronous reset in the gtx clock domain. |
gen_chk_reset : process (gtx_clk_bufg) |
begin |
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then |
if chk_reset_int = '1' then |
chk_pre_resetn <= '0'; |
chk_resetn <= '0'; |
else |
chk_pre_resetn <= '1'; |
chk_resetn <= chk_pre_resetn; |
end if; |
end if; |
end process gen_chk_reset; |
|
|
----------------- |
-- PHY reset |
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles |
-- this is derived using the 125MHz available and a 6 bit counter |
gen_phy_reset : process (gtx_clk_bufg) |
begin |
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then |
if glbl_rst_intn = '0' then |
phy_resetn_int <= '0'; |
phy_reset_count <= (others => '0'); |
else |
if phy_reset_count /= "111111" then |
phy_reset_count <= phy_reset_count + "000001"; |
else |
phy_resetn_int <= '1'; |
end if; |
end if; |
end if; |
end process gen_phy_reset; |
|
phy_resetn <= phy_resetn_int; |
|
|
end wrapper; |
/udp_ip_stack/trunk/rtl/vhdl/ml605/udp_constraints.ucf
20,17 → 20,18
NET "display[6]" LOC = AE24; |
NET "display[7]" LOC = AD24; |
|
NET PBTX_LED LOC = AD21; |
NET UDP_RX LOC = AH27; |
NET UDP_START LOC = AH28; |
NET TX_RSLT_0 LOC = AE21; |
NET TX_RSLT_1 LOC = AP24; |
NET PBTX_LED LOC = AD21; |
NET UDP_RX LOC = AH27; |
NET DO_SECOND_TX_LED LOC = AH28; |
NET TX_RSLT_0 LOC = AE21; |
NET TX_RSLT_1 LOC = AP24; |
|
|
|
#### Module Push_Buttons_4Bit constraints |
NET PBTX LOC = H17; |
NET reset_leds LOC = G26; |
NET PBTX LOC = H17; |
NET PB_DO_SECOND_TX LOC = A18; |
NET reset_leds LOC = G26; |
|
#### Module DIP_Switches_4Bit constraints |
|
/udp_ip_stack/trunk/rtl/vhdl/arp_REQ.vhd
0,0 → 1,316
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Peter Fall |
-- |
-- Create Date: 12:00:04 05/31/2011 |
-- Design Name: |
-- Module Name: arp_REQ - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- handle requests for ARP resolution |
-- responds from single entry cache or searches external arp store, or asks to send a request |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created from arp.vhd 0.2 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.arp_types.all; |
|
entity arp_req is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error |
); |
Port ( |
-- lookup request signals |
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC |
arp_req_rslt : out arp_req_rslt_type; -- the result |
-- external arp store signals |
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store |
arp_store_result : in arp_store_result_t; -- the result |
-- network request signals |
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network |
arp_nwk_result : in arp_nwk_result_t; -- the result |
-- system signals |
clear_cache : in std_logic; -- clear the internal cache |
clk : in std_logic; |
reset : in STD_LOGIC |
); |
end arp_req; |
|
architecture Behavioral of arp_req is |
|
type req_state_t is (IDLE,LOOKUP,WAIT_REPLY,PAUSE1,PAUSE2,PAUSE3); |
type set_cntr_t is (HOLD,CLR,INCR); |
type set_clr_type is (SET, CLR, HOLD); |
|
-- state variables |
signal req_state : req_state_t; |
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup |
signal arp_entry_cache : arp_entry_t; -- single entry cache for fast response |
signal cache_valid : std_logic; -- single entry cache is valid |
signal nwk_rx_cntr : unsigned(7 downto 0); -- counts nwk rx pkts that dont satisfy |
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz |
signal timer : unsigned (7 downto 0); -- counts seconds timeout |
signal timeout_reg : std_logic; |
|
-- busses |
signal next_req_state : req_state_t; |
signal arp_entry_val : arp_entry_t; |
|
-- requester control signals |
signal set_req_state : std_logic; |
signal set_req_ip : std_logic; |
signal store_arp_cache : std_logic; |
signal set_nwk_rx_cntr : set_cntr_t; |
signal set_timer : set_cntr_t; -- timer reset, count, hold control |
signal timer_enable : std_logic; -- enable the timer counting |
signal set_timeout : set_clr_type; -- control the timeout register |
signal clear_cache_valid : std_logic; |
|
begin |
req_combinatorial : process ( |
-- input signals |
arp_req_req, arp_store_result, arp_nwk_result, clear_cache, |
-- state variables |
req_state, req_ip_addr, arp_entry_cache, cache_valid, nwk_rx_cntr, |
freq_scaler, timer, timeout_reg, |
-- busses |
next_req_state, arp_entry_val, |
-- control signals |
set_req_state, set_req_ip, store_arp_cache, set_nwk_rx_cntr, clear_cache_valid, |
set_timer, timer_enable, set_timeout |
) |
begin |
-- set output followers |
arp_req_rslt.got_mac <= '0'; -- set initial value of request result outputs |
arp_req_rslt.got_err <= '0'; |
arp_req_rslt.mac <= (others => '0'); |
arp_store_req.req <= '0'; |
arp_store_req.ip <= (others => '0'); |
arp_nwk_req.req <= '0'; |
arp_nwk_req.ip <= (others => '0'); |
|
-- zero time response to lookup request if already in cache |
if arp_req_req.lookup_req = '1' and arp_req_req.ip = arp_entry_cache.ip and cache_valid = '1' then |
arp_req_rslt.got_mac <= '1'; |
arp_req_rslt.mac <= arp_entry_cache.mac; |
elsif arp_req_req.lookup_req = '1' then |
-- hold off got_mac while req is there as arp_entry will not be correct yet |
arp_req_rslt.got_mac <= '0'; |
arp_req_rslt.mac <= arp_entry_cache.mac; |
else |
arp_req_rslt.got_mac <= cache_valid; |
arp_req_rslt.mac <= arp_entry_cache.mac; |
end if; |
|
if arp_req_req.lookup_req = '1' then |
-- ensure any existing error report is killed at the start of a request |
arp_req_rslt.got_err <= '0'; |
else |
arp_req_rslt.got_err <= timeout_reg; |
end if; |
|
-- set signal defaults |
next_req_state <= IDLE; |
set_req_state <= '0'; |
set_req_ip <= '0'; |
store_arp_cache <= '0'; |
arp_entry_val.ip <= (others => '0'); |
arp_entry_val.mac <= (others => '0'); |
set_nwk_rx_cntr <= HOLD; |
set_timer <= INCR; -- default is timer running, unless we hold or reset it |
set_timeout <= HOLD; |
timer_enable <= '0'; |
clear_cache_valid <= clear_cache; |
|
-- combinatorial logic |
if freq_scaler = x"00000000" then |
timer_enable <= '1'; |
end if; |
|
-- REQ FSM |
case req_state is |
when IDLE => |
set_timer <= CLR; |
if arp_req_req.lookup_req = '1' then |
-- check if we already have the info in cache |
if arp_req_req.ip = arp_entry_cache.ip and cache_valid = '1' then |
-- already have this IP - feed output back |
arp_req_rslt.got_mac <= '1'; |
arp_req_rslt.mac <= arp_entry_cache.mac; |
else |
clear_cache_valid <= '1'; -- remove cache entry |
set_timeout <= CLR; |
next_req_state <= LOOKUP; |
set_req_state <= '1'; |
set_req_ip <= '1'; |
end if; |
end if; |
|
when LOOKUP => |
-- put request on the store |
arp_store_req.ip <= req_ip_addr; |
arp_store_req.req <= '1'; |
case arp_store_result.status is |
when FOUND => |
-- update the cache |
arp_entry_val <= arp_store_result.entry; |
store_arp_cache <= '1'; |
-- and feed output back |
arp_req_rslt.got_mac <= '1'; |
arp_req_rslt.mac <= arp_store_result.entry.mac; |
next_req_state <= IDLE; |
set_req_state <= '1'; |
|
when NOT_FOUND => |
-- need to request from the network |
set_timer <= CLR; |
set_nwk_rx_cntr <= CLR; |
arp_nwk_req.req <= '1'; |
arp_nwk_req.ip <= req_ip_addr; |
next_req_state <= WAIT_REPLY; |
set_req_state <= '1'; |
|
when OTHERS => |
-- just keep waiting - no timeout (assumes lookup with either succeed or fail) |
end case; |
|
when WAIT_REPLY => |
case arp_nwk_result.status is |
when RECEIVED => |
-- store into cache |
arp_entry_val <= arp_nwk_result.entry; |
store_arp_cache <= '1'; |
-- and feed output back |
if arp_nwk_result.entry.ip = req_ip_addr then |
arp_req_rslt.got_mac <= '1'; |
arp_req_rslt.mac <= arp_nwk_result.entry.mac; |
next_req_state <= IDLE; |
set_req_state <= '1'; |
else |
if nwk_rx_cntr > ARP_MAX_PKT_TMO then |
set_timeout <= SET; |
next_req_state <= IDLE; |
set_req_state <= '1'; |
else |
set_nwk_rx_cntr <= INCR; |
end if; |
end if; |
|
when ERROR => |
set_timeout <= SET; |
|
when OTHERS => |
if timer >= ARP_TIMEOUT then |
set_timeout <= SET; |
next_req_state <= PAUSE1; |
set_req_state <= '1'; |
end if; |
end case; |
|
when PAUSE1 => |
next_req_state <= PAUSE2; |
set_req_state <= '1'; |
|
when PAUSE2 => |
next_req_state <= PAUSE3; |
set_req_state <= '1'; |
|
when PAUSE3 => |
next_req_state <= IDLE; |
set_req_state <= '1'; |
|
end case; |
end process; |
|
req_sequential : process (clk) |
begin |
if rising_edge(clk) then |
if reset = '1' then |
-- reset state variables |
req_state <= IDLE; |
req_ip_addr <= (others => '0'); |
arp_entry_cache.ip <= (others => '0'); |
arp_entry_cache.mac <= (others => '0'); |
cache_valid <= '0'; |
nwk_rx_cntr <= (others => '0'); |
freq_scaler <= to_unsigned(CLOCK_FREQ,32); |
timer <= (others => '0'); |
timeout_reg <= '0'; |
else |
-- Next req_state processing |
if set_req_state = '1' then |
req_state <= next_req_state; |
else |
req_state <= req_state; |
end if; |
|
-- Latch the requested IP address |
if set_req_ip = '1' then |
req_ip_addr <= arp_req_req.ip; |
else |
req_ip_addr <= req_ip_addr; |
end if; |
|
-- network received counter |
case set_nwk_rx_cntr is |
when CLR => nwk_rx_cntr <= (others => '0'); |
when INCR => nwk_rx_cntr <= nwk_rx_cntr + 1; |
when HOLD => nwk_rx_cntr <= nwk_rx_cntr; |
end case; |
|
-- set the arp_entry_cache |
if clear_cache_valid = '1' then |
arp_entry_cache <= arp_entry_cache; |
cache_valid <= '0'; |
elsif store_arp_cache = '1' then |
arp_entry_cache <= arp_entry_val; |
cache_valid <= '1'; |
else |
arp_entry_cache <= arp_entry_cache; |
cache_valid <= cache_valid; |
end if; |
|
-- freq scaling and 1-sec timer |
if freq_scaler = x"00000000" then |
freq_scaler <= to_unsigned(CLOCK_FREQ,32); |
else |
freq_scaler <= freq_scaler - 1; |
end if; |
|
-- timer processing |
case set_timer is |
when CLR => |
timer <= x"00"; |
when INCR => |
if timer_enable = '1' then |
timer <= timer + 1; |
else |
timer <= timer; |
end if; |
when HOLD => |
timer <= timer; |
end case; |
|
-- timeout latching |
case set_timeout is |
when CLR => timeout_reg <= '0'; |
when SET => timeout_reg <= '1'; |
when HOLD => timeout_reg <= timeout_reg; |
end case; |
|
end if; |
end if; |
end process; |
|
end Behavioral; |
/udp_ip_stack/trunk/rtl/vhdl/arpv2.vhd
0,0 → 1,311
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Peter Fall |
-- |
-- Create Date: 12:00:04 05/31/2011 |
-- Design Name: |
-- Module Name: arpv2 - Structural |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- handle simple IP lookup in 1-deep cache and arp store |
-- request cache fill through ARP protocol if required |
-- Handle ARP protocol |
-- Respond to ARP requests and replies |
-- Ignore pkts that are not ARP |
-- Ignore pkts that are not addressed to us |
-- |
-- structural decomposition includes |
-- arp TX block - encoding of ARP protocol |
-- arp RX block - decoding of ARP protocol |
-- arp REQ block - sequencing requests for resolution |
-- arp STORE block - storing address resolution entries (indexed by IP addr) |
-- arp sync block - sync between master RX clock and TX clock domains |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.arp_types.all; |
|
entity arpv2 is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store |
); |
Port ( |
-- lookup request signals |
arp_req_req : in arp_req_req_type; |
arp_req_rslt : out arp_req_rslt_type; |
-- MAC layer RX signals |
data_in_clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock |
data_in_last : in STD_LOGIC; -- indicates last data in frame |
-- MAC layer TX signals |
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx) |
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted |
data_out_clk : in std_logic; |
data_out_ready : in std_logic; -- indicates system ready to consume data |
data_out_valid : out std_logic; -- indicates data out is valid |
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame |
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame |
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
-- system signals |
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
control : in arp_control_type; |
req_count : out STD_LOGIC_VECTOR(7 downto 0) -- count of arp pkts received |
); |
end arpv2; |
|
architecture structural of arpv2 is |
|
COMPONENT arp_req |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error |
); |
Port ( |
-- lookup request signals |
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC |
arp_req_rslt : out arp_req_rslt_type; -- the result |
-- external arp store signals |
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store |
arp_store_result : in arp_store_result_t; -- the result |
-- network request signals |
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network |
arp_nwk_result : in arp_nwk_result_t; -- the result |
-- system signals |
clear_cache : in std_logic; -- clear the internal cache |
clk : in std_logic; |
reset : in STD_LOGIC |
); |
END COMPONENT; |
|
COMPONENT arp_tx |
PORT( |
-- control signals |
send_I_have : in std_logic; -- pulse will be latched |
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched) |
send_who_has : in std_logic; -- pulse will be latched |
ip_entry : in STD_LOGIC_VECTOR (31 downto 0); -- ip target for who_has req (will be latched) |
-- MAC layer TX signals |
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx) |
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted |
data_out_ready : in std_logic; -- indicates system ready to consume data |
data_out_valid : out std_logic; -- indicates data out is valid |
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame |
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame |
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
-- system signals |
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
tx_clk : in std_logic; |
reset : in std_logic |
); |
END COMPONENT; |
|
COMPONENT arp_rx |
PORT( |
-- MAC layer RX signals |
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock |
data_in_last : in STD_LOGIC; -- indicates last data in frame |
-- ARP output signals |
recv_who_has : out std_logic; -- pulse will be latched |
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to) |
recv_I_have : out std_logic; -- pulse will be latched |
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg |
-- control and status signals |
req_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
-- system signals |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
rx_clk : in std_logic; |
reset : in STD_LOGIC |
); |
END COMPONENT; |
|
|
COMPONENT arp_store_br |
generic ( |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store |
); |
Port ( |
-- read signals |
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store |
read_result : out arp_store_result_t; -- the result |
-- write signals |
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store |
-- control and status signals |
clear_store : in std_logic; -- erase all entries |
entry_count : out unsigned(7 downto 0); -- how many entries currently in store |
-- system signals |
clk : in std_logic; |
reset : in STD_LOGIC |
); |
END COMPONENT; |
|
COMPONENT arp_sync |
Port ( |
-- REQ to TX |
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC |
send_who_has : out std_logic; |
ip_entry : out STD_LOGIC_VECTOR (31 downto 0); |
-- RX to TX |
recv_who_has : in std_logic; -- this is for us, we will respond |
arp_entry_for_who_has : in arp_entry_t; |
send_I_have : out std_logic; |
arp_entry : out arp_entry_t; |
-- RX to REQ |
I_have_received : in std_logic; |
nwk_result_status : out arp_nwk_rslt_t; |
-- System Signals |
rx_clk : in std_logic; |
tx_clk : in std_logic; |
reset : in std_logic |
); |
END COMPONENT; |
|
|
-- interconnect REQ -> ARP_TX |
signal arp_nwk_req_int : arp_nwk_request_t; -- tx req from REQ |
|
signal send_I_have_int : std_logic; |
signal arp_entry_int : arp_entry_t; |
signal send_who_has_int : std_logic; |
signal ip_entry_int : STD_LOGIC_VECTOR (31 downto 0); |
|
-- interconnect REQ <-> ARP_STORE |
signal arp_store_req_int : arp_store_rdrequest_t; -- lookup request |
signal arp_store_result_int: arp_store_result_t; -- lookup result |
|
-- interconnect ARP_RX -> REQ |
signal nwk_result_status_int : arp_nwk_rslt_t; -- response from a TX req |
|
-- interconnect ARP_RX -> ARP_STORE |
signal recv_I_have_int : std_logic; -- path to store new arp entry |
signal arp_entry_for_I_have_int: arp_entry_t; |
|
-- interconnect ARP_RX -> ARP_TX |
signal recv_who_has_int : std_logic; -- path for reply when we can anser |
signal arp_entry_for_who_has_int : arp_entry_t; -- target for who_has msg (ie, who to reply to) |
|
|
begin |
|
|
req : arp_req |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO |
) |
PORT MAP ( |
-- lookup request signals |
arp_req_req => arp_req_req, |
arp_req_rslt => arp_req_rslt, |
-- external arp store signals |
arp_store_req => arp_store_req_int, |
arp_store_result => arp_store_result_int, |
-- network request signals |
arp_nwk_req => arp_nwk_req_int, |
arp_nwk_result.status => nwk_result_status_int, |
arp_nwk_result.entry => arp_entry_for_I_have_int, |
-- system signals |
clear_cache => control.clear_cache, |
clk => data_in_clk, |
reset => reset |
); |
|
sync : arp_sync PORT MAP ( |
-- REQ to TX |
arp_nwk_req => arp_nwk_req_int, |
send_who_has => send_who_has_int, |
ip_entry => ip_entry_int, |
-- RX to TX |
recv_who_has => recv_who_has_int, |
arp_entry_for_who_has => arp_entry_for_who_has_int, |
send_I_have => send_I_have_int, |
arp_entry => arp_entry_int, |
-- RX to REQ |
I_have_received => recv_I_have_int, |
nwk_result_status => nwk_result_status_int, |
-- system |
rx_clk => data_in_clk, |
tx_clk => data_out_clk, |
reset => reset |
); |
|
tx : arp_tx PORT MAP ( |
-- control signals |
send_I_have => send_I_have_int, |
arp_entry => arp_entry_int, |
send_who_has => send_who_has_int, |
ip_entry => ip_entry_int, |
-- MAC layer TX signals |
mac_tx_req => mac_tx_req, |
mac_tx_granted => mac_tx_granted, |
data_out_ready => data_out_ready, |
data_out_valid => data_out_valid, |
data_out_first => data_out_first, |
data_out_last => data_out_last, |
data_out => data_out, |
-- system signals |
our_ip_address => our_ip_address, |
our_mac_address => our_mac_address, |
tx_clk => data_out_clk, |
reset => reset |
); |
|
rx : arp_rx PORT MAP ( |
-- MAC layer RX signals |
data_in => data_in, |
data_in_valid => data_in_valid, |
data_in_last => data_in_last, |
-- ARP output signals |
recv_who_has => recv_who_has_int, |
arp_entry_for_who_has=> arp_entry_for_who_has_int, |
recv_I_have => recv_I_have_int, |
arp_entry_for_I_have=> arp_entry_for_I_have_int, |
-- control and status signals |
req_count => req_count, |
-- system signals |
our_ip_address => our_ip_address, |
rx_clk => data_in_clk, |
reset => reset |
); |
|
store : arp_store_br |
generic map ( |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
PORT MAP ( |
-- read signals |
read_req => arp_store_req_int, |
read_result => arp_store_result_int, |
-- write signals |
write_req.req => recv_I_have_int, |
write_req.entry => arp_entry_for_I_have_int, |
-- control and status signals |
clear_store => control.clear_cache, |
entry_count => open, |
-- system signals |
clk => data_in_clk, |
reset => reset |
); |
|
|
end structural; |
|
/udp_ip_stack/trunk/rtl/vhdl/arp_RX.vhd
0,0 → 1,372
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Peter Fall |
-- |
-- Create Date: 12:00:04 05/31/2011 |
-- Design Name: |
-- Module Name: arp_rx - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- handle receipt of arp pkt |
-- ignores other types of pkt |
-- |
-- When it receives an ARP pkt that is either addressed to our IP or is a global request, |
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along |
-- with associated mac or arp entry data. |
-- |
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup |
-- on the expectation that we will want to reply to this host. |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created - refactored from arp v0.02 module |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.arp_types.all; |
|
entity arp_rx is |
Port ( |
-- MAC layer RX signals |
data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock |
data_in_last : in STD_LOGIC; -- indicates last data in frame |
-- ARP output signals |
recv_who_has : out std_logic; -- pulse will be latched |
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to) |
recv_I_have : out std_logic; -- pulse will be latched |
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg |
-- control and status signals |
req_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received |
-- system signals |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
rx_clk : in std_logic; |
reset : in STD_LOGIC |
); |
end arp_rx; |
|
|
architecture Behavioral of arp_rx is |
|
type rx_state_t is (IDLE,PARSE,PROCESS_ARP,WAIT_END); |
type rx_event_t is (NO_EVENT,DATA); |
type count_mode_t is (RST,INCR,HOLD); |
type arp_oper_t is (NOP,REQUEST,REPLY); |
|
type tx_state_type is (IDLE,WAIT_MAC,SEND); |
|
-- state variables |
signal send_request_needed : std_logic; |
signal tx_mac_chn_reqd : std_logic; |
|
signal rx_state : rx_state_t; |
signal rx_count : unsigned (7 downto 0); |
signal arp_operation : arp_oper_t; |
signal arp_req_count : unsigned (7 downto 0); |
signal new_arp_entry : arp_entry_t; |
|
-- FIXME - remove these debug state signals |
signal arp_err_data : std_logic_vector (7 downto 0); |
signal set_err_data : std_logic; |
|
attribute keep : string; |
attribute keep of arp_err_data : signal is "true"; |
|
|
-- rx control signals |
signal next_rx_state : rx_state_t; |
signal set_rx_state : std_logic; |
signal rx_event : rx_event_t; |
signal rx_count_mode : count_mode_t; |
signal set_arp_oper : std_logic; |
signal arp_oper_set_val : arp_oper_t; |
signal dataval : std_logic_vector (7 downto 0); |
signal count_arp_rcvd : std_logic; |
|
signal set_mac5 : std_logic; |
signal set_mac4 : std_logic; |
signal set_mac3 : std_logic; |
signal set_mac2 : std_logic; |
signal set_mac1 : std_logic; |
signal set_mac0 : std_logic; |
|
signal set_ip3 : std_logic; |
signal set_ip2 : std_logic; |
signal set_ip1 : std_logic; |
signal set_ip0 : std_logic; |
|
|
|
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it |
-- Returns 1 if we should discard |
-- The following will make us ignore the frame (all values hexadecimal): |
-- PDU type /= 0806 |
-- Protocol Type /= 0800 |
-- Hardware Type /= 1 |
-- Hardware Length /= 6 |
-- Protocol Length /= 4 |
-- Operation /= 1 or 2 |
-- Target IP /= our IP (i.er. message is not meant for us) |
-- |
function not_our_arp(data : STD_LOGIC_VECTOR; count : unsigned; our_ip : std_logic_vector) return std_logic is |
begin |
if |
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP |
(count = 13 and data /= x"06") or |
(count = 14 and data /= x"00") or -- HW type 1 : eth |
(count = 15 and data /= x"01") or |
(count = 16 and data /= x"08") or -- Protocol 0800 : IP |
(count = 17 and data /= x"00") or |
(count = 18 and data /= x"06") or -- HW Length 6 |
(count = 19 and data /= x"04") or -- protocol length 4 |
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply) |
(count = 21 and data /= x"01" and data /= x"02") or |
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours |
(count = 39 and data /= our_ip(23 downto 16)) or |
(count = 40 and data /= our_ip(15 downto 8)) or |
(count = 41 and data /= our_ip(7 downto 0)) |
then |
return '1'; |
else |
return '0'; |
end if; |
end function not_our_arp; |
|
begin |
|
rx_combinatorial : process ( |
-- input signals |
data_in, data_in_valid, data_in_last, our_ip_address, |
-- state variables |
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry, |
-- control signals |
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val, |
dataval,set_mac5,set_mac4,set_mac3,set_mac2,set_mac1,set_mac0,set_ip3,set_ip2,set_ip1,set_ip0, set_err_data, |
count_arp_rcvd |
) |
begin |
-- set output followers |
req_count <= STD_LOGIC_VECTOR(arp_req_count); |
|
-- set defaults for combinatorial outputs |
recv_who_has <= '0'; |
arp_entry_for_who_has.ip <= (others => '0'); |
arp_entry_for_who_has.mac <= (others => '0'); |
recv_I_have <= '0'; |
arp_entry_for_I_have.ip <= (others => '0'); |
arp_entry_for_I_have.mac <= (others => '0'); |
|
-- set signal defaults |
next_rx_state <= IDLE; |
set_rx_state <= '0'; |
rx_event <= NO_EVENT; |
rx_count_mode <= HOLD; |
set_arp_oper <= '0'; |
arp_oper_set_val <= NOP; |
dataval <= (others => '0'); |
set_mac5 <= '0'; |
set_mac4 <= '0'; |
set_mac3 <= '0'; |
set_mac2 <= '0'; |
set_mac1 <= '0'; |
set_mac0 <= '0'; |
set_ip3 <= '0'; |
set_ip2 <= '0'; |
set_ip1 <= '0'; |
set_ip0 <= '0'; |
count_arp_rcvd <= '0'; |
set_err_data <= '0'; |
|
-- determine event (if any) |
if data_in_valid = '1' then |
rx_event <= DATA; |
end if; |
|
-- RX FSM |
case rx_state is |
when IDLE => |
rx_count_mode <= RST; |
case rx_event is |
when NO_EVENT => -- (nothing to do) |
when DATA => |
next_rx_state <= PARSE; |
set_rx_state <= '1'; |
rx_count_mode <= INCR; |
end case; |
|
when PARSE => |
case rx_event is |
when NO_EVENT => -- (nothing to do) |
when DATA => |
rx_count_mode <= INCR; |
-- handle early frame termination |
if data_in_last = '1' then |
next_rx_state <= IDLE; |
set_rx_state <= '1'; |
else |
-- check for end of frame. Also, detect and discard if not our frame |
if rx_count = 42 then |
next_rx_state <= PROCESS_ARP; |
set_rx_state <= '1'; |
elsif not_our_arp(data_in,rx_count,our_ip_address) = '1' then |
dataval <= data_in; |
set_err_data <= '1'; |
next_rx_state <= WAIT_END; |
set_rx_state <= '1'; |
elsif rx_count = 21 then |
-- capture ARP operation |
case data_in is |
when x"01" => |
arp_oper_set_val <= REQUEST; |
set_arp_oper <= '1'; |
when x"02" => |
arp_oper_set_val <= REPLY; |
set_arp_oper <= '1'; |
when others => -- ignore other values |
end case; |
-- capture source mac addr |
elsif rx_count = 22 then |
set_mac5 <= '1'; |
dataval <= data_in; |
elsif rx_count = 23 then |
set_mac4 <= '1'; |
dataval <= data_in; |
elsif rx_count = 24 then |
set_mac3 <= '1'; |
dataval <= data_in; |
elsif rx_count = 25 then |
set_mac2 <= '1'; |
dataval <= data_in; |
elsif rx_count = 26 then |
set_mac1 <= '1'; |
dataval <= data_in; |
elsif rx_count = 27 then |
set_mac0 <= '1'; |
dataval <= data_in; |
-- capture source ip addr |
elsif rx_count = 28 then |
set_ip3 <= '1'; |
dataval <= data_in; |
elsif rx_count = 29 then |
set_ip2 <= '1'; |
dataval <= data_in; |
elsif rx_count = 30 then |
set_ip1 <= '1'; |
dataval <= data_in; |
elsif rx_count = 31 then |
set_ip0 <= '1'; |
dataval <= data_in; |
end if; |
end if; |
end case; |
|
when PROCESS_ARP => |
next_rx_state <= WAIT_END; |
set_rx_state <= '1'; |
arp_oper_set_val <= NOP; |
set_arp_oper <= '1'; |
case arp_operation is |
when NOP => -- (nothing to do) |
when REQUEST => |
count_arp_rcvd <= '1'; |
recv_who_has <= '1'; |
arp_entry_for_who_has <= new_arp_entry; |
-- setting I_Have as well allows us to cache the remote node's entry immediately |
recv_I_have <= '1'; |
arp_entry_for_I_have <= new_arp_entry; |
when REPLY => |
count_arp_rcvd <= '1'; |
recv_I_have <= '1'; |
arp_entry_for_I_have <= new_arp_entry; |
end case; |
|
when WAIT_END => |
case rx_event is |
when NO_EVENT => -- (nothing to do) |
when DATA => |
if data_in_last = '1' then |
next_rx_state <= IDLE; |
set_rx_state <= '1'; |
end if; |
end case; |
|
end case; |
|
end process; |
|
rx_sequential : process (rx_clk) |
begin |
if rising_edge(rx_clk) then |
if reset = '1' then |
-- reset state variables |
rx_state <= IDLE; |
rx_count <= x"00"; |
arp_operation <= NOP; |
arp_req_count <= x"00"; |
arp_err_data <= (others => '0'); |
else |
-- Next rx_state processing |
if set_rx_state = '1' then |
rx_state <= next_rx_state; |
else |
rx_state <= rx_state; |
end if; |
|
-- rx_count processing |
case rx_count_mode is |
when RST => |
rx_count <= x"00"; |
when INCR => |
rx_count <= rx_count + 1; |
when HOLD => |
rx_count <= rx_count; |
end case; |
|
-- err data |
if set_err_data = '1' then |
arp_err_data <= data_in; |
else |
arp_err_data <= arp_err_data; |
end if; |
|
-- arp operation processing |
if set_arp_oper = '1' then |
arp_operation <= arp_oper_set_val; |
else |
arp_operation <= arp_operation; |
end if; |
|
-- source mac capture |
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if; |
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if; |
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if; |
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if; |
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if; |
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if; |
|
-- source ip capture |
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if; |
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if; |
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if; |
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if; |
|
-- set arp entry request |
if count_arp_rcvd = '1' then |
-- count another ARP pkt received |
arp_req_count <= arp_req_count + 1; |
else |
arp_req_count <= arp_req_count; |
end if; |
|
end if; |
end if; |
end process; |
|
end Behavioral; |
|
/udp_ip_stack/trunk/rtl/vhdl/UDP_Complete_nomac.vhd
29,7 → 29,9
entity UDP_Complete_nomac is |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- UDP TX signals |
67,6 → 69,9
end UDP_Complete_nomac; |
|
|
|
|
|
architecture structural of UDP_Complete_nomac is |
|
------------------------------------------------------------------------------ |
116,7 → 121,9
component IP_complete_nomac |
generic ( |
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr |
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s) |
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s) |
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error |
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store |
); |
Port ( |
-- IP Layer signals |
203,7 → 210,9
IP_block : IP_complete_nomac |
generic map ( |
CLOCK_FREQ => CLOCK_FREQ, |
ARP_TIMEOUT => ARP_TIMEOUT |
ARP_TIMEOUT => ARP_TIMEOUT, |
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO, |
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES |
) |
PORT MAP ( |
-- IP interface |
239,3 → 248,4
|
end structural; |
|
|
/udp_ip_stack/trunk/rtl/vhdl/IPv4_TX.vhd
366,7 → 366,8
if mac_data_out_ready = '1' then |
if ip_tx.data.data_out_valid = '1' or tx_count = x"000" then |
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast |
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then |
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then |
-- TX terminated due to count - end normally |
set_last <= '1'; |
set_chn_reqd <= CLR; |
tx_data <= ip_tx.data.data_out; |
374,7 → 375,17
set_tx_result <= '1'; |
next_tx_state <= IDLE; |
set_tx_state <= '1'; |
elsif ip_tx.data.data_out_last = '1' then |
-- TX terminated due to receiving last indication from upstream - end with error |
set_last <= '1'; |
set_chn_reqd <= CLR; |
tx_data <= ip_tx.data.data_out; |
next_tx_result <= IPTX_RESULT_ERR; |
set_tx_result <= '1'; |
next_tx_state <= IDLE; |
set_tx_state <= '1'; |
else |
-- TX continues |
tx_count_mode <= INCR; |
tx_data <= ip_tx.data.data_out; |
end if; |
/udp_ip_stack/trunk/rtl/vhdl/arp_TX.vhd
0,0 → 1,336
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Peter Fall |
-- |
-- Create Date: 12:00:04 05/31/2011 |
-- Design Name: |
-- Module Name: arp_tx - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- handle transmission of an ARP packet. |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created - refactored this arp_tx module from the complete arp v0.02 module |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.NUMERIC_STD.ALL; |
use work.arp_types.all; |
|
entity arp_tx is |
Port ( |
-- control signals |
send_I_have : in std_logic; -- pulse will be latched |
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched) |
send_who_has : in std_logic; -- pulse will be latched |
ip_entry : in STD_LOGIC_VECTOR (31 downto 0); -- IP target for who_has req (will be latched) |
-- MAC layer TX signals |
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx) |
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted |
data_out_ready : in std_logic; -- indicates system ready to consume data |
data_out_valid : out std_logic; -- indicates data out is valid |
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame |
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame |
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame) |
-- system signals |
our_mac_address : in STD_LOGIC_VECTOR (47 downto 0); |
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0); |
tx_clk : in std_logic; |
reset : in std_logic |
); |
end arp_tx; |
|
architecture Behavioral of arp_tx is |
|
type count_mode_t is (RST,INCR,HOLD); |
type set_clr_t is (SET, CLR, HOLD); |
type tx_state_t is (IDLE,WAIT_MAC,SEND); |
type tx_mode_t is (REPLY,REQUEST); |
|
-- state variables |
signal tx_mac_chn_reqd : std_logic; |
signal tx_state : tx_state_t; |
signal tx_count : unsigned (7 downto 0); |
signal send_I_have_reg : std_logic; |
signal send_who_has_reg : std_logic; |
signal I_have_target : arp_entry_t; -- latched target for "I have" request |
signal who_has_target : std_logic_vector (31 downto 0); -- latched IP for "who has" request |
signal tx_mode : tx_mode_t; -- what sort of tx to make |
signal target : arp_entry_t; -- target to send to |
|
-- busses |
signal next_tx_state : tx_state_t; |
signal tx_mode_val : tx_mode_t; |
signal target_val : arp_entry_t; |
|
-- tx control signals |
signal set_tx_state : std_logic; |
signal tx_count_mode : count_mode_t; |
signal set_chn_reqd : set_clr_t; |
signal kill_data_out_valid : std_logic; |
signal set_send_I_have : set_clr_t; |
signal set_send_who_has : set_clr_t; |
signal set_tx_mode : std_logic; |
signal set_target : std_logic; |
|
begin |
|
tx_combinatorial : process ( |
-- input signals |
send_I_have, send_who_has, arp_entry, ip_entry, data_out_ready, mac_tx_granted, |
our_mac_address, our_ip_address, reset, |
-- state variables |
tx_state, tx_count, tx_mac_chn_reqd, I_have_target, who_has_target, |
send_I_have_reg, send_who_has_reg, tx_mode, target, |
-- busses |
next_tx_state, tx_mode_val, target_val, |
-- control signals |
tx_count_mode, kill_data_out_valid, set_send_I_have, set_send_who_has, |
set_chn_reqd, set_tx_mode, set_target |
) |
begin |
-- set output followers |
mac_tx_req <= tx_mac_chn_reqd; |
|
-- set combinatorial output defaults |
data_out_first <= '0'; |
|
case tx_state is |
when SEND => |
if data_out_ready = '1' and kill_data_out_valid = '0' then |
data_out_valid <= '1'; |
else |
data_out_valid <= '0'; |
end if; |
when OTHERS => data_out_valid <= '0'; |
end case; |
|
-- set bus defaults |
next_tx_state <= IDLE; |
tx_mode_val <= REPLY; |
target_val.ip <= (others => '0'); |
target_val.mac <= (others => '0'); |
|
-- set signal defaults |
set_tx_state <= '0'; |
tx_count_mode <= HOLD; |
data_out <= x"00"; |
data_out_last <= '0'; |
set_chn_reqd <= HOLD; |
kill_data_out_valid <= '0'; |
set_send_I_have <= HOLD; |
set_send_who_has <= HOLD; |
set_tx_mode <= '0'; |
set_target <= '0'; |
|
-- process requests in regardless of FSM state |
if send_I_have = '1' then |
set_send_I_have <= SET; |
end if; |
if send_who_has = '1' then |
set_send_who_has <= SET; |
end if; |
|
-- TX FSM |
case tx_state is |
when IDLE => |
tx_count_mode <= RST; |
if send_I_have_reg = '1' then |
set_chn_reqd <= SET; |
tx_mode_val <= REPLY; |
set_tx_mode <= '1'; |
target_val <= I_have_target; |
set_target <= '1'; |
set_send_I_have <= CLR; |
next_tx_state <= WAIT_MAC; |
set_tx_state <= '1'; |
elsif send_who_has_reg = '1' then |
set_chn_reqd <= SET; |
tx_mode_val <= REQUEST; |
set_tx_mode <= '1'; |
target_val.ip <= who_has_target; |
target_val.mac <= (others => '0'); |
set_target <= '1'; |
set_send_who_has <= CLR; |
next_tx_state <= WAIT_MAC; |
set_tx_state <= '1'; |
else |
set_chn_reqd <= CLR; |
end if; |
|
when WAIT_MAC => |
tx_count_mode <= RST; |
if mac_tx_granted = '1' then |
next_tx_state <= SEND; |
set_tx_state <= '1'; |
end if; |
-- TODO - should handle timeout here |
|
when SEND => |
if data_out_ready = '1' then |
tx_count_mode <= INCR; |
end if; |
case tx_count is |
when x"00" => |
data_out_first <= data_out_ready; |
data_out <= x"ff"; -- dst = broadcast |
|
when x"01" => data_out <= x"ff"; |
when x"02" => data_out <= x"ff"; |
when x"03" => data_out <= x"ff"; |
when x"04" => data_out <= x"ff"; |
when x"05" => data_out <= x"ff"; |
when x"06" => data_out <= our_mac_address (47 downto 40); -- src = our mac |
when x"07" => data_out <= our_mac_address (39 downto 32); |
when x"08" => data_out <= our_mac_address (31 downto 24); |
when x"09" => data_out <= our_mac_address (23 downto 16); |
when x"0a" => data_out <= our_mac_address (15 downto 8); |
when x"0b" => data_out <= our_mac_address (7 downto 0); |
when x"0c" => data_out <= x"08"; -- pkt type = 0806 : ARP |
when x"0d" => data_out <= x"06"; |
when x"0e" => data_out <= x"00"; -- HW type = 0001 : eth |
when x"0f" => data_out <= x"01"; |
when x"10" => data_out <= x"08"; -- protocol = 0800 : ip |
when x"11" => data_out <= x"00"; |
when x"12" => data_out <= x"06"; -- HW size = 06 |
when x"13" => data_out <= x"04"; -- prot size = 04 |
|
when x"14" => data_out <= x"00"; -- opcode = |
when x"15" => |
if tx_mode = REPLY then |
data_out <= x"02"; -- 02 : REPLY |
else |
data_out <= x"01"; -- 01 : REQ |
end if; |
|
when x"16" => data_out <= our_mac_address (47 downto 40); -- sender mac |
when x"17" => data_out <= our_mac_address (39 downto 32); |
when x"18" => data_out <= our_mac_address (31 downto 24); |
when x"19" => data_out <= our_mac_address (23 downto 16); |
when x"1a" => data_out <= our_mac_address (15 downto 8); |
when x"1b" => data_out <= our_mac_address (7 downto 0); |
when x"1c" => data_out <= our_ip_address (31 downto 24); -- sender ip |
when x"1d" => data_out <= our_ip_address (23 downto 16); |
when x"1e" => data_out <= our_ip_address (15 downto 8); |
when x"1f" => data_out <= our_ip_address (7 downto 0); |
when x"20" => data_out <= target.mac (47 downto 40); -- target mac |
when x"21" => data_out <= target.mac (39 downto 32); |
when x"22" => data_out <= target.mac (31 downto 24); |
when x"23" => data_out <= target.mac (23 downto 16); |
when x"24" => data_out <= target.mac (15 downto 8); |
when x"25" => data_out <= target.mac (7 downto 0); |
when x"26" => data_out <= target.ip (31 downto 24); -- target ip |
when x"27" => data_out <= target.ip (23 downto 16); |
when x"28" => data_out <= target.ip (15 downto 8); |
|
when x"29" => |
data_out <= target.ip(7 downto 0); |
data_out_last <= '1'; |
|
when x"2a" => |
kill_data_out_valid <= '1'; -- data is no longer valid |
next_tx_state <= IDLE; |
set_tx_state <= '1'; |
|
when others => |
next_tx_state <= IDLE; |
set_tx_state <= '1'; |
end case; |
end case; |
end process; |
|
tx_sequential : process (tx_clk) |
begin |
if rising_edge(tx_clk) then |
if reset = '1' then |
-- reset state variables |
tx_state <= IDLE; |
tx_count <= (others => '0'); |
tx_mac_chn_reqd <= '0'; |
send_I_have_reg <= '0'; |
send_who_has_reg <= '0'; |
who_has_target <= (others => '0'); |
I_have_target.ip <= (others => '0'); |
I_have_target.mac <= (others => '0'); |
target.ip <= (others => '0'); |
target.mac <= (others => '0'); |
|
else |
-- normal (non reset) processing |
|
-- Next tx_state processing |
if set_tx_state = '1' then |
tx_state <= next_tx_state; |
else |
tx_state <= tx_state; |
end if; |
|
-- input request latching |
case set_send_I_have is |
when SET => |
send_I_have_reg <= '1'; |
I_have_target <= arp_entry; |
when CLR => |
send_I_have_reg <= '0'; |
I_have_target <= I_have_target; |
when HOLD => |
send_I_have_reg <= send_I_have_reg; |
I_have_target <= I_have_target; |
end case; |
|
case set_send_who_has is |
when SET => |
send_who_has_reg <= '1'; |
who_has_target <= ip_entry; |
when CLR => |
send_who_has_reg <= '0'; |
who_has_target <= who_has_target; |
when HOLD => |
send_who_has_reg <= send_who_has_reg; |
who_has_target <= who_has_target; |
end case; |
|
-- tx mode |
if set_tx_mode = '1' then |
tx_mode <= tx_mode_val; |
else |
tx_mode <= tx_mode; |
end if; |
|
-- target latching |
if set_target = '1' then |
target <= target_val; |
else |
target <= target; |
end if; |
|
-- tx_count processing |
case tx_count_mode is |
when RST => |
tx_count <= x"00"; |
when INCR => |
tx_count <= tx_count + 1; |
when HOLD => |
tx_count <= tx_count; |
end case; |
|
-- control access request to mac tx chn |
case set_chn_reqd is |
when SET => tx_mac_chn_reqd <= '1'; |
when CLR => tx_mac_chn_reqd <= '0'; |
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd; |
end case; |
|
end if; |
end if; |
end process; |
|
|
end Behavioral; |
|
/udp_ip_stack/trunk/doc/src/UDP_IP_Stack.pptx
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/udp_ip_stack/trunk/doc/UDP_IP_Stack.pdf
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