OpenCores
URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /udp_ip_stack/trunk/rtl/vhdl/ml605
    from Rev 8 to Rev 10
    ↔ Reverse comparison
  •

Rev 8 → Rev 10

/IP_complete.vhd
27,7 → 27,9
entity IP_complete is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
73,7 → 75,9
COMPONENT IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
111,7 → 115,7
------------------------------------------------------------------------------
-- Component Declaration for the MAC layer
------------------------------------------------------------------------------
component mac_layer
component mac_layer_v2_1
port (
-- System controls
------------------
184,8 → 188,10
IP_layer : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT
)
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
PORT MAP (
-- IP Layer signals
ip_tx_start => ip_tx_start,
221,7 → 227,7
------------------------------------------------------------------------------
-- Instantiate the MAC layer
------------------------------------------------------------------------------
mac_block : mac_layer
mac_block : mac_layer_v2_1
Port map(
-- System controls
------------------
/UDP_Complete.vhd
28,7 → 28,9
entity UDP_Complete is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
68,6 → 70,9
);
end UDP_Complete;
 
 
 
 
architecture structural of UDP_Complete is
 
------------------------------------------------------------------------------
77,7 → 82,9
COMPONENT UDP_Complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
118,7 → 125,8
------------------------------------------------------------------------------
-- Component Declaration for the MAC layer
------------------------------------------------------------------------------
component mac_layer
component mac_v2_2
-- component xv6mac_straight
port (
-- System controls
------------------
196,11 → 204,13
------------------------------------------------------------------------------
 
udp_block: UDP_Complete_nomac
generic map (
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
PORT MAP (
PORT MAP (
-- UDP TX signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
238,7 → 248,8
------------------------------------------------------------------------------
-- Instantiate the MAC layer
------------------------------------------------------------------------------
mac_block : mac_layer
mac_block : mac_v2_2
-- mac_block : xv6mac_straight
Port map(
-- System controls
------------------
282,3 → 293,4
 
end structural;
 
 
/UDP_integration_example.vhd
35,6 → 35,8
-- System controls
------------------
PBTX : in std_logic;
PB_DO_SECOND_TX : in std_logic;
DO_SECOND_TX_LED : out std_logic;
UDP_RX : out std_logic;
UDP_Start : out std_logic;
PBTX_LED : out std_logic;
64,13 → 66,16
 
architecture Behavioral of UDP_integration_example is
 
 
------------------------------------------------------------------------------
-- Component Declaration for the complete IP layer
-- Component Declaration for the complete UDP layer
------------------------------------------------------------------------------
component UDP_Complete
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
110,10 → 115,13
);
end component;
 
-- for UDP_block : UDP_Complete use configuration work.UDP_Complete.udpc_multi_slot_arp;
 
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT);
 
type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR);
type count_mode_type is (RST, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD);
 
-- system signals
signal clk_int : std_logic;
136,7 → 144,9
signal tx_start_reg : std_logic;
signal tx_started_reg : std_logic;
signal tx_fin_reg : std_logic;
signal prime_second_tx : std_logic; -- if want to do a 2nd tx after the first
signal do_second_tx : std_logic; -- if need to do a 2nd tx as next tx
-- control signals
signal next_state : state_type;
signal set_state : std_logic;
148,6 → 158,7
signal set_tx_fin : set_clr_type;
signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
signal control_int : udp_control_type;
signal set_second_tx : sec_tx_ctrl_type;
 
begin
 
154,11 → 165,12
process (
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
reset, tx_started_reg, tx_fin_reg, tx_start_reg
reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx,
PB_DO_SECOND_TX, do_second_tx
)
begin
-- set up our local addresses and default controls
our_ip <= x"c0a80509"; -- 192.168.5.9
our_ip <= x"c0a80019"; -- 192.168.0.25
our_mac <= x"002320212223";
control_int.ip_controls.arp_controls.clear_cache <= '0';
174,6 → 186,7
TX_Completed <= tx_fin_reg;
TX_RSLT_0 <= udp_tx_result_int(0);
TX_RSLT_1 <= udp_tx_result_int(1);
DO_SECOND_TX_LED <= prime_second_tx;
-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
183,6 → 196,9
when IDLE => display (3 downto 0) <= "0001";
when WAIT_RX_DONE => display (3 downto 0) <= "0010";
when DATA_OUT => display (3 downto 0) <= "0011";
when PAUSE => display (3 downto 0) <= "0100";
when CHECK_SECOND_TX => display (3 downto 0) <= "0101";
when SET_SEC_HDR => display (3 downto 0) <= "0110";
end case;
 
end process;
193,12 → 209,12
tx_proc_combinatorial: process(
-- inputs
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
udp_tx_int.data.data_out_valid, PBTX,
udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX,
-- state
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx,
-- controls
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
set_tx_started, set_tx_fin, first_byte_rx
set_tx_started, set_tx_fin, first_byte_rx, set_second_tx
)
begin
-- set output_followers
218,7 → 234,12
first_byte_rx <= (others => '0');
udp_tx_int.data.data_out <= (others => '0');
udp_tx_int.data.data_out_valid <= '0';
set_second_tx <= HOLD;
if PB_DO_SECOND_TX = '1' then
set_second_tx <= PRIME;
end if;
-- FSM
case state is
259,6 → 280,7
set_tx_start <= CLR;
set_tx_fin <= SET;
set_tx_started <= CLR;
set_second_tx <= CLR;
next_state <= IDLE;
set_state <= '1';
else
276,7 → 298,7
set_last <= '1';
set_tx_fin <= SET;
set_tx_started <= CLR;
next_state <= IDLE;
next_state <= PAUSE;
set_state <= '1';
else
set_count <= INCR;
283,7 → 305,30
end if;
end if;
end if;
 
when PAUSE =>
next_state <= CHECK_SECOND_TX;
set_state <= '1';
 
 
when CHECK_SECOND_TX =>
if prime_second_tx = '1' then
set_second_tx <= DO;
next_state <= SET_SEC_HDR;
set_state <= '1';
else
set_second_tx <= CLR;
next_state <= IDLE;
set_state <= '1';
end if;
when SET_SEC_HDR =>
set_hdr <= '1';
set_tx_started <= SET;
set_tx_start <= SET;
next_state <= DATA_OUT;
set_state <= '1';
end case;
end process;
 
306,6 → 351,8
tx_started_reg <= '0';
tx_fin_reg <= '0';
PBTX_LED <= '0';
do_second_tx <= '0';
prime_second_tx <= '0';
else
PBTX_LED <= PBTX;
325,11 → 372,21
-- set tx hdr
if set_hdr = '1' then
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
if first_byte_rx = x"42" then
-- select the dst addr of the tx:
-- if do_second_tx, to solaris box
-- otherwise control according to first byte of received data:
-- B = broadcast
-- C = to dummy address to test timeout
-- D to solaris box
-- otherwise, direct to sender
if do_second_tx = '1' then
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
elsif first_byte_rx = x"42" then
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr
elsif first_byte_rx = x"43" then
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout
elsif first_byte_rx = x"44" then
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
else
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender
end if;
361,8 → 418,22
when CLR => tx_fin_reg <= '0';
when HOLD => tx_fin_reg <= tx_fin_reg;
end case;
 
-- set do_second_tx
case set_second_tx is
when PRIME =>
prime_second_tx <= '1';
when DO =>
prime_second_tx <= '0';
do_second_tx <= '1';
when CLR =>
prime_second_tx <= '0';
do_second_tx <= '0';
when HOLD =>
prime_second_tx <= prime_second_tx;
do_second_tx <= do_second_tx;
end case;
end if;
end if;
 
375,7 → 446,7
------------------------------------------------------------------------------
UDP_block : UDP_Complete
generic map (
ARP_TIMEOUT => 30 -- timeout in seconds
ARP_TIMEOUT => 10 -- timeout in seconds
)
PORT MAP (
-- UDP interface
/xv6mac_straight.vhd
0,0 → 1,463
--------------------------------------------------------------------------------
-- Project : low latency UDP
-- File : xv6mac_straight
-- Version : 0.0
-------------------------------------------------------------------------------
--
--
-- Description: This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs
--
--
--
-- ---------------------------------------------------------------------
-- | EXAMPLE DESIGN WRAPPER |
-- | --------------------------------------------------------|
-- | |FIFO BLOCK WRAPPER |
-- | | |
-- | | |
-- | | -----------------------------------------|
-- | | | BLOCK LEVEL WRAPPER |
-- | | | --------------------- |
-- | | | | V6 EMAC CORE | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | | | | | | | --------- |
-- | | |->|->----------->|--|--->| Tx Tx |--| |--->|
-- | | | | | | AXI-S PHY | | | |
-- | | | | | | I/F I/F | | | |
-- | | | | | | | | PHY | |
-- | | | | | | | | I/F | |
-- | | | | | | | | | |
-- | | | | | | Rx Rx | | | |
-- | | | | | | AX)-S PHY | | | |
-- | | |<-|<-------------|----| I/F I/F |<-| |<---|
-- | | | | | | | --------- |
-- | -------- | | --------------------- |
-- | | | |
-- | | -----------------------------------------|
-- | --------------------------------------------------------|
-- ---------------------------------------------------------------------
--
--------------------------------------------------------------------------------
 
library unisim;
use unisim.vcomponents.all;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity xv6mac_straight is
port (
-- System controls
------------------
glbl_rst : in std_logic; -- asynchronous reset
mac_reset : in std_logic; -- reset mac layer
clk_in_p : in std_logic; -- 200MHz clock input from board
clk_in_n : in std_logic;
-- MAC Transmitter (AXI-S) Interface
---------------------------------------------
mac_tx_clock : out std_logic; -- data sampled on rising edge
mac_tx_tdata : in std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : in std_logic; -- tdata is valid
mac_tx_tready : out std_logic; -- mac is ready to accept data
mac_tx_tlast : in std_logic; -- indicates last byte of frame
 
-- MAC Receiver (AXI-S) Interface
------------------------------------------
mac_rx_clock : out std_logic; -- data valid on rising edge
mac_rx_tdata : out std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : out std_logic; -- indicates tdata is valid
mac_rx_tready : in std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : out std_logic; -- indicates last byte of the trame
-- GMII Interface
-----------------
phy_resetn : out std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
mii_tx_clk : in std_logic
);
end xv6mac_straight;
 
architecture wrapper of xv6mac_straight is
 
------------------------------------------------------------------------------
-- Component declaration for the internal mac layer
------------------------------------------------------------------------------
component mac_layer_v2_2_block
port(
gtx_clk : in std_logic;
 
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
 
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
 
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
 
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
tx_collision : out std_logic;
tx_retransmit : out std_logic;
 
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
 
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
 
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
 
-- asynchronous reset
-----------------
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic
 
);
end component;
 
 
------------------------------------------------------------------------------
-- Component Declaration for the Clock generator
------------------------------------------------------------------------------
 
component clk_wiz_v2_2
port (
-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
 
 
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component reset_sync_v2_2
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
 
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component sync_block_v2_2
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
 
------------------------------------------------------------------------------
-- Constants used in this top level wrapper.
------------------------------------------------------------------------------
constant BOARD_PHY_ADDR : std_logic_vector(7 downto 0) := "00000111";
 
 
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
 
-- example design clocks
signal gtx_clk_bufg : std_logic;
signal refclk_bufg : std_logic;
signal rx_mac_aclk : std_logic;
-- tx handshaking
signal mac_tx_tready_int : std_logic;
signal tx_full_reg : std_logic;
signal tx_full_val : std_logic;
signal tx_data_reg : std_logic_vector(7 downto 0);
signal tx_last_reg : std_logic;
signal set_tx_reg : std_logic;
signal phy_resetn_int : std_logic;
 
-- resets (and reset generation)
signal local_chk_reset : std_logic;
signal chk_reset_int : std_logic;
signal chk_pre_resetn : std_logic := '0';
signal chk_resetn : std_logic := '0';
signal dcm_locked : std_logic;
 
signal glbl_rst_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0);
signal glbl_rst_intn : std_logic;
 
-- pipeline register for RX signals
signal rx_data_val : std_logic_vector(7 downto 0);
signal rx_tvalid_val : std_logic;
signal rx_tlast_val : std_logic;
signal rx_data_reg : std_logic_vector(7 downto 0);
signal rx_tvalid_reg : std_logic;
signal rx_tlast_reg : std_logic;
 
attribute keep : string;
attribute keep of gtx_clk_bufg : signal is "true";
attribute keep of refclk_bufg : signal is "true";
attribute keep of mac_tx_tready_int : signal is "true";
attribute keep of tx_full_reg : signal is "true";
 
 
------------------------------------------------------------------------------
-- Begin architecture
------------------------------------------------------------------------------
 
begin
 
combinatorial: process (
rx_data_reg, rx_tvalid_reg, rx_tlast_reg,
mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg
)
begin
-- output followers
mac_rx_tdata <= rx_data_reg;
mac_rx_tvalid <= rx_tvalid_reg;
mac_rx_tlast <= rx_tlast_reg;
mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int); -- if not full, we are ready to accept
 
-- control defaults
tx_full_val <= tx_full_reg;
set_tx_reg <= '0';
-- tx handshaking logic
if mac_tx_tvalid = '1' then
tx_full_val <= '1';
set_tx_reg <= '1';
elsif mac_tx_tready_int = '1' then
tx_full_val <= '0';
end if;
end process;
 
sequential: process(gtx_clk_bufg)
begin
if rising_edge(gtx_clk_bufg) then
if chk_resetn = '0' then
-- reset state variables
rx_data_reg <= (others => '0');
rx_tvalid_reg <= '0';
rx_tlast_reg <= '0';
tx_full_reg <= '0';
tx_data_reg <= (others => '0');
tx_last_reg <= '0';
else
-- register rx data
rx_data_reg <= rx_data_val;
rx_tvalid_reg <= rx_tvalid_val;
rx_tlast_reg <= rx_tlast_val;
-- process tx tvalid and tready
tx_full_reg <= tx_full_val;
if set_tx_reg = '1' then
tx_data_reg <= mac_tx_tdata;
tx_last_reg <= mac_tx_tlast;
else
tx_data_reg <= tx_data_reg;
tx_last_reg <= tx_last_reg;
end if;
end if;
end if;
end process;
 
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode EMAC Block wrapper
------------------------------------------------------------------------------
v6emac_block : mac_layer_v2_2_block
port map(
gtx_clk => gtx_clk_bufg,
 
-- Client Receiver Interface
rx_statistics_vector => open,
rx_statistics_valid => open,
 
rx_mac_aclk => open,
rx_reset => open,
rx_axis_mac_tdata => rx_data_val,
rx_axis_mac_tvalid => rx_tvalid_val,
rx_axis_mac_tlast => rx_tlast_val,
rx_axis_mac_tuser => open,
 
-- Client Transmitter Interface
tx_ifg_delay => x"00",
tx_statistics_vector => open,
tx_statistics_valid => open,
 
tx_reset => open,
tx_axis_mac_tdata => tx_data_reg,
tx_axis_mac_tvalid => tx_full_reg,
tx_axis_mac_tlast => tx_last_reg,
tx_axis_mac_tuser => '0',
tx_axis_mac_tready => mac_tx_tready_int,
tx_collision => open,
tx_retransmit => open,
 
-- Flow Control
pause_req => '0',
pause_val => x"0000",
 
-- Reference clock for IDELAYCTRL's
refclk => refclk_bufg,
 
-- GMII Interface
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
 
-- asynchronous reset
glbl_rstn => chk_resetn,
rx_axi_rstn => '1',
tx_axi_rstn => '1'
);
 
 
 
------------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
------------------------------------------------------------------------------
clock_generator : clk_wiz_v2_2
port map (
-- Clock in ports
CLK_IN1_P => clk_in_p,
CLK_IN1_N => clk_in_n,
-- Clock out ports
CLK_OUT1 => gtx_clk_bufg,
CLK_OUT2 => open,
CLK_OUT3 => refclk_bufg,
-- Status and control signals
RESET => glbl_rst,
LOCKED => dcm_locked
);
 
-----------------
-- global reset
glbl_reset_gen : reset_sync_v2_2
port map (
clk => gtx_clk_bufg,
enable => dcm_locked,
reset_in => glbl_rst,
reset_out => glbl_rst_int
);
 
glbl_rst_intn <= not glbl_rst_int;
 
-- generate the user side clocks
mac_tx_clock <= gtx_clk_bufg;
mac_rx_clock <= gtx_clk_bufg;
 
------------------------------------------------------------------------------
-- Generate resets
------------------------------------------------------------------------------
-- in each case the async reset is first captured and then synchronised
 
 
local_chk_reset <= glbl_rst or mac_reset;
 
-----------------
-- data check reset
chk_reset_gen : reset_sync_v2_2
port map (
clk => gtx_clk_bufg,
enable => dcm_locked,
reset_in => local_chk_reset,
reset_out => chk_reset_int
);
 
-- Create fully synchronous reset in the gtx clock domain.
gen_chk_reset : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
if chk_reset_int = '1' then
chk_pre_resetn <= '0';
chk_resetn <= '0';
else
chk_pre_resetn <= '1';
chk_resetn <= chk_pre_resetn;
end if;
end if;
end process gen_chk_reset;
 
 
-----------------
-- PHY reset
-- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
-- this is derived using the 125MHz available and a 6 bit counter
gen_phy_reset : process (gtx_clk_bufg)
begin
if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
if glbl_rst_intn = '0' then
phy_resetn_int <= '0';
phy_reset_count <= (others => '0');
else
if phy_reset_count /= "111111" then
phy_reset_count <= phy_reset_count + "000001";
else
phy_resetn_int <= '1';
end if;
end if;
end if;
end process gen_phy_reset;
 
phy_resetn <= phy_resetn_int;
 
 
end wrapper;
/udp_constraints.ucf
20,17 → 20,18
NET "display[6]" LOC = AE24;
NET "display[7]" LOC = AD24;
 
NET PBTX_LED LOC = AD21;
NET UDP_RX LOC = AH27;
NET UDP_START LOC = AH28;
NET TX_RSLT_0 LOC = AE21;
NET TX_RSLT_1 LOC = AP24;
NET PBTX_LED LOC = AD21;
NET UDP_RX LOC = AH27;
NET DO_SECOND_TX_LED LOC = AH28;
NET TX_RSLT_0 LOC = AE21;
NET TX_RSLT_1 LOC = AP24;
 
 
 
#### Module Push_Buttons_4Bit constraints
NET PBTX LOC = H17;
NET reset_leds LOC = G26;
NET PBTX LOC = H17;
NET PB_DO_SECOND_TX LOC = A18;
NET reset_leds LOC = G26;
 
#### Module DIP_Switches_4Bit constraints
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.