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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 127 to Rev 126
    Reverse comparison

Rev 127 → Rev 126

/versatile_library/trunk/rtl/verilog/versatile_library.v
6162,7 → 6162,7
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==dw_m/4) ? aw_s-2 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
2863,7 → 2863,7
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==dw_m/4) ? aw_s-2 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;
/versatile_library/trunk/rtl/verilog/wb.v
1244,7 → 1244,7
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==dw_m/4) ? aw_s-2 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2968,7 → 2968,7
(dw_s==dw_m*16) ? aw_s+4 :
(dw_s==dw_m*32) ? aw_s+5 :
(dw_s==dw_m/2) ? aw_s-1 :
(dw_s==dw_m/4) ? aw_s-2 :
(dw_s==adw_m/4) ? aw_s-2 :
(dw_s==dw_m/8) ? aw_s-3 :
(dw_s==dw_m/16) ? aw_s-4 :
(dw_s==dw_m/32) ? aw_s-5 : 0;

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