OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 137 to Rev 136
    ↔ Reverse comparison
  •

Rev 137 → Rev 136

/versatile_library/trunk/rtl/verilog/versatile_library.v
4471,7 → 4471,7
.d_b({d_b,d_b}),
.q_b(temp),
.adr_b(adr_b[b_addr_width-1:1]),
.be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
.we_b(we_b),
.clk_b(clk_b)
);
6344,8 → 6344,7
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
//wire [aw_slot-1:0] wbm_adr;
wire [aw_m-1:0] wbm_adr;
wire [aw_slot-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
 
reg [2:0] phase;
6550,7 → 6549,7
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
 
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1873,7 → 1873,7
.d_b({d_b,d_b}),
.q_b(temp),
.adr_b(adr_b[b_addr_width-1:1]),
.be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
.we_b(we_b),
.clk_b(clk_b)
);
3064,8 → 3064,7
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
//wire [aw_slot-1:0] wbm_adr;
wire [aw_m-1:0] wbm_adr;
wire [aw_slot-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
reg [2:0] phase;
// phase = {we,stb,cyc}
3237,7 → 3236,7
endgenerate
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
/versatile_library/trunk/rtl/verilog/wb.v
1317,8 → 1317,7
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
//wire [aw_slot-1:0] wbm_adr;
wire [aw_m-1:0] wbm_adr;
wire [aw_slot-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
 
reg [2:0] phase;
1523,7 → 1522,7
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
 
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
1968,7 → 1968,7
.d_b({d_b,d_b}),
.q_b(temp),
.adr_b(adr_b[b_addr_width-1:1]),
.be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
.we_b(we_b),
.clk_b(clk_b)
);
3157,8 → 3157,7
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
//wire [aw_slot-1:0] wbm_adr;
wire [aw_m-1:0] wbm_adr;
wire [aw_slot-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
reg [2:0] phase;
// phase = {we,stb,cyc}
3330,7 → 3329,7
endgenerate
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
/versatile_library/trunk/rtl/verilog/memories.v
599,7 → 599,7
.d_b({d_b,d_b}),
.q_b(temp),
.adr_b(adr_b[b_addr_width-1:1]),
.be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
.we_b(we_b),
.clk_b(clk_b)
);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.