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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 149 to Rev 150
    Reverse comparison

Rev 149 → Rev 150

/versatile_library/trunk/rtl/verilog/versatile_library.v
7458,7 → 7458,7
case (opcode)
opcode_sll: dout = din << s;
opcode_srl: dout = din >> s;
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}}));
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}));
//opcode_ror: dout = not yet implemented
default: dout = din << s;
endcase
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
5181,7 → 5181,7
case (opcode)
opcode_sll: dout = din << s;
opcode_srl: dout = din >> s;
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}}));
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}));
//opcode_ror: dout = not yet implemented
default: dout = din << s;
endcase
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
5276,7 → 5276,7
case (opcode)
opcode_sll: dout = din << s;
opcode_srl: dout = din >> s;
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}}));
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}));
//opcode_ror: dout = not yet implemented
default: dout = din << s;
endcase
/versatile_library/trunk/rtl/verilog/arith.v
199,7 → 199,7
case (opcode)
opcode_sll: dout = din << s;
opcode_srl: dout = din >> s;
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}}));
opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}));
//opcode_ror: dout = not yet implemented
default: dout = din << s;
endcase

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