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Rev 18 → Rev 17

/versatile_library/trunk/rtl/verilog/arith.v File deleted
/versatile_library/trunk/rtl/verilog/cnt_gray.csv File deleted
/versatile_library/trunk/rtl/verilog/versatile_library.v
90,7 → 90,7
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
output rst_o;
reg [1:0] tmp;
reg [0:1] tmp;
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
tmp <= 2'b11;
285,7 → 285,7
//// ////
//////////////////////////////////////////////////////////////////////
 
module vl_dff ( d, q, clk, rst);
module dff ( d, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
302,7 → 302,7
 
endmodule
 
module vl_dff_array ( d, q, clk, rst);
module dff_array ( d, q, clk, rst);
 
parameter width = 1;
parameter depth = 2;
327,7 → 327,7
endmodule
 
module vl_dff_ce ( d, ce, q, clk, rst);
module dff_ce ( d, ce, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
345,7 → 345,7
 
endmodule
 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
module dff_ce_clear ( d, ce, clear, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
405,7 → 405,7
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vl_dff_sr (
module dff_sr (
aclr,
aset,
clock,
490,7 → 490,7
`else
 
 
module vl_dff_sr ( aclr, aset, clock, data, q);
module dff_sr ( aclr, aset, clock, data, q);
 
input aclr;
input aset;
513,7 → 513,7
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
`ifdef ALTERA
module vl_latch ( d, le, q, clk);
module latch ( d, le, q, clk);
input d, le;
output q;
input clk;
532,7 → 532,7
endmodule
`endif
 
module vl_shreg ( d, q, clk, rst);
module shreg ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
548,7 → 548,7
assign q = dffs[depth];
endmodule
 
module vl_shreg_ce ( d, ce, q, clk, rst);
module shreg_ce ( d, ce, q, clk, rst);
parameter depth = 10;
input d, ce;
output q;
565,7 → 565,7
assign q = dffs[depth];
endmodule
 
module vl_delay ( d, q, clk, rst);
module delay ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
581,7 → 581,7
assign q = dffs[depth];
endmodule
 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
module delay_emptyflag ( d, q, emptyflag, clk, rst);
parameter depth = 10;
input d;
output q, emptyflag;
599,116 → 599,6
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Logic functions ////
//// ////
//// Description ////
//// Logic functions such as multiplexers ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
 
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
 
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
 
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
750,7 → 640,7
//////////////////////////////////////////////////////////////////////
 
// binary counter
module vl_cnt_bin_ce ( cke, q, rst, clk);
module cnt_bin_ce ( cke, q, rst, clk);
 
parameter length = 4;
input cke;
820,7 → 710,7
//////////////////////////////////////////////////////////////////////
 
// binary counter
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
 
parameter length = 4;
input clear;
891,7 → 781,7
//////////////////////////////////////////////////////////////////////
 
// binary counter
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
 
parameter length = 4;
input clear;
966,7 → 856,7
//////////////////////////////////////////////////////////////////////
 
// binary counter
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
 
parameter length = 4;
input cke;
1048,7 → 938,7
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
module vl_cnt_lfsr_zq ( zq, rst, clk);
module cnt_lfsr_zq ( zq, rst, clk);
 
parameter length = 4;
output reg zq;
1167,7 → 1057,7
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
 
parameter length = 4;
input cke;
1289,7 → 1179,7
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
 
parameter length = 4;
input cke;
1463,7 → 1353,7
//////////////////////////////////////////////////////////////////////
 
// GRAY counter
module vl_cnt_gray ( q, rst, clk);
module cnt_gray ( q, rst, clk);
 
parameter length = 4;
output reg [length:1] q;
1535,7 → 1425,7
//////////////////////////////////////////////////////////////////////
 
// GRAY counter
module vl_cnt_gray_ce ( cke, q, rst, clk);
module cnt_gray_ce ( cke, q, rst, clk);
 
parameter length = 4;
input cke;
1610,7 → 1500,7
//////////////////////////////////////////////////////////////////////
 
// GRAY counter
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
 
parameter length = 4;
input cke;
1687,7 → 1577,7
//// ////
//////////////////////////////////////////////////////////////////////
 
module vl_cnt_shreg_wrap ( q, rst, clk);
module cnt_shreg_wrap ( q, rst, clk);
 
parameter length = 4;
output reg [0:length-1] q;
1702,7 → 1592,7
endmodule
 
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
 
parameter length = 4;
input cke;
1719,7 → 1609,7
endmodule
 
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
 
parameter length = 4;
input cke, clear;
1739,7 → 1629,7
endmodule
 
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
 
parameter length = 4;
input cke, clear;
2088,7 → 1978,7
endcase
 
`ifndef GENERATE_DIRECTION_AS_LATCH
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
2102,8 → 1992,8
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
2119,8 → 2009,8
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
 
endmodule // async_comp
 
2152,11 → 2042,11
q, rd, fifo_empty, rd_clk, rd_rst
);
 
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
2258,19 → 2148,19
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
2336,7 → 2226,7
 
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module vl_wb3wb3_bridge (
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
2412,7 → 2302,7
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
 
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
2479,12 → 2369,12
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
 
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
 
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
2534,50 → 2424,39
endmodule
 
// WB ROM
module vl_wb_boot_rom (
module wb_boot_rom (
wb_adr_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
parameter adr_hi = 31;
parameter adr_lo = 28;
parameter adr_sel = 4'hf;
parameter addr_width = 5;
 
`ifndef BOOT_ROM
`define BOOT_ROM "boot_rom.v"
`endif
parameter addr_width = 5;
input [adr_hi:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output hit_o;
input wb_clk;
input wb_rst;
 
wire hit;
reg [31:0] wb_dat;
reg wb_ack;
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
input [(addr_width+2)-1:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output reg [31:0] wb_dat_o;
output reg wb_ack_o;
input wb_clk;
input wb_rst;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat <= 32'h15000000;
wb_dat_o <= 32'h15000000;
else
case (wb_adr_i[addr_width-1:2])
case (wb_adr_i)
`include `BOOT_ROM
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat <= 32'h18000000;
1 : wb_dat <= 32'hA8200000;
2 : wb_dat <= 32'hA8C00100;
3 : wb_dat <= 32'h44003000;
4 : wb_dat <= 32'h15000000;
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat <= 32'h00000000;
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
 
2584,223 → 2463,8
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack <= 1'b0;
wb_ack_o <= 1'b0;
else
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
 
assign hit_o = hit;
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
 
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Arithmetic functions ////
//// ////
//// Description ////
//// Arithmetic functions for ALU and DSP ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// signed multiplication
module vl_mults (a,b,p);
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_b_width-1:0] b;
output [result_hi:result_lo] p;
wire signed [operand_a_width-1:0] ai;
wire signed [operand_b_width-1:0] bi;
wire signed [operand_a_width+operand_b_width-1:0] result;
 
assign ai = a;
assign bi = b;
assign result = ai * bi;
assign p = result[result_hi:result_lo];
endmodule
 
module vl_mults18x18 (a,b,p);
input [17:0] a,b;
output [35:0] p;
vl_mult
# (.operand_a_width(18), .operand_b_width(18))
mult0 (.a(a), .b(b), .p(p));
endmodule
 
// unsigned multiplication
module vl_mult (a,b,p);
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_b_width-1:0] b;
output [result_hi:result_hi] p;
 
wire [operand_a_width+operand_b_width-1:0] result;
 
assign result = a * b;
assign p = result[result_hi:result_lo];
endmodule
 
// shift unit
// supporting the following shift functions
// SLL
// SRL
// SRA
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
module vl_shift_unit_32( din, s, dout, opcode);
input [31:0] din; // data in operand
input [4:0] s; // shift operand
input [1:0] opcode;
output [31:0] dout;
 
parameter opcode_sll = 2'b00;
//parameter opcode_srl = 2'b01;
parameter opcode_sra = 2'b10;
//parameter opcode_ror = 2'b11;
 
wire sll, sra;
assign sll = opcode == opcode_sll;
assign sra = opcode == opcode_sra;
 
wire [15:1] s1;
wire [3:0] sign;
wire [7:0] tmp [0:3];
 
// first stage is multiplier based
// shift operand as fractional 8.7
assign s1[15] = sll & s[2:0]==3'd7;
assign s1[14] = sll & s[2:0]==3'd6;
assign s1[13] = sll & s[2:0]==3'd5;
assign s1[12] = sll & s[2:0]==3'd4;
assign s1[11] = sll & s[2:0]==3'd3;
assign s1[10] = sll & s[2:0]==3'd2;
assign s1[ 9] = sll & s[2:0]==3'd1;
assign s1[ 8] = s[2:0]==3'd0;
assign s1[ 7] = !sll & s[2:0]==3'd1;
assign s1[ 6] = !sll & s[2:0]==3'd2;
assign s1[ 5] = !sll & s[2:0]==3'd3;
assign s1[ 4] = !sll & s[2:0]==3'd4;
assign s1[ 3] = !sll & s[2:0]==3'd5;
assign s1[ 2] = !sll & s[2:0]==3'd6;
assign s1[ 1] = !sll & s[2:0]==3'd7;
 
assign sign[3] = din[31] & sra;
assign sign[2] = sign[3] & (&din[31:24]);
assign sign[1] = sign[2] & (&din[23:16]);
assign sign[0] = sign[1] & (&din[15:8]);
vl_mults `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
vl_mults `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
vl_mults `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
vl_mults `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
 
// second stage is multiplexer based
// shift on byte level
 
// mux byte 3
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
(sll & s[4:3]==2'b01) ? tmp[2] :
(sll & s[4:3]==2'b10) ? tmp[1] :
(sll & s[4:3]==2'b11) ? tmp[0] :
{8{sign[3]}};
 
// mux byte 2
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
(sll & s[4:3]==2'b01) ? tmp[1] :
(sll & s[4:3]==2'b10) ? tmp[0] :
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
(s[4:3]==2'b01) ? tmp[3] :
{8{sign[3]}};
 
// mux byte 1
assign dout[15:8] = (s[4:3]==2'b00) ? tmp[1] :
(sll & s[4:3]==2'b01) ? tmp[0] :
(sll & s[4:3]==2'b10) ? {8{1'b0}} :
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
(s[4:3]==2'b01) ? tmp[2] :
(s[4:3]==2'b10) ? tmp[3] :
{8{sign[3]}};
 
// mux byte 0
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
(sll) ? {8{1'b0}}:
(s[4:3]==2'b01) ? tmp[1] :
(s[4:3]==2'b10) ? tmp[2] :
tmp[3];
 
endmodule
 
// logic unit
// supporting the following logic functions
// a and b
// a or b
// a xor b
// not b
module vl_logic_unit( a, b, result, opcode);
parameter width = 32;
parameter opcode_and = 2'b00;
parameter opcode_or = 2'b01;
parameter opcode_xor = 2'b10;
input [width-1:0] a,b;
output [width-1:0] result;
input [1:0] opcode;
 
assign result = (opcode==opcode_and) ? a & b :
(opcode==opcode_or) ? a | b :
(opcode==opcode_xor) ? a ^ b :
b;
 
endmodule
 
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
parameter width = 32;
parameter opcode_add = 1'b0;
parameter opcode_sub = 1'b1;
input [width-1:0] a,b;
input c_in, add_sub, sign;
output [width-1:0] result;
output c_out, z, ovfl;
 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
assign z = (result=={width{1'b0}});
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
(~a[width-1] & ~b[width-1] & result[width-1]);
endmodule
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
70,7 → 70,7
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
output rst_o;
reg [1:0] tmp;
reg [0:1] tmp;
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
tmp <= 2'b11;
207,7 → 207,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_dff ( d, q, clk, rst);
module dff ( d, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
219,7 → 219,7
else
q <= d;
endmodule
module vl_dff_array ( d, q, clk, rst);
module dff_array ( d, q, clk, rst);
parameter width = 1;
parameter depth = 2;
parameter reset_value = 1'b0;
239,7 → 239,7
end
assign q = q_tmp[depth-1];
endmodule
module vl_dff_ce ( d, ce, q, clk, rst);
module dff_ce ( d, ce, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
252,7 → 252,7
if (ce)
q <= d;
endmodule
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
module dff_ce_clear ( d, ce, clear, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
268,7 → 268,7
else
q <= d;
endmodule
module vl_dff_sr ( aclr, aset, clock, data, q);
module dff_sr ( aclr, aset, clock, data, q);
input aclr;
input aset;
input clock;
294,7 → 294,7
else
direction <= going_full;*/
endmodule
module vl_shreg ( d, q, clk, rst);
module shreg ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
307,7 → 307,7
dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
module vl_shreg_ce ( d, ce, q, clk, rst);
module shreg_ce ( d, ce, q, clk, rst);
parameter depth = 10;
input d, ce;
output q;
321,7 → 321,7
dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
module vl_delay ( d, q, clk, rst);
module delay ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
334,7 → 334,7
dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
module delay_emptyflag ( d, q, emptyflag, clk, rst);
parameter depth = 10;
input d;
output q, emptyflag;
350,98 → 350,6
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Logic functions ////
//// ////
//// Description ////
//// Logic functions such as multiplexers ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
482,7 → 390,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce ( cke, q, rst, clk);
module cnt_bin_ce ( cke, q, rst, clk);
parameter length = 4;
input cke;
output [length:1] q;
545,7 → 453,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
parameter length = 4;
input clear;
input cke;
609,7 → 517,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
parameter length = 4;
input clear;
input set;
677,7 → 585,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
751,7 → 659,7
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_zq ( zq, rst, clk);
module cnt_lfsr_zq ( zq, rst, clk);
parameter length = 4;
output reg zq;
input rst;
861,7 → 769,7
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
parameter length = 4;
input cke;
output reg zq;
974,7 → 882,7
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
1139,7 → 1047,7
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray ( q, rst, clk);
module cnt_gray ( q, rst, clk);
parameter length = 4;
output reg [length:1] q;
input rst;
1204,7 → 1112,7
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce ( cke, q, rst, clk);
module cnt_gray_ce ( cke, q, rst, clk);
parameter length = 4;
input cke;
output reg [length:1] q;
1272,7 → 1180,7
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
parameter length = 4;
input cke;
output reg [length:1] q;
1341,7 → 1249,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_cnt_shreg_wrap ( q, rst, clk);
module cnt_shreg_wrap ( q, rst, clk);
parameter length = 4;
output reg [0:length-1] q;
input rst;
1352,7 → 1260,7
else
q <= {q[length-1],q[0:length-2]};
endmodule
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
parameter length = 4;
input cke;
output reg [0:length-1] q;
1365,7 → 1273,7
if (cke)
q <= {q[length-1],q[0:length-2]};
endmodule
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
parameter length = 4;
input cke, clear;
output reg [0:length-1] q;
1381,7 → 1289,7
else
q <= q >> 1;
endmodule
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
parameter length = 4;
input cke, clear;
output reg [0:length-1] q;
1673,11 → 1581,11
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
1692,8 → 1600,8
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
endmodule // async_comp
module vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
1718,10 → 1626,10
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dpram_1r1w
1807,16 → 1715,16
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
1876,7 → 1784,7
//////////////////////////////////////////////////////////////////////
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module vl_wb3wb3_bridge (
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
1937,7 → 1845,7
wbs_eoc <= wbs_bte_i==linear;
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
1996,10 → 1904,10
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
2044,236 → 1952,40
);
endmodule
// WB ROM
module vl_wb_boot_rom (
module wb_boot_rom (
wb_adr_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
parameter adr_hi = 31;
parameter adr_lo = 28;
parameter adr_sel = 4'hf;
parameter addr_width = 5;
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
`ifndef BOOT_ROM
`define BOOT_ROM "boot_rom.v"
`endif
input [adr_hi:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output hit_o;
input wb_clk;
input wb_rst;
wire hit;
reg [31:0] wb_dat;
reg wb_ack;
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
parameter addr_width = 5;
input [(addr_width+2)-1:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output reg [31:0] wb_dat_o;
output reg wb_ack_o;
input wb_clk;
input wb_rst;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat <= 32'h15000000;
wb_dat_o <= 32'h15000000;
else
case (wb_adr_i[addr_width-1:2])
case (wb_adr_i)
`include `BOOT_ROM
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat <= 32'h18000000;
1 : wb_dat <= 32'hA8200000;
2 : wb_dat <= 32'hA8C00100;
3 : wb_dat <= 32'h44003000;
4 : wb_dat <= 32'h15000000;
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat <= 32'h00000000;
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack <= 1'b0;
wb_ack_o <= 1'b0;
else
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
assign hit_o = hit;
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Arithmetic functions ////
//// ////
//// Description ////
//// Arithmetic functions for ALU and DSP ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// signed multiplication
module vl_mults (a,b,p);
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_b_width-1:0] b;
output [result_hi:result_lo] p;
wire signed [operand_a_width-1:0] ai;
wire signed [operand_b_width-1:0] bi;
wire signed [operand_a_width+operand_b_width-1:0] result;
assign ai = a;
assign bi = b;
assign result = ai * bi;
assign p = result[result_hi:result_lo];
endmodule
module vl_mults18x18 (a,b,p);
input [17:0] a,b;
output [35:0] p;
vl_mult
# (.operand_a_width(18), .operand_b_width(18))
mult0 (.a(a), .b(b), .p(p));
endmodule
// unsigned multiplication
module vl_mult (a,b,p);
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_b_width-1:0] b;
output [result_hi:result_hi] p;
wire [operand_a_width+operand_b_width-1:0] result;
assign result = a * b;
assign p = result[result_hi:result_lo];
endmodule
// shift unit
// supporting the following shift functions
// SLL
// SRL
// SRA
module vl_shift_unit_32( din, s, dout, opcode);
input [31:0] din; // data in operand
input [4:0] s; // shift operand
input [1:0] opcode;
output [31:0] dout;
parameter opcode_sll = 2'b00;
//parameter opcode_srl = 2'b01;
parameter opcode_sra = 2'b10;
//parameter opcode_ror = 2'b11;
wire sll, sra;
assign sll = opcode == opcode_sll;
assign sra = opcode == opcode_sra;
wire [15:1] s1;
wire [3:0] sign;
wire [7:0] tmp [0:3];
// first stage is multiplier based
// shift operand as fractional 8.7
assign s1[15] = sll & s[2:0]==3'd7;
assign s1[14] = sll & s[2:0]==3'd6;
assign s1[13] = sll & s[2:0]==3'd5;
assign s1[12] = sll & s[2:0]==3'd4;
assign s1[11] = sll & s[2:0]==3'd3;
assign s1[10] = sll & s[2:0]==3'd2;
assign s1[ 9] = sll & s[2:0]==3'd1;
assign s1[ 8] = s[2:0]==3'd0;
assign s1[ 7] = !sll & s[2:0]==3'd1;
assign s1[ 6] = !sll & s[2:0]==3'd2;
assign s1[ 5] = !sll & s[2:0]==3'd3;
assign s1[ 4] = !sll & s[2:0]==3'd4;
assign s1[ 3] = !sll & s[2:0]==3'd5;
assign s1[ 2] = !sll & s[2:0]==3'd6;
assign s1[ 1] = !sll & s[2:0]==3'd7;
assign sign[3] = din[31] & sra;
assign sign[2] = sign[3] & (&din[31:24]);
assign sign[1] = sign[2] & (&din[23:16]);
assign sign[0] = sign[1] & (&din[15:8]);
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
// second stage is multiplexer based
// shift on byte level
// mux byte 3
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
(sll & s[4:3]==2'b01) ? tmp[2] :
(sll & s[4:3]==2'b10) ? tmp[1] :
(sll & s[4:3]==2'b11) ? tmp[0] :
{8{sign[3]}};
// mux byte 2
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
(sll & s[4:3]==2'b01) ? tmp[1] :
(sll & s[4:3]==2'b10) ? tmp[0] :
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
(s[4:3]==2'b01) ? tmp[3] :
{8{sign[3]}};
// mux byte 1
assign dout[15:8] = (s[4:3]==2'b00) ? tmp[1] :
(sll & s[4:3]==2'b01) ? tmp[0] :
(sll & s[4:3]==2'b10) ? {8{1'b0}} :
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
(s[4:3]==2'b01) ? tmp[2] :
(s[4:3]==2'b10) ? tmp[3] :
{8{sign[3]}};
// mux byte 0
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
(sll) ? {8{1'b0}}:
(s[4:3]==2'b01) ? tmp[1] :
(s[4:3]==2'b10) ? tmp[2] :
tmp[3];
endmodule
// logic unit
// supporting the following logic functions
// a and b
// a or b
// a xor b
// not b
module vl_logic_unit( a, b, result, opcode);
parameter width = 32;
parameter opcode_and = 2'b00;
parameter opcode_or = 2'b01;
parameter opcode_xor = 2'b10;
input [width-1:0] a,b;
output [width-1:0] result;
input [1:0] opcode;
assign result = (opcode==opcode_and) ? a & b :
(opcode==opcode_or) ? a | b :
(opcode==opcode_xor) ? a ^ b :
b;
endmodule
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
parameter width = 32;
parameter opcode_add = 1'b0;
parameter opcode_sub = 1'b1;
input [width-1:0] a,b;
input c_in, add_sub, sign;
output [width-1:0] result;
output c_out, z, ovfl;
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
assign z = (result=={width{1'b0}});
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
(~a[width-1] & ~b[width-1] & result[width-1]);
endmodule
/versatile_library/trunk/rtl/verilog/clk_and_reset.v
90,7 → 90,7
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
output rst_o;
reg [1:0] tmp;
reg [0:1] tmp;
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
tmp <= 2'b11;
/versatile_library/trunk/rtl/verilog/registers.v
40,7 → 40,7
//// ////
//////////////////////////////////////////////////////////////////////
 
module vl_dff ( d, q, clk, rst);
module dff ( d, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
57,7 → 57,7
 
endmodule
 
module vl_dff_array ( d, q, clk, rst);
module dff_array ( d, q, clk, rst);
 
parameter width = 1;
parameter depth = 2;
82,7 → 82,7
endmodule
 
module vl_dff_ce ( d, ce, q, clk, rst);
module dff_ce ( d, ce, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
100,7 → 100,7
 
endmodule
 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
module dff_ce_clear ( d, ce, clear, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
160,7 → 160,7
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vl_dff_sr (
module dff_sr (
aclr,
aset,
clock,
245,7 → 245,7
`else
 
 
module vl_dff_sr ( aclr, aset, clock, data, q);
module dff_sr ( aclr, aset, clock, data, q);
 
input aclr;
input aset;
268,7 → 268,7
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
`ifdef ALTERA
module vl_latch ( d, le, q, clk);
module latch ( d, le, q, clk);
input d, le;
output q;
input clk;
287,7 → 287,7
endmodule
`endif
 
module vl_shreg ( d, q, clk, rst);
module shreg ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
303,7 → 303,7
assign q = dffs[depth];
endmodule
 
module vl_shreg_ce ( d, ce, q, clk, rst);
module shreg_ce ( d, ce, q, clk, rst);
parameter depth = 10;
input d, ce;
output q;
320,7 → 320,7
assign q = dffs[depth];
endmodule
 
module vl_delay ( d, q, clk, rst);
module delay ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
336,7 → 336,7
assign q = dffs[depth];
endmodule
 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
module delay_emptyflag ( d, q, emptyflag, clk, rst);
parameter depth = 10;
input d;
output q, emptyflag;
/versatile_library/trunk/rtl/verilog/wb.v
42,7 → 42,7
 
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module vl_wb3wb3_bridge (
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
118,7 → 118,7
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
 
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
185,12 → 185,12
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
 
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
 
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
240,50 → 240,39
endmodule
 
// WB ROM
module vl_wb_boot_rom (
module wb_boot_rom (
wb_adr_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
parameter adr_hi = 31;
parameter adr_lo = 28;
parameter adr_sel = 4'hf;
parameter addr_width = 5;
 
//E2_ifndef BOOT_ROM
//E2_define BOOT_ROM "boot_rom.v"
//E2_endif
parameter addr_width = 5;
input [adr_hi:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output hit_o;
input wb_clk;
input wb_rst;
 
wire hit;
reg [31:0] wb_dat;
reg wb_ack;
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
input [(addr_width+2)-1:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output reg [31:0] wb_dat_o;
output reg wb_ack_o;
input wb_clk;
input wb_rst;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat <= 32'h15000000;
wb_dat_o <= 32'h15000000;
else
case (wb_adr_i[addr_width-1:2])
case (wb_adr_i)
//E2_include `BOOT_ROM
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat <= 32'h18000000;
1 : wb_dat <= 32'hA8200000;
2 : wb_dat <= 32'hA8C00100;
3 : wb_dat <= 32'h44003000;
4 : wb_dat <= 32'h15000000;
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat <= 32'h00000000;
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
 
290,12 → 279,8
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack <= 1'b0;
wb_ack_o <= 1'b0;
else
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
 
assign hit_o = hit;
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
 
endmodule
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
52,7 → 52,7
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
output rst_o;
reg [1:0] tmp;
reg [0:1] tmp;
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
tmp <= 2'b11;
104,7 → 104,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_dff ( d, q, clk, rst);
module dff ( d, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
116,7 → 116,7
else
q <= d;
endmodule
module vl_dff_array ( d, q, clk, rst);
module dff_array ( d, q, clk, rst);
parameter width = 1;
parameter depth = 2;
parameter reset_value = 1'b0;
136,7 → 136,7
end
assign q = q_tmp[depth-1];
endmodule
module vl_dff_ce ( d, ce, q, clk, rst);
module dff_ce ( d, ce, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
149,7 → 149,7
if (ce)
q <= d;
endmodule
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
module dff_ce_clear ( d, ce, clear, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
198,7 → 198,7
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vl_dff_sr (
module dff_sr (
aclr,
aset,
clock,
274,13 → 274,13
// Retrieval info: LIB_FILE: lpm
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
module vl_latch ( d, le, q, clk);
module latch ( d, le, q, clk);
input d, le;
output q;
input clk;
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
endmodule
module vl_shreg ( d, q, clk, rst);
module shreg ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
293,7 → 293,7
dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
module vl_shreg_ce ( d, ce, q, clk, rst);
module shreg_ce ( d, ce, q, clk, rst);
parameter depth = 10;
input d, ce;
output q;
307,7 → 307,7
dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
module vl_delay ( d, q, clk, rst);
module delay ( d, q, clk, rst);
parameter depth = 10;
input d;
output q;
320,7 → 320,7
dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
module delay_emptyflag ( d, q, emptyflag, clk, rst);
parameter depth = 10;
input d;
output q, emptyflag;
336,98 → 336,6
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Logic functions ////
//// ////
//// Description ////
//// Logic functions such as multiplexers ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
468,7 → 376,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce ( cke, q, rst, clk);
module cnt_bin_ce ( cke, q, rst, clk);
parameter length = 4;
input cke;
output [length:1] q;
531,7 → 439,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
parameter length = 4;
input clear;
input cke;
595,7 → 503,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
parameter length = 4;
input clear;
input set;
663,7 → 571,7
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
737,7 → 645,7
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_zq ( zq, rst, clk);
module cnt_lfsr_zq ( zq, rst, clk);
parameter length = 4;
output reg zq;
input rst;
847,7 → 755,7
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
parameter length = 4;
input cke;
output reg zq;
960,7 → 868,7
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
1125,7 → 1033,7
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray ( q, rst, clk);
module cnt_gray ( q, rst, clk);
parameter length = 4;
output reg [length:1] q;
input rst;
1190,7 → 1098,7
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce ( cke, q, rst, clk);
module cnt_gray_ce ( cke, q, rst, clk);
parameter length = 4;
input cke;
output reg [length:1] q;
1258,7 → 1166,7
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
parameter length = 4;
input cke;
output reg [length:1] q;
1327,7 → 1235,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_cnt_shreg_wrap ( q, rst, clk);
module cnt_shreg_wrap ( q, rst, clk);
parameter length = 4;
output reg [0:length-1] q;
input rst;
1338,7 → 1246,7
else
q <= {q[length-1],q[0:length-2]};
endmodule
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
parameter length = 4;
input cke;
output reg [0:length-1] q;
1351,7 → 1259,7
if (cke)
q <= {q[length-1],q[0:length-2]};
endmodule
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
parameter length = 4;
input cke, clear;
output reg [0:length-1] q;
1367,7 → 1275,7
else
q <= q >> 1;
endmodule
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
parameter length = 4;
input cke, clear;
output reg [0:length-1] q;
1659,11 → 1567,11
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
1678,8 → 1586,8
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
endmodule // async_comp
module vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
1704,10 → 1612,10
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dpram_1r1w
1793,16 → 1701,16
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
1862,7 → 1770,7
//////////////////////////////////////////////////////////////////////
// async wb3 - wb3 bridge
`timescale 1ns/1ns
module vl_wb3wb3_bridge (
module wb3wb3_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
1923,7 → 1831,7
wbs_eoc <= wbs_bte_i==linear;
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt0 (
.cke(wbs_ack_o),
.clear(wbs_eoc),
1982,10 → 1890,10
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1'b0;
assign b_rd = b_rd_adr | b_rd_data;
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
vl_cnt_shreg_ce_clear # ( .length(16))
cnt_shreg_ce_clear # ( .length(16))
cnt1 (
.cke(wbm_ack_i),
.clear(wbm_eoc),
2030,236 → 1938,40
);
endmodule
// WB ROM
module vl_wb_boot_rom (
module wb_boot_rom (
wb_adr_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
parameter adr_hi = 31;
parameter adr_lo = 28;
parameter adr_sel = 4'hf;
parameter addr_width = 5;
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
//E2_ifndef BOOT_ROM
//E2_define BOOT_ROM "boot_rom.v"
//E2_endif
input [adr_hi:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output hit_o;
input wb_clk;
input wb_rst;
wire hit;
reg [31:0] wb_dat;
reg wb_ack;
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
parameter addr_width = 5;
input [(addr_width+2)-1:2] wb_adr_i;
input wb_stb_i;
input wb_cyc_i;
output reg [31:0] wb_dat_o;
output reg wb_ack_o;
input wb_clk;
input wb_rst;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat <= 32'h15000000;
wb_dat_o <= 32'h15000000;
else
case (wb_adr_i[addr_width-1:2])
case (wb_adr_i)
//E2_include `BOOT_ROM
/*
// Zero r0 and jump to 0x00000100
0 : wb_dat <= 32'h18000000;
1 : wb_dat <= 32'hA8200000;
2 : wb_dat <= 32'hA8C00100;
3 : wb_dat <= 32'h44003000;
4 : wb_dat <= 32'h15000000;
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
*/
default:
wb_dat <= 32'h00000000;
wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack <= 1'b0;
wb_ack_o <= 1'b0;
else
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
assign hit_o = hit;
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Arithmetic functions ////
//// ////
//// Description ////
//// Arithmetic functions for ALU and DSP ////
//// ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// signed multiplication
module vl_mults (a,b,p);
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_b_width-1:0] b;
output [result_hi:result_lo] p;
wire signed [operand_a_width-1:0] ai;
wire signed [operand_b_width-1:0] bi;
wire signed [operand_a_width+operand_b_width-1:0] result;
assign ai = a;
assign bi = b;
assign result = ai * bi;
assign p = result[result_hi:result_lo];
endmodule
module vl_mults18x18 (a,b,p);
input [17:0] a,b;
output [35:0] p;
vl_mult
# (.operand_a_width(18), .operand_b_width(18))
mult0 (.a(a), .b(b), .p(p));
endmodule
// unsigned multiplication
module vl_mult (a,b,p);
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_b_width-1:0] b;
output [result_hi:result_hi] p;
wire [operand_a_width+operand_b_width-1:0] result;
assign result = a * b;
assign p = result[result_hi:result_lo];
endmodule
// shift unit
// supporting the following shift functions
// SLL
// SRL
// SRA
module vl_shift_unit_32( din, s, dout, opcode);
input [31:0] din; // data in operand
input [4:0] s; // shift operand
input [1:0] opcode;
output [31:0] dout;
parameter opcode_sll = 2'b00;
//parameter opcode_srl = 2'b01;
parameter opcode_sra = 2'b10;
//parameter opcode_ror = 2'b11;
wire sll, sra;
assign sll = opcode == opcode_sll;
assign sra = opcode == opcode_sra;
wire [15:1] s1;
wire [3:0] sign;
wire [7:0] tmp [0:3];
// first stage is multiplier based
// shift operand as fractional 8.7
assign s1[15] = sll & s[2:0]==3'd7;
assign s1[14] = sll & s[2:0]==3'd6;
assign s1[13] = sll & s[2:0]==3'd5;
assign s1[12] = sll & s[2:0]==3'd4;
assign s1[11] = sll & s[2:0]==3'd3;
assign s1[10] = sll & s[2:0]==3'd2;
assign s1[ 9] = sll & s[2:0]==3'd1;
assign s1[ 8] = s[2:0]==3'd0;
assign s1[ 7] = !sll & s[2:0]==3'd1;
assign s1[ 6] = !sll & s[2:0]==3'd2;
assign s1[ 5] = !sll & s[2:0]==3'd3;
assign s1[ 4] = !sll & s[2:0]==3'd4;
assign s1[ 3] = !sll & s[2:0]==3'd5;
assign s1[ 2] = !sll & s[2:0]==3'd6;
assign s1[ 1] = !sll & s[2:0]==3'd7;
assign sign[3] = din[31] & sra;
assign sign[2] = sign[3] & (&din[31:24]);
assign sign[1] = sign[2] & (&din[23:16]);
assign sign[0] = sign[1] & (&din[15:8]);
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
// second stage is multiplexer based
// shift on byte level
// mux byte 3
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
(sll & s[4:3]==2'b01) ? tmp[2] :
(sll & s[4:3]==2'b10) ? tmp[1] :
(sll & s[4:3]==2'b11) ? tmp[0] :
{8{sign[3]}};
// mux byte 2
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
(sll & s[4:3]==2'b01) ? tmp[1] :
(sll & s[4:3]==2'b10) ? tmp[0] :
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
(s[4:3]==2'b01) ? tmp[3] :
{8{sign[3]}};
// mux byte 1
assign dout[15:8] = (s[4:3]==2'b00) ? tmp[1] :
(sll & s[4:3]==2'b01) ? tmp[0] :
(sll & s[4:3]==2'b10) ? {8{1'b0}} :
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
(s[4:3]==2'b01) ? tmp[2] :
(s[4:3]==2'b10) ? tmp[3] :
{8{sign[3]}};
// mux byte 0
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
(sll) ? {8{1'b0}}:
(s[4:3]==2'b01) ? tmp[1] :
(s[4:3]==2'b10) ? tmp[2] :
tmp[3];
endmodule
// logic unit
// supporting the following logic functions
// a and b
// a or b
// a xor b
// not b
module vl_logic_unit( a, b, result, opcode);
parameter width = 32;
parameter opcode_and = 2'b00;
parameter opcode_or = 2'b01;
parameter opcode_xor = 2'b10;
input [width-1:0] a,b;
output [width-1:0] result;
input [1:0] opcode;
assign result = (opcode==opcode_and) ? a & b :
(opcode==opcode_or) ? a | b :
(opcode==opcode_xor) ? a ^ b :
b;
endmodule
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
parameter width = 32;
parameter opcode_add = 1'b0;
parameter opcode_sub = 1'b1;
input [width-1:0] a,b;
input c_in, add_sub, sign;
output [width-1:0] result;
output c_out, z, ovfl;
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
assign z = (result=={width{1'b0}});
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
(~a[width-1] & ~b[width-1] & result[width-1]);
endmodule
/versatile_library/trunk/rtl/verilog/memories.v
328,7 → 328,7
endcase
 
`ifndef GENERATE_DIRECTION_AS_LATCH
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
342,8 → 342,8
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
359,8 → 359,8
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
 
endmodule // async_comp
 
392,11 → 392,11
q, rd, fifo_empty, rd_clk, rd_rst
);
 
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
498,19 → 498,19
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# ( .length(addr_width))
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
vl_cnt_gray_ce_bin
cnt_gray_ce_bin
# (.length(addr_width))
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
/versatile_library/trunk/rtl/verilog/Makefile
1,23 → 1,21
VERILOG_FILES = clk_and_reset.v
VERILOG_FILES += registers.v
VERILOG_FILES += logic.v
 
VERILOG_FILES_CNT = vl_cnt_bin_ce.v
VERILOG_FILES_CNT += vl_cnt_bin_ce_clear.v
VERILOG_FILES_CNT += vl_cnt_bin_ce_clear_set_rew.v
VERILOG_FILES_CNT += vl_cnt_bin_ce_rew_l1.v
VERILOG_FILES_CNT += vl_cnt_lfsr_zq.v
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_zq.v
VERILOG_FILES_CNT += vl_cnt_lfsr_ce_rew_l1.v
VERILOG_FILES_CNT += vl_cnt_gray.v
VERILOG_FILES_CNT += vl_cnt_gray_ce.v
VERILOG_FILES_CNT += vl_cnt_gray_ce_bin.v
VERILOG_FILES_CNT = cnt_bin_ce.v
VERILOG_FILES_CNT += cnt_bin_ce_clear.v
VERILOG_FILES_CNT += cnt_bin_ce_clear_set_rew.v
VERILOG_FILES_CNT += cnt_bin_ce_rew_l1.v
VERILOG_FILES_CNT += cnt_lfsr_zq.v
VERILOG_FILES_CNT += cnt_lfsr_ce_zq.v
VERILOG_FILES_CNT += cnt_lfsr_ce_rew_l1.v
VERILOG_FILES_CNT += cnt_gray.v
VERILOG_FILES_CNT += cnt_gray_ce.v
VERILOG_FILES_CNT += cnt_gray_ce_bin.v
 
VERILOG_FILES += $(VERILOG_FILES_CNT)
VERILOG_FILES += counters.v
VERILOG_FILES += memories.v
VERILOG_FILES += wb.v
VERILOG_FILES += arith.v
 
VERSATILE_LIBRARIES = versatile_library.v
VERSATILE_LIBRARIES += versatile_library_actel.v
29,16 → 27,15
 
#.PHONY: $(VERILOG_FILES_CNT)
$(VERILOG_FILES_CNT):
./versatile_counter_generator.php cnt_bin_ce.csv > vl_cnt_bin_ce.v
./versatile_counter_generator.php cnt_bin_ce_clear.csv > vl_cnt_bin_ce_clear.v
./versatile_counter_generator.php cnt_bin_ce_clear_set_rew.csv > vl_cnt_bin_ce_clear_set_rew.v
./versatile_counter_generator.php cnt_bin_ce_rew_l1.csv > vl_cnt_bin_ce_rew_l1.v
./versatile_counter_generator.php cnt_lfsr_zq.csv > vl_cnt_lfsr_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_zq.csv > vl_cnt_lfsr_ce_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_rew_l1.csv > vl_cnt_lfsr_ce_rew_l1.v
./versatile_counter_generator.php cnt_gray.csv > vl_cnt_gray.v
./versatile_counter_generator.php cnt_gray_ce.csv > vl_cnt_gray_ce.v
./versatile_counter_generator.php cnt_gray_ce_bin.csv > vl_cnt_gray_ce_bin.v
./versatile_counter_generator.php cnt_bin_ce.csv > cnt_bin_ce.v
./versatile_counter_generator.php cnt_bin_ce_clear.csv > cnt_bin_ce_clear.v
./versatile_counter_generator.php cnt_bin_ce_clear_set_rew.csv > cnt_bin_ce_clear_set_rew.v
./versatile_counter_generator.php cnt_bin_ce_rew_l1.csv > cnt_bin_ce_rew_l1.v
./versatile_counter_generator.php cnt_lfsr_zq.csv > cnt_lfsr_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_zq.csv > cnt_lfsr_ce_zq.v
./versatile_counter_generator.php cnt_lfsr_ce_rew_l1.csv > cnt_lfsr_ce_rew_l1.v
./versatile_counter_generator.php cnt_gray_ce.csv > cnt_gray_ce.v
./versatile_counter_generator.php cnt_gray_ce_bin.csv > cnt_gray_ce_bin.v
 
versatile_library.v: $(VERILOG_FILES)
cat $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library.v
/versatile_library/trunk/rtl/verilog/counters.v
40,7 → 40,7
//// ////
//////////////////////////////////////////////////////////////////////
 
module vl_cnt_shreg_wrap ( q, rst, clk);
module cnt_shreg_wrap ( q, rst, clk);
 
parameter length = 4;
output reg [0:length-1] q;
55,7 → 55,7
endmodule
 
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
 
parameter length = 4;
input cke;
72,7 → 72,7
endmodule
 
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
 
parameter length = 4;
input cke, clear;
92,7 → 92,7
endmodule
 
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
 
parameter length = 4;
input cke, clear;
/versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_bin_ce_clear,binary,,,,
cnt_bin_ce_clear,binary,,,,
,,,,,
clear,set,cke,rew,,
1,0,1,0,,
/versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_rew_l1.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_lfsr_ce_rew_l1,LFSR,,,,
cnt_lfsr_ce_rew_l1,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,1,,
/versatile_library/trunk/rtl/verilog/cnt_lfsr_ce_zq.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_lfsr_ce_zq,LFSR,,,,
cnt_lfsr_ce_zq,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
/versatile_library/trunk/rtl/verilog/cnt_bin_ce_rew_l1.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_bin_ce_rew_l1,binary,,,,
cnt_bin_ce_rew_l1,binary,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,1,,
/versatile_library/trunk/rtl/verilog/cnt_gray_ce_bin.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_gray_ce_bin,GRAY,,,,
cnt_gray_ce_bin,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
/versatile_library/trunk/rtl/verilog/cnt_bin_ce_clear_set_rew.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_bin_ce_clear_set_rew,binary,,,,
cnt_bin_ce_clear_set_rew,binary,,,,
,,,,,
clear,set,cke,rew,,
1,1,1,1,,
/versatile_library/trunk/rtl/verilog/cnt_bin_ce.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_bin_ce,binary,,,,
cnt_bin_ce,binary,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
/versatile_library/trunk/rtl/verilog/cnt_lfsr_zq.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_lfsr_zq,LFSR,,,,
cnt_lfsr_zq,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,0,0,,
/versatile_library/trunk/rtl/verilog/cnt_lfsr.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_lfsr,LFSR,,,,
cnt_lfsr,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,0,0,,
/versatile_library/trunk/rtl/verilog/cnt_gray_ce.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_gray_ce,GRAY,,,,
cnt_gray_ce,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
/versatile_library/trunk/rtl/verilog/cnt_lfsr_ce.csv
1,5 → 1,5
Name,type,,,,
vl_cnt_lfsr_ce,LFSR,,,,
cnt_lfsr_ce,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
/versatile_library/trunk/doc/src/Versatile_library.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/versatile_library/trunk/doc/Versatile_library.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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