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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

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    from Rev 23 to Rev 22
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Rev 23 → Rev 22

/versatile_library/trunk/rtl/verilog/versatile_library.v
2407,7 → 2407,12
input rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2414,7 → 2419,7
vl_cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1952,12 → 1952,18
input rd_clk;
input rd_rst;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
vl_cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
1938,12 → 1938,18
input rd_clk;
input rd_rst;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
vl_cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
/versatile_library/trunk/rtl/verilog/memories.v
386,7 → 386,12
input rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
393,7 → 398,7
vl_cnt_gray_ce_bin
# (.length(addr_width))
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))

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