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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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    from Rev 30 to Rev 31
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Rev 30 → Rev 31

/versatile_library/trunk/rtl/verilog/memories.v
309,7 → 309,7
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
 
vl_cnt_bin_ce_rew_zq_l1
vl_cnt_bin_ce_rew_q_zq_l1
# (.length(addr_width+1), .level1_value(1<<addr_width))
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
 
/versatile_library/trunk/rtl/verilog/versatile_library.v
2923,7 → 2923,7
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
 
vl_cnt_bin_ce_rew_zq_l1
vl_cnt_bin_ce_rew_q_zq_l1
# (.length(addr_width+1), .level1_value(1<<addr_width))
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
 
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
2435,7 → 2435,7
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
vl_cnt_bin_ce_rew_zq_l1
vl_cnt_bin_ce_rew_q_zq_l1
# (.length(addr_width+1), .level1_value(1<<addr_width))
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
endmodule
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2421,7 → 2421,7
vl_dpram_1r1w
# (.data_width(data_width), .addr_width(addr_width))
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
vl_cnt_bin_ce_rew_zq_l1
vl_cnt_bin_ce_rew_q_zq_l1
# (.length(addr_width+1), .level1_value(1<<addr_width))
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
endmodule

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