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    from Rev 67 to Rev 68
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Rev 67 → Rev 68

/versatile_library/trunk/rtl/verilog/versatile_library.v
3524,6 → 3524,7
 
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
3532,9 → 3533,9
input clk;
 
`ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
`else
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
reg [data_width-1:0] ram [mem_size-1:0];
`endif
 
parameter memory_init = 0;
4789,8 → 4790,9
 
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 26;
parameter adr_size = 16;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
4876,8 → 4878,8
`BASE`MODULE # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(1),
.memory_file("memory_file"))
.memory_init(memory_init),
.memory_file(memory_file))
ram0(
`undef MODULE
.d(wbs_dat_i),
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1122,6 → 1122,7
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
1129,9 → 1130,9
output reg [(data_width-1):0] q;
input clk;
`ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
`else
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
reg [data_width-1:0] ram [mem_size-1:0];
`endif
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
2053,8 → 2054,9
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 26;
parameter adr_size = 16;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
2130,8 → 2132,8
vl_ram_be # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(1),
.memory_file("memory_file"))
.memory_init(memory_init),
.memory_file(memory_file))
ram0(
.d(wbs_dat_i),
.adr(wbs_adr_i[adr_size-1:2]),
/versatile_library/trunk/rtl/verilog/wb.v
582,8 → 582,9
 
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 26;
parameter adr_size = 16;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
669,8 → 670,8
`BASE`MODULE # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(1),
.memory_file("memory_file"))
.memory_init(memory_init),
.memory_file(memory_file))
ram0(
`undef MODULE
.d(wbs_dat_i),
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
1230,6 → 1230,7
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
1237,9 → 1238,9
output reg [(data_width-1):0] q;
input clk;
`ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
`else
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
reg [data_width-1:0] ram [mem_size-1:0];
`endif
parameter memory_init = 0;
parameter memory_file = "vl_ram.vmem";
2158,8 → 2159,9
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
parameter adr_size = 26;
parameter adr_size = 16;
parameter adr_lo = 2;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
2235,8 → 2237,8
vl_ram_be # (
.data_width(dat_size),
.addr_width(adr_size),
.memory_init(1),
.memory_file("memory_file"))
.memory_init(memory_init),
.memory_file(memory_file))
ram0(
.d(wbs_dat_i),
.adr(wbs_adr_i[adr_size-1:2]),
/versatile_library/trunk/rtl/verilog/memories.v
105,6 → 105,7
 
parameter data_width = 32;
parameter addr_width = 8;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
113,9 → 114,9
input clk;
 
//E2_ifdef SYSTEMVERILOG
logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
reg [data_width-1:0] ram [mem_size-1:0];
//E2_endif
 
parameter memory_init = 0;

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