OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 69 to Rev 70
    Reverse comparison

Rev 69 → Rev 70

/versatile_library/trunk/rtl/verilog/versatile_library.v
4801,15 → 4801,15
localparam cw = 3;
localparam bw = 2;
 
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
output wb_ack_o;
input wb_clk, wb_rst;
input [dw-1:0] wbs_dat_i;
input [aw-1:0] wbs_adr_i;
input [cw-1:0] wbs_cti_i;
input [bw-1:0] wbs_bte_i;
input [sw-1:0] wbs_sel_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
 
wire [sw-1:0] cke;
 
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
2063,15 → 2063,15
localparam sw = dat_size/8;
localparam cw = 3;
localparam bw = 2;
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
output wb_ack_o;
input wb_clk, wb_rst;
input [dw-1:0] wbs_dat_i;
input [aw-1:0] wbs_adr_i;
input [cw-1:0] wbs_cti_i;
input [bw-1:0] wbs_bte_i;
input [sw-1:0] wbs_sel_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
wire [sw-1:0] cke;
reg wbs_ack_o;
vl_ram_be # (
/versatile_library/trunk/rtl/verilog/wb.v
593,15 → 593,15
localparam cw = 3;
localparam bw = 2;
 
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
output wb_ack_o;
input wb_clk, wb_rst;
input [dw-1:0] wbs_dat_i;
input [aw-1:0] wbs_adr_i;
input [cw-1:0] wbs_cti_i;
input [bw-1:0] wbs_bte_i;
input [sw-1:0] wbs_sel_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
 
wire [sw-1:0] cke;
 
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2168,15 → 2168,15
localparam sw = dat_size/8;
localparam cw = 3;
localparam bw = 2;
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
output wb_ack_o;
input wb_clk, wb_rst;
input [dw-1:0] wbs_dat_i;
input [aw-1:0] wbs_adr_i;
input [cw-1:0] wbs_cti_i;
input [bw-1:0] wbs_bte_i;
input [sw-1:0] wbs_sel_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
wire [sw-1:0] cke;
reg wbs_ack_o;
vl_ram_be # (

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.