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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 70 to Rev 71
    Reverse comparison

Rev 70 → Rev 71

/versatile_library/trunk/rtl/verilog/versatile_library.v
4809,7 → 4809,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
input wb_clk, wb_rst;
 
wire [sw-1:0] cke;
 
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
2071,7 → 2071,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
input wb_clk, wb_rst;
wire [sw-1:0] cke;
reg wbs_ack_o;
vl_ram_be # (
/versatile_library/trunk/rtl/verilog/wb.v
601,7 → 601,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
input wb_clk, wb_rst;
 
wire [sw-1:0] cke;
 
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2176,7 → 2176,7
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
input wb_clk, wb_rst;
wire [sw-1:0] cke;
reg wbs_ack_o;
vl_ram_be # (

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