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Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 76 to Rev 77
    Reverse comparison

Rev 76 → Rev 77

/versatile_library/trunk/rtl/verilog/versatile_library.v
3928,7 → 3928,7
generate
if (a_data_width==32 & b_data_width==64) begin : inst32to64
 
wire [63:0] temp;
wire [63:0] tmp;
`define MODULE dpram_2r2w
`BASE`MODULE
# (.data_width(8), .addr_width(b_addr_width-3))
4743,7 → 4743,7
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
 
4905,7 → 4905,7
`undef MODULE
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
// avalon master side
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
 
input [31:0] wbs_dat_i;
4951,7 → 4951,7
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
 
`define MODULE wb3wb3_bridge
`BASE`MODULE (
`BASE`MODULE wbwb3inst (
`undef MODULE
// wishbone slave side
.wbs_dat_i(wbs_dat_i),
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
1402,7 → 1402,7
reg [(b_data_width-1):0] q_b;
generate
if (a_data_width==32 & b_data_width==64) begin : inst32to64
wire [63:0] temp;
wire [63:0] tmp;
vl_dpram_2r2w
# (.data_width(8), .addr_width(b_addr_width-3))
ram0 (
1991,7 → 1991,7
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
vl_cnt_shreg_ce_clear # ( .length(16))
2120,7 → 2120,7
module vl_wb3avalon_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
// avalon master side
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
2159,7 → 2159,7
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
vl_wb3wb3_bridge (
vl_wb3wb3_bridge wbwb3inst (
// wishbone slave side
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
/versatile_library/trunk/rtl/verilog/wb.v
148,7 → 148,7
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
 
310,7 → 310,7
`undef MODULE
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
// avalon master side
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
 
input [31:0] wbs_dat_i;
356,7 → 356,7
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
 
`define MODULE wb3wb3_bridge
`BASE`MODULE (
`BASE`MODULE wbwb3inst (
`undef MODULE
// wishbone slave side
.wbs_dat_i(wbs_dat_i),
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
1509,7 → 1509,7
reg [(b_data_width-1):0] q_b;
generate
if (a_data_width==32 & b_data_width==64) begin : inst32to64
wire [63:0] temp;
wire [63:0] tmp;
vl_dpram_2r2w
# (.data_width(8), .addr_width(b_addr_width-3))
ram0 (
2096,7 → 2096,7
wbs_eoc <= 1'b0;
else
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
wbs_eoc <= wbs_bte_i==linear;
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
else if (wbs_eoc_alert & (a_rd | a_wr))
wbs_eoc <= 1'b1;
vl_cnt_shreg_ce_clear # ( .length(16))
2225,7 → 2225,7
module vl_wb3avalon_bridge (
// wishbone slave side
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
// wishbone master side
// avalon master side
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
2264,7 → 2264,7
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
vl_wb3wb3_bridge (
vl_wb3wb3_bridge wbwb3inst (
// wishbone slave side
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
/versatile_library/trunk/rtl/verilog/memories.v
318,7 → 318,7
generate
if (a_data_width==32 & b_data_width==64) begin : inst32to64
 
wire [63:0] temp;
wire [63:0] tmp;
`define MODULE dpram_2r2w
`BASE`MODULE
# (.data_width(8), .addr_width(b_addr_width-3))

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