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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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    from Rev 81 to Rev 82
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Rev 81 → Rev 82

/versatile_library/trunk/rtl/verilog/versatile_library.v
4936,6 → 4936,7
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
reg last_cyc;
reg [3:0] counter;
reg read_busy;
 
always @ (posedge clk or posedge rst)
if (rst)
4943,17 → 4944,15
else
last_cyc <= wbm_cyc_o;
 
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
read_busy <= 1'b0;
else
if (!last_cyc & wbm_cyc_o & !wbm_we_o)
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
if (read & !waitrequest)
read_busy <= 1'b1;
else if (wbm_ack_i & wbm_cti_o!=3'b010)
read_busy <= 1'b0;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
4960,7 → 4959,7
(wbm_bte_o==2'b10) ? 4'd8 :
(wbm_bte_o==2'b11) ? 4'd16:
4'd1;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
 
always @ (posedge clk or posedge rst)
if (rst) begin
4974,7 → 4973,7
end else if (!waitrequest & wbm_stb_o) begin
counter <= counter - 4'd1;
end
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
 
`define MODULE wb3wb3_bridge
/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
2148,28 → 2148,27
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
reg last_cyc;
reg [3:0] counter;
reg read_busy;
always @ (posedge clk or posedge rst)
if (rst)
last_cyc <= 1'b0;
else
last_cyc <= wbm_cyc_o;
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
read_busy <= 1'b0;
else
if (!last_cyc & wbm_cyc_o & !wbm_we_o)
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
if (read & !waitrequest)
read_busy <= 1'b1;
else if (wbm_ack_i & wbm_cti_o!=3'b010)
read_busy <= 1'b0;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
(wbm_bte_o==2'b10) ? 4'd8 :
(wbm_bte_o==2'b11) ? 4'd16:
4'd1;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
always @ (posedge clk or posedge rst)
if (rst) begin
counter <= 4'd0;
2182,7 → 2181,7
end else if (!waitrequest & wbm_stb_o) begin
counter <= counter - 4'd1;
end
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
vl_wb3wb3_bridge wbwb3inst (
// wishbone slave side
/versatile_library/trunk/rtl/verilog/wb.v
341,6 → 341,7
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
reg last_cyc;
reg [3:0] counter;
reg read_busy;
 
always @ (posedge clk or posedge rst)
if (rst)
348,17 → 349,15
else
last_cyc <= wbm_cyc_o;
 
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
read_busy <= 1'b0;
else
if (!last_cyc & wbm_cyc_o & !wbm_we_o)
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
if (read & !waitrequest)
read_busy <= 1'b1;
else if (wbm_ack_i & wbm_cti_o!=3'b010)
read_busy <= 1'b0;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
365,7 → 364,7
(wbm_bte_o==2'b10) ? 4'd8 :
(wbm_bte_o==2'b11) ? 4'd16:
4'd1;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
 
always @ (posedge clk or posedge rst)
if (rst) begin
379,7 → 378,7
end else if (!waitrequest & wbm_stb_o) begin
counter <= counter - 4'd1;
end
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
 
`define MODULE wb3wb3_bridge
/versatile_library/trunk/rtl/verilog/versatile_library_altera.v
2253,28 → 2253,27
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
reg last_cyc;
reg [3:0] counter;
reg read_busy;
always @ (posedge clk or posedge rst)
if (rst)
last_cyc <= 1'b0;
else
last_cyc <= wbm_cyc_o;
/*
always @ (posedge clk or posedge rst)
if (rst)
read <= 1'b0;
read_busy <= 1'b0;
else
if (!last_cyc & wbm_cyc_o & !wbm_we_o)
read <= 1'b1;
else if (!waitrequest)
read <= 1'b0;
*/
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
if (read & !waitrequest)
read_busy <= 1'b1;
else if (wbm_ack_i & wbm_cti_o!=3'b010)
read_busy <= 1'b0;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
(wbm_bte_o==2'b10) ? 4'd8 :
(wbm_bte_o==2'b11) ? 4'd16:
4'd1;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
always @ (posedge clk or posedge rst)
if (rst) begin
counter <= 4'd0;
2287,7 → 2286,7
end else if (!waitrequest & wbm_stb_o) begin
counter <= counter - 4'd1;
end
end
end
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
vl_wb3wb3_bridge wbwb3inst (
// wishbone slave side

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