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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 106 to Rev 107
    Reverse comparison

Rev 106 → Rev 107

/versatile_library.v
6053,7 → 6053,7
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [data_width_a-1:0] wbsa_dat_o;
output wbsa_ack_o;
output reg wbsa_ack_o;
output wbsa_stall_o;
input wbsa_clk, wbsa_rst;
 
6064,7 → 6064,7
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [data_width_b-1:0] wbsb_dat_o;
output wbsb_ack_o;
output reg wbsb_ack_o;
output wbsb_stall_o;
input wbsb_clk, wbsb_rst;
 
/versatile_library_actel.v
2766,7 → 2766,7
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [data_width_a-1:0] wbsa_dat_o;
output wbsa_ack_o;
output reg wbsa_ack_o;
output wbsa_stall_o;
input wbsa_clk, wbsa_rst;
input [data_width_b-1:0] wbsb_dat_i;
2776,7 → 2776,7
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [data_width_b-1:0] wbsb_dat_o;
output wbsb_ack_o;
output reg wbsb_ack_o;
output wbsb_stall_o;
input wbsb_clk, wbsb_rst;
wire [addr_width_a-1:0] adr_a;
/wb.v
1141,7 → 1141,7
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [data_width_a-1:0] wbsa_dat_o;
output wbsa_ack_o;
output reg wbsa_ack_o;
output wbsa_stall_o;
input wbsa_clk, wbsa_rst;
 
1152,7 → 1152,7
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [data_width_b-1:0] wbsb_dat_o;
output wbsb_ack_o;
output reg wbsb_ack_o;
output wbsb_stall_o;
input wbsb_clk, wbsb_rst;
 
/versatile_library_altera.v
2871,7 → 2871,7
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [data_width_a-1:0] wbsa_dat_o;
output wbsa_ack_o;
output reg wbsa_ack_o;
output wbsa_stall_o;
input wbsa_clk, wbsa_rst;
input [data_width_b-1:0] wbsb_dat_i;
2881,7 → 2881,7
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [data_width_b-1:0] wbsb_dat_o;
output wbsb_ack_o;
output reg wbsb_ack_o;
output wbsb_stall_o;
input wbsb_clk, wbsb_rst;
wire [addr_width_a-1:0] adr_a;

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