URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 109 to Rev 110
- ↔ Reverse comparison
Rev 109 → Rev 110
/versatile_library.v
6115,7 → 6115,7
|
`define MODULE dpram_be_2r2w |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.b_data_width(data_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
ram_i ( |
/versatile_library_actel.v
2820,7 → 2820,7
end |
endgenerate |
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.b_data_width(data_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
ram_i ( |
.d_a(wbsa_dat_i), |
/wb.v
1203,7 → 1203,7
|
`define MODULE dpram_be_2r2w |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.b_data_width(data_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
`undef MODULE |
ram_i ( |
/versatile_library_altera.v
2925,7 → 2925,7
end |
endgenerate |
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size), |
.b_data_width(data_width_b), .b_addr_width(addr_width_b), |
.b_data_width(data_width_b), |
.memory_init(memory_init), .memory_file(memory_file)) |
ram_i ( |
.d_a(wbsa_dat_i), |