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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 141 to Rev 142
    Reverse comparison

Rev 141 → Rev 142

/versatile_library.v
6202,6 → 6202,7
parameter mode = "B3";
parameter memory_init = 0;
parameter memory_file = "vl_ram.v";
parameter debug = 0;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
6256,10 → 6257,12
`undef MODULE
assign we_b = wbsb_we_i & wbsb_ack_o;
end else if (mode=="B4") begin : b4_inst
assign adr_a = wbsa_adr_i;
`define MODULE dff
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
assign wbsa_stall_o = 1'b0;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
assign adr_b = wbsb_adr_i;
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
`undef MODULE
assign wbsb_stall_o = 1'b0;
6270,7 → 6273,8
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.memory_init(memory_init), .memory_file(memory_file))
.memory_init(memory_init), .memory_file(memory_file),
.debug(debug))
`undef MODULE
ram_i (
.d_a(wbsa_dat_i),
/versatile_library_actel.v
4100,6 → 4100,7
parameter mode = "B3";
parameter memory_init = 0;
parameter memory_file = "vl_ram.v";
parameter debug = 0;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
4150,9 → 4151,11
.rst(wbsb_rst));
assign we_b = wbsb_we_i & wbsb_ack_o;
end else if (mode=="B4") begin : b4_inst
assign adr_a = wbsa_adr_i;
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
assign wbsa_stall_o = 1'b0;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
assign adr_b = wbsb_adr_i;
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
assign wbsb_stall_o = 1'b0;
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
4160,7 → 4163,8
endgenerate
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.memory_init(memory_init), .memory_file(memory_file))
.memory_init(memory_init), .memory_file(memory_file),
.debug(debug))
ram_i (
.d_a(wbsa_dat_i),
.q_a(wbsa_dat_o),
/wb.v
1137,6 → 1137,7
parameter mode = "B3";
parameter memory_init = 0;
parameter memory_file = "vl_ram.v";
parameter debug = 0;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
1191,10 → 1192,12
`undef MODULE
assign we_b = wbsb_we_i & wbsb_ack_o;
end else if (mode=="B4") begin : b4_inst
assign adr_a = wbsa_adr_i;
`define MODULE dff
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
assign wbsa_stall_o = 1'b0;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
assign adr_b = wbsb_adr_i;
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
`undef MODULE
assign wbsb_stall_o = 1'b0;
1205,7 → 1208,8
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.memory_init(memory_init), .memory_file(memory_file))
.memory_init(memory_init), .memory_file(memory_file),
.debug(debug))
`undef MODULE
ram_i (
.d_a(wbsa_dat_i),
/versatile_library_altera.v
4193,6 → 4193,7
parameter mode = "B3";
parameter memory_init = 0;
parameter memory_file = "vl_ram.v";
parameter debug = 0;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
4243,9 → 4244,11
.rst(wbsb_rst));
assign we_b = wbsb_we_i & wbsb_ack_o;
end else if (mode=="B4") begin : b4_inst
assign adr_a = wbsa_adr_i;
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
assign wbsa_stall_o = 1'b0;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
assign adr_b = wbsb_adr_i;
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
assign wbsb_stall_o = 1'b0;
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
4253,7 → 4256,8
endgenerate
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.memory_init(memory_init), .memory_file(memory_file))
.memory_init(memory_init), .memory_file(memory_file),
.debug(debug))
ram_i (
.d_a(wbsa_dat_i),
.q_a(wbsa_dat_o),

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