URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 153 to Rev 152
- ↔ Reverse comparison
Rev 153 → Rev 152
/versatile_library.v
7449,12 → 7449,19
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
|
assign dout = |
(opcode==opcode_sll) ? din << s : |
(opcode==opcode_srl) ? din >> s : |
(opcode==opcode_sra) ? (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})) : |
din << s; |
reg [31:0] dout; |
`ifdef SYSTEMVERILOG |
always_comb |
`else |
always @ (din or s or opcode) |
`endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
|
end |
endgenerate |
/versatile_library_actel.v
5172,11 → 5172,19
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
assign dout = |
(opcode==opcode_sll) ? din << s : |
(opcode==opcode_srl) ? din >> s : |
(opcode==opcode_sra) ? (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})) : |
din << s; |
reg [31:0] dout; |
`ifdef SYSTEMVERILOG |
always_comb |
`else |
always @ (din or s or opcode) |
`endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
end |
endgenerate |
endmodule |
/versatile_library_altera.v
5267,11 → 5267,19
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
assign dout = |
(opcode==opcode_sll) ? din << s : |
(opcode==opcode_srl) ? din >> s : |
(opcode==opcode_sra) ? (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})) : |
din << s; |
reg [31:0] dout; |
`ifdef SYSTEMVERILOG |
always_comb |
`else |
always @ (din or s or opcode) |
`endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
end |
endgenerate |
endmodule |
/arith.v
190,12 → 190,19
(s[4:3]==2'b10) ? tmp[2] : |
tmp[3]; |
end else begin : impl_classic |
|
assign dout = |
(opcode==opcode_sll) ? din << s : |
(opcode==opcode_srl) ? din >> s : |
(opcode==opcode_sra) ? (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})) : |
din << s; |
reg [31:0] dout; |
//E2_ifdef SYSTEMVERILOG |
always_comb |
//E2_else |
always @ (din or s or opcode) |
//E2_endif |
case (opcode) |
opcode_sll: dout = din << s; |
opcode_srl: dout = din >> s; |
opcode_sra: dout = (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})); |
//opcode_ror: dout = not yet implemented |
default: dout = din << s; |
endcase |
|
end |
endgenerate |