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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 18 to Rev 21
    Reverse comparison

Rev 18 → Rev 21

/memories.v
386,12 → 386,12
input rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
 
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
/versatile_library.v
71,7 → 71,7
endmodule
`else
`ifdef ALTERA
altera
//altera
`else
 
`timescale 1 ns/100 ps
647,7 → 647,7
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
669,7 → 669,7
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
692,7 → 692,7
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
// and
2146,12 → 2146,12
input rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
 
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
/versatile_library_actel.v
395,7 → 395,7
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
411,7 → 411,7
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
428,7 → 428,7
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
1714,10 → 1714,12
input rd_clk;
input rd_rst;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
/clk_and_reset.v
71,7 → 71,7
endmodule
`else
`ifdef ALTERA
altera
//altera
`else
 
`timescale 1 ns/100 ps
/versatile_library_altera.v
42,7 → 42,7
// Global buffer
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
altera
//altera
// ALTERA
//ACTEL
// sync reset
381,7 → 381,7
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
397,7 → 397,7
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
414,7 → 414,7
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
assign tmp[0] = {width{sel[0]}} & a0;
1700,10 → 1700,12
input rd_clk;
input rd_rst;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
/*
vl_fifo_1r1w_async (
d, wr, fifo_full, wr_clk, wr_rst,
q, rd, fifo_empty, rd_clk, rd_rst
);
*/
vl_cnt_gray_ce_bin
# ( .length(addr_width))
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));

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