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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 23 to Rev 24
    Reverse comparison

Rev 23 → Rev 24

/versatile_library.v
366,6 → 366,27
 
endmodule
 
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
output reg [width-1:0] q;
 
always @ (posedge clk or posedge rst)
if (rst)
q <= reset_value;
else
if (ce)
if (set)
q <= {width{1'b1}};
else
q <= d;
 
endmodule
 
`ifdef ALTERA
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
/versatile_library_actel.v
268,6 → 268,22
else
q <= d;
endmodule
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
output reg [width-1:0] q;
always @ (posedge clk or posedge rst)
if (rst)
q <= reset_value;
else
if (ce)
if (set)
q <= {width{1'b1}};
else
q <= d;
endmodule
module vl_dff_sr ( aclr, aset, clock, data, q);
input aclr;
input aset;
/registers.v
121,6 → 121,27
 
endmodule
 
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
output reg [width-1:0] q;
 
always @ (posedge clk or posedge rst)
if (rst)
q <= reset_value;
else
if (ce)
if (set)
q <= {width{1'b1}};
else
q <= d;
 
endmodule
 
`ifdef ALTERA
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
/versatile_library_altera.v
165,6 → 165,22
else
q <= d;
endmodule
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
output reg [width-1:0] q;
always @ (posedge clk or posedge rst)
if (rst)
q <= reset_value;
else
if (ce)
if (set)
q <= {width{1'b1}};
else
q <= d;
endmodule
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0

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