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    /versatile_library/trunk/rtl/verilog
    from Rev 35 to Rev 36
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Rev 35 → Rev 36

/versatile_library.v
844,6 → 844,24
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 4;
 
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
 
endmodule
 
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
852,6 → 870,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
861,7 → 883,7
 
// or
assign dout = tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
872,6 → 894,11
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
882,7 → 909,7
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
893,6 → 920,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
904,7 → 935,7
 
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
915,6 → 946,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
927,7 → 962,7
 
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
938,6 → 973,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
951,7 → 990,7
 
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/versatile_library_actel.v
437,6 → 437,19
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 2;
443,6 → 456,10
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
450,6 → 467,7
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
457,6 → 475,10
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
465,6 → 487,7
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
472,6 → 495,10
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
481,6 → 508,7
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
488,6 → 516,10
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
498,6 → 530,7
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
505,6 → 538,10
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
516,6 → 553,7
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/versatile_library_altera.v
545,6 → 545,19
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
parameter width = 32;
parameter nr_of_ports = 4;
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
localparam nr_of_ports = 2;
551,6 → 564,10
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
558,6 → 575,7
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign dout = tmp[1] | tmp[0];
*/
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
565,6 → 583,10
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
573,6 → 595,7
assign tmp[2] = {width{sel[2]}} & a2;
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
580,6 → 603,10
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
589,6 → 616,7
assign tmp[3] = {width{sel[3]}} & a3;
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
596,6 → 624,10
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
606,6 → 638,7
assign tmp[4] = {width{sel[4]}} & a4;
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
613,6 → 646,10
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
// and
624,6 → 661,7
assign tmp[5] = {width{sel[5]}} & a5;
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
*/
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
/logic.v
39,6 → 39,24
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
 
parameter width = 32;
parameter nr_of_ports = 4;
 
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
always @ (a, sel)
begin
dout = a[width-1:0] & {width{sel[0]}};
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
end
 
endmodule
 
module vl_mux2_andor ( a1, a0, sel, dout);
 
parameter width = 32;
47,6 → 65,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
56,7 → 78,7
 
// or
assign dout = tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
67,6 → 89,11
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
77,7 → 104,7
 
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
88,6 → 115,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
99,7 → 130,7
 
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
110,6 → 141,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
122,7 → 157,7
 
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
133,6 → 168,10
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
vl_mux_andor
# ( .width(width), .nr_of_ports(nr_of_ports)
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
 
146,5 → 185,5
 
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule

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