OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 48 to Rev 49
    Reverse comparison

Rev 48 → Rev 49

/versatile_library.v
61,6 → 61,7
 
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
4636,6 → 4637,44
endmodule
`endif
 
`ifdef WB_B4_RAM_BE
// WB RAM with byte enable
`define MODULE wb_b4_ram_be
module `BASE`MODULE (
`undef MODULE
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
 
parameter dat_width = 32;
parameter adr_width = 8;
 
input [dat_width-1:0] wb_dat_i;
input [adr_width-1:0] wb_adr_i;
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
 
generate
if (dat_width==32) begin
reg [31:0] ram [1<<(addr_width-2))-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
if (wb_sel_i[2]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= ram[adr_width-1:2];
end
end
endgenerate
 
endmodule
`endif
 
`ifdef WB_B4_ROM
// WB ROM
`define MODULE wb_b4_rom
/versatile_library_actel.v
1943,6 → 1943,35
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
endmodule
// WB RAM with byte enable
module vl_wb_b4_ram_be (
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
parameter dat_width = 32;
parameter adr_width = 8;
input [dat_width-1:0] wb_dat_i;
input [adr_width-1:0] wb_adr_i;
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
generate
if (dat_width==32) begin
reg [31:0] ram [1<<(addr_width-2))-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
if (wb_sel_i[2]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= ram[adr_width-1:2];
end
end
endgenerate
endmodule
// WB ROM
module vl_wb_b4_rom (
wb_adr_i, wb_stb_i, wb_cyc_i,
/wb.v
467,6 → 467,44
endmodule
`endif
 
`ifdef WB_B4_RAM_BE
// WB RAM with byte enable
`define MODULE wb_b4_ram_be
module `BASE`MODULE (
`undef MODULE
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
 
parameter dat_width = 32;
parameter adr_width = 8;
 
input [dat_width-1:0] wb_dat_i;
input [adr_width-1:0] wb_adr_i;
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
 
generate
if (dat_width==32) begin
reg [31:0] ram [1<<(addr_width-2))-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
if (wb_sel_i[2]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= ram[adr_width-1:2];
end
end
endgenerate
 
endmodule
`endif
 
`ifdef WB_B4_ROM
// WB ROM
`define MODULE wb_b4_rom
/versatile_library_altera.v
2048,6 → 2048,35
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
endmodule
// WB RAM with byte enable
module vl_wb_b4_ram_be (
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
parameter dat_width = 32;
parameter adr_width = 8;
input [dat_width-1:0] wb_dat_i;
input [adr_width-1:0] wb_adr_i;
input [dat_width/8-1:0] wb_sel_i;
input wb_we_i, wb_stb_i, wb_cyc_i;
output [dat_width-1:0] wb_dat_o;
output stall_o;
output wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
generate
if (dat_width==32) begin
reg [31:0] ram [1<<(addr_width-2))-1:0];
always @ (posedge wb_clk)
begin
if (wb_sel_i[3]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
if (wb_sel_i[2]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
if (wb_sel_i[1]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
if (wb_sel_i[0]) ram[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
wb_dat_o <= ram[adr_width-1:2];
end
end
endgenerate
endmodule
// WB ROM
module vl_wb_b4_rom (
wb_adr_i, wb_stb_i, wb_cyc_i,
/defines.v
61,6 → 61,7
 
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.