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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 61 to Rev 60
    Reverse comparison

Rev 61 → Rev 60

/versatile_library.v
234,15 → 234,7
`define DPRAM_1R1W
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, clock and reset ////
//// ////
4675,7 → 4667,7
`define MODULE wb_b3_ram_be
module `BASE`MODULE (
`undef MODULE
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
parameter nr_of_ports = 3;
4695,7 → 4687,6
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
4710,7 → 4701,6
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/versatile_library_actel.v
1962,7 → 1962,7
endmodule
// WB RAM with byte enable
module vl_wb_b3_ram_be (
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
1979,7 → 1979,6
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
1992,7 → 1991,6
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/wb.v
472,7 → 472,7
`define MODULE wb_b3_ram_be
module `BASE`MODULE (
`undef MODULE
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
parameter nr_of_ports = 3;
492,7 → 492,6
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
507,7 → 506,6
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/versatile_library_altera.v
2067,7 → 2067,7
endmodule
// WB RAM with byte enable
module vl_wb_b3_ram_be (
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
parameter nr_of_ports = 3;
parameter wb_arbiter_type = 1;
2084,7 → 2084,6
input [dw-1:0] wb_dat_i;
input [aw-1:0] wb_adr_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
2097,7 → 2096,6
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire [(dat_size/8)-1:0] wbs_sel_i;
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
wire [dat_size-1:0] wbs_dat_o;
/defines.v
234,12 → 234,3
`define DPRAM_1R1W
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif

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