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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 63 to Rev 64
    Reverse comparison

Rev 63 → Rev 64

/versatile_library.v
830,8 → 830,8
module `BASE`MODULE ( sp, r, q, clk, rst);
`undef MODULE
 
parameter width = 1;
parameter reset_value = 0;
//parameter width = 1;
parameter reset_value = 1'b0;
input sp, r;
output reg q;
/versatile_library_actel.v
288,8 → 288,8
q <= d;
endmodule
module vl_spr ( sp, r, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
//parameter width = 1;
parameter reset_value = 1'b0;
input sp, r;
output reg q;
input clk, rst;
/versatile_library_altera.v
304,8 → 304,8
q <= d;
endmodule
module vl_spr ( sp, r, q, clk, rst);
parameter width = 1;
parameter reset_value = 0;
//parameter width = 1;
parameter reset_value = 1'b0;
input sp, r;
output reg q;
input clk, rst;
/registers.v
166,8 → 166,8
module `BASE`MODULE ( sp, r, q, clk, rst);
`undef MODULE
 
parameter width = 1;
parameter reset_value = 0;
//parameter width = 1;
parameter reset_value = 1'b0;
input sp, r;
output reg q;

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