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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 71 to Rev 72
    Reverse comparison

Rev 71 → Rev 72

/versatile_library.v
3523,7 → 3523,7
`undef MODULE
 
parameter data_width = 32;
parameter addr_width = 8;
parameter addr_width = 6;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
4818,7 → 4818,7
`define MODULE ram_be
`BASE`MODULE # (
.data_width(dat_size),
.addr_width(adr_size),
.addr_width(adr_size-2),
.mem_size(mem_size),
.memory_init(memory_init),
.memory_file(memory_file))
/versatile_library_actel.v
1121,7 → 1121,7
endmodule
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
parameter addr_width = 6;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
2076,7 → 2076,7
reg wbs_ack_o;
vl_ram_be # (
.data_width(dat_size),
.addr_width(adr_size),
.addr_width(adr_size-2),
.mem_size(mem_size),
.memory_init(memory_init),
.memory_file(memory_file))
/wb.v
610,7 → 610,7
`define MODULE ram_be
`BASE`MODULE # (
.data_width(dat_size),
.addr_width(adr_size),
.addr_width(adr_size-2),
.mem_size(mem_size),
.memory_init(memory_init),
.memory_file(memory_file))
/versatile_library_altera.v
1229,7 → 1229,7
endmodule
module vl_ram_be ( d, adr, be, we, q, clk);
parameter data_width = 32;
parameter addr_width = 8;
parameter addr_width = 6;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
2181,7 → 2181,7
reg wbs_ack_o;
vl_ram_be # (
.data_width(dat_size),
.addr_width(adr_size),
.addr_width(adr_size-2),
.mem_size(mem_size),
.memory_init(memory_init),
.memory_file(memory_file))
/memories.v
104,7 → 104,7
`undef MODULE
 
parameter data_width = 32;
parameter addr_width = 8;
parameter addr_width = 6;
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;

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