OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 72 to Rev 73
    Reverse comparison

Rev 72 → Rev 73

/versatile_library.v
3527,7 → 3527,7
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input [(data_width/8)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
/versatile_library_actel.v
1125,7 → 1125,7
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input [(data_width/8)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
/versatile_library_altera.v
1233,7 → 1233,7
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input [(data_width/8)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;
/memories.v
108,7 → 108,7
parameter mem_size = 256;
input [(data_width-1):0] d;
input [(addr_width-1):0] adr;
input [(addr_width/4)-1:0] be;
input [(data_width/8)-1:0] be;
input we;
output reg [(data_width-1):0] q;
input clk;

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.