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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl/verilog
    from Rev 92 to Rev 93
    Reverse comparison

Rev 92 → Rev 93

/versatile_library.v
3775,6 → 3775,7
 
`endif
 
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem;
// verilator public
3789,6 → 3790,7
input [data_width-1:0] data;
ram[addr] = data;
endfunction // set_mem
`endif
 
endmodule
`endif
/versatile_library_actel.v
1285,6 → 1285,7
always @ (posedge clk)
q <= ram[adr];
`endif
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem;
// verilator public
1298,6 → 1299,7
input [data_width-1:0] data;
ram[addr] = data;
endfunction // set_mem
`endif
endmodule
// ACTEL FPGA should not use logic to handle rw collision
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
/versatile_library_altera.v
1393,6 → 1393,7
always @ (posedge clk)
q <= ram[adr];
`endif
`ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem;
// verilator public
1406,6 → 1407,7
input [data_width-1:0] data;
ram[addr] = data;
endfunction // set_mem
`endif
endmodule
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
parameter data_width = 32;
/memories.v
164,6 → 164,7
 
//E2_endif
 
//E2_ifdef verilator
// Function to access RAM (for use by Verilator).
function [31:0] get_mem;
// verilator public
178,6 → 179,7
input [data_width-1:0] data;
ram[addr] = data;
endfunction // set_mem
//E2_endif
 
endmodule
`endif

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