URL
https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
Subversion Repositories versatile_library
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_library/trunk/rtl/verilog
- from Rev 93 to Rev 92
- ↔ Reverse comparison
Rev 93 → Rev 92
/versatile_library.v
3775,7 → 3775,6
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`endif |
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`ifdef verilator |
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
3790,7 → 3789,6
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
`endif |
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endmodule |
`endif |
/versatile_library_actel.v
1285,7 → 1285,6
always @ (posedge clk) |
q <= ram[adr]; |
`endif |
`ifdef verilator |
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
1299,7 → 1298,6
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
`endif |
endmodule |
// ACTEL FPGA should not use logic to handle rw collision |
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
/versatile_library_altera.v
1393,7 → 1393,6
always @ (posedge clk) |
q <= ram[adr]; |
`endif |
`ifdef verilator |
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
1407,7 → 1406,6
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
`endif |
endmodule |
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b ); |
parameter data_width = 32; |
/memories.v
164,7 → 164,6
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//E2_endif |
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//E2_ifdef verilator |
// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
179,7 → 178,6
input [data_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
//E2_endif |
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endmodule |
`endif |