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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 110 to Rev 109
    Reverse comparison

Rev 110 → Rev 109

/verilog/versatile_library.v
6115,7 → 6115,7
 
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.b_data_width(data_width_b), .b_addr_width(addr_width_b),
.memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
ram_i (
/verilog/versatile_library_actel.v
2820,7 → 2820,7
end
endgenerate
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.b_data_width(data_width_b), .b_addr_width(addr_width_b),
.memory_init(memory_init), .memory_file(memory_file))
ram_i (
.d_a(wbsa_dat_i),
/verilog/wb.v
1203,7 → 1203,7
 
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.b_data_width(data_width_b), .b_addr_width(addr_width_b),
.memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
ram_i (
/verilog/versatile_library_altera.v
2925,7 → 2925,7
end
endgenerate
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
.b_data_width(data_width_b),
.b_data_width(data_width_b), .b_addr_width(addr_width_b),
.memory_init(memory_init), .memory_file(memory_file))
ram_i (
.d_a(wbsa_dat_i),

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