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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

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  • This comparison shows the changes necessary to convert path
    /versatile_library/trunk/rtl
    from Rev 132 to Rev 133
    Reverse comparison

Rev 132 → Rev 133

/verilog/versatile_library.v
6300,14 → 6300,14
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
(dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
 
`define MODULE dpram_be_2r2w
`BASE`MODULE
/verilog/versatile_library_actel.v
2971,14 → 2971,14
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
(dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
vl_dpram_be_2r2w
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
/verilog/wb.v
1382,14 → 1382,14
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
(dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
 
`define MODULE dpram_be_2r2w
`BASE`MODULE
/verilog/versatile_library_altera.v
3076,14 → 3076,14
endgenerate
localparam cache_mem_b_aw =
(dw_s==dw_m) ? aw_slot+aw_offset :
(dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
(dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
(dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
(dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
(dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
(dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
(dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
(dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
(dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
vl_dpram_be_2r2w
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),

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