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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

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    /versatile_library/trunk/rtl
    from Rev 139 to Rev 137
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Rev 139 → Rev 137

/verilog/custom_defines.v File deleted
/verilog/versatile_library.v
35,26 → 35,6
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define CNT_BIN
`define CNT_BIN_CE
`define CNT_BIN_CLEAR
`define CNT_BIN_CE_CLEAR
`define CNT_BIN_CE_CLEAR_L1_L2
`define CNT_BIN_CE_CLEAR_SET_REW
`define CNT_BIN_CE_REW_L1
`define CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_GRAY
`define CNT_GRAY_CE
`define CNT_GRAY_CE_BIN
`define CNT_LFSR_ZQ
`define CNT_LFSR_CE
`define CNT_LFSR_CE_CLEAR_Q
`define CNT_LFSR_CE_Q
`define CNT_LFSR_CE_ZQ
`define CNT_LFSR_CE_Q_ZQ
`define CNT_LFSR_CE_REW_L1
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
861,7 → 841,7
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
 
input [width-1:0] d;
input clk, rst;
911,7 → 891,7
`undef MODULE
 
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clk, rst;
933,7 → 913,7
`undef MODULE
 
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clear, clk, rst;
958,7 → 938,7
`undef MODULE
 
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
/verilog/versatile_library_actel.v
217,7 → 217,7
//////////////////////////////////////////////////////////////////////
module vl_dff ( d, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input clk, rst;
output reg [width-1:0] q;
249,7 → 249,7
endmodule
module vl_dff_ce ( d, ce, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clk, rst;
output reg [width-1:0] q;
262,7 → 262,7
endmodule
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clear, clk, rst;
output reg [width-1:0] q;
278,7 → 278,7
endmodule
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
output reg [width-1:0] q;
781,131 → 781,6
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin (
q, rst, clk);
parameter length = 4;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_clear (
clear, q, rst, clk);
parameter length = 4;
input clear;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce (
cke, q, rst, clk);
parameter length = 4;
970,311 → 845,6
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear (
clear, cke, q, rst, clk);
parameter length = 4;
input clear;
input cke;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear_l1_l2 (
clear, cke, q, level1, level2, rst, clk);
parameter length = 4;
input clear;
input cke;
output [length:1] q;
output reg level1;
output reg level2;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
wire rew;
assign rew = 1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
always @ (posedge clk or posedge rst)
if (rst)
level1 <= 1'b0;
else
if (cke)
if (clear)
level1 <= 1'b0;
else if (q_next == level1_value)
level1 <= 1'b1;
else if (qi == level1_value & rew)
level1 <= 1'b0;
always @ (posedge clk or posedge rst)
if (rst)
level2 <= 1'b0;
else
if (cke)
if (clear)
level2 <= 1'b0;
else if (q_next == level2_value)
level2 <= 1'b1;
else if (qi == level2_value & rew)
level2 <= 1'b0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear_set_rew (
clear, set, cke, rew, q, rst, clk);
parameter length = 4;
input clear;
input set;
input cke;
input rew;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
assign q_next = rew ? q_next_rew : q_next_fw;
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_rew_l1 (
cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
output reg level1;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
assign q_next = rew ? q_next_rew : q_next_fw;
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
level1 <= 1'b0;
else
if (cke)
if (clear)
level1 <= 1'b0;
else if (q_next == level1_value)
level1 <= 1'b1;
else if (qi == level1_value & rew)
level1 <= 1'b0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_rew_zq_l1 (
cke, rew, zq, level1, rst, clk);
parameter length = 4;
1673,761 → 1243,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_zq (
cke, zq, rst, clk);
parameter length = 4;
input cke;
output reg zq;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == {length{1'b0}};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_q (
cke, q, rst, clk);
parameter length = 4;
input cke;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_clear_q (
clear, cke, q, rst, clk);
parameter length = 4;
input clear;
input cke;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_q_zq (
cke, q, zq, rst, clk);
parameter length = 4;
input cke;
output [length:1] q;
output reg zq;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == {length{1'b0}};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_rew_l1 (
cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
output reg level1;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;
reg [32:1] polynom_rew;
integer j;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (qi)
begin
case (length)
2: polynom_rew = 32'b11;
3: polynom_rew = 32'b110;
4: polynom_rew = 32'b1100;
5: polynom_rew = 32'b10100;
6: polynom_rew = 32'b110000;
7: polynom_rew = 32'b1100000;
8: polynom_rew = 32'b10111000;
9: polynom_rew = 32'b100010000;
10: polynom_rew = 32'b1001000000;
11: polynom_rew = 32'b10100000000;
12: polynom_rew = 32'b100000101001;
13: polynom_rew = 32'b1000000001100;
14: polynom_rew = 32'b10000000010101;
15: polynom_rew = 32'b110000000000000;
16: polynom_rew = 32'b1101000000001000;
17: polynom_rew = 32'b10010000000000000;
18: polynom_rew = 32'b100000010000000000;
19: polynom_rew = 32'b1000000000000100011;
20: polynom_rew = 32'b10000010000000000000;
21: polynom_rew = 32'b101000000000000000000;
22: polynom_rew = 32'b1100000000000000000000;
23: polynom_rew = 32'b10000100000000000000000;
24: polynom_rew = 32'b111000010000000000000000;
25: polynom_rew = 32'b1001000000000000000000000;
26: polynom_rew = 32'b10000000000000000000100011;
27: polynom_rew = 32'b100000000000000000000010011;
28: polynom_rew = 32'b1100100000000000000000000000;
29: polynom_rew = 32'b10100000000000000000000000000;
30: polynom_rew = 32'b100000000000000000000000101001;
31: polynom_rew = 32'b1001000000000000000000000000000;
32: polynom_rew = 32'b10000000001000000000000000000011;
default: polynom_rew = 32'b0;
endcase
// rotate left
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
lfsr_fb_rew = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom_rew[i])
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
end
end
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
assign q_next = rew ? q_next_rew : q_next_fw;
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
level1 <= 1'b0;
else
if (cke)
if (clear)
level1 <= 1'b0;
else if (q_next == level1_value)
level1 <= 1'b1;
else if (qi == level1_value & rew)
level1 <= 1'b0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray (
q, rst, clk);
parameter length = 4;
output reg [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
q <= {length{1'b0}};
else
q <= (q_next>>1) ^ q_next;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce (
cke, q, rst, clk);
parameter length = 4;
input cke;
output reg [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
q <= {length{1'b0}};
else
if (cke)
q <= (q_next>>1) ^ q_next;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce_bin (
cke, q, q_bin, rst, clk);
parameter length = 4;
/verilog/versatile_library_altera.v
232,7 → 232,7
//////////////////////////////////////////////////////////////////////
module vl_dff ( d, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input clk, rst;
output reg [width-1:0] q;
264,7 → 264,7
endmodule
module vl_dff_ce ( d, ce, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clk, rst;
output reg [width-1:0] q;
277,7 → 277,7
endmodule
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clear, clk, rst;
output reg [width-1:0] q;
293,7 → 293,7
endmodule
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
output reg [width-1:0] q;
876,131 → 876,6
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin (
q, rst, clk);
parameter length = 4;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_clear (
clear, q, rst, clk);
parameter length = 4;
input clear;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce (
cke, q, rst, clk);
parameter length = 4;
1065,311 → 940,6
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear (
clear, cke, q, rst, clk);
parameter length = 4;
input clear;
input cke;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear_l1_l2 (
clear, cke, q, level1, level2, rst, clk);
parameter length = 4;
input clear;
input cke;
output [length:1] q;
output reg level1;
output reg level2;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 15;
parameter level1_value = 8;
parameter level2_value = 15;
wire rew;
assign rew = 1'b0;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
always @ (posedge clk or posedge rst)
if (rst)
level1 <= 1'b0;
else
if (cke)
if (clear)
level1 <= 1'b0;
else if (q_next == level1_value)
level1 <= 1'b1;
else if (qi == level1_value & rew)
level1 <= 1'b0;
always @ (posedge clk or posedge rst)
if (rst)
level2 <= 1'b0;
else
if (cke)
if (clear)
level2 <= 1'b0;
else if (q_next == level2_value)
level2 <= 1'b1;
else if (qi == level2_value & rew)
level2 <= 1'b0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_clear_set_rew (
clear, set, cke, rew, q, rst, clk);
parameter length = 4;
input clear;
input set;
input cke;
input rew;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 0;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
assign q_next = rew ? q_next_rew : q_next_fw;
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_rew_l1 (
cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
output reg level1;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 1;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
reg [length:1] qi;
wire [length:1] q_next, q_next_fw, q_next_rew;
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
assign q_next = rew ? q_next_rew : q_next_fw;
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
level1 <= 1'b0;
else
if (cke)
if (clear)
level1 <= 1'b0;
else if (q_next == level1_value)
level1 <= 1'b1;
else if (qi == level1_value & rew)
level1 <= 1'b0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// binary counter
module vl_cnt_bin_ce_rew_zq_l1 (
cke, rew, zq, level1, rst, clk);
parameter length = 4;
1768,761 → 1338,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_zq (
cke, zq, rst, clk);
parameter length = 4;
input cke;
output reg zq;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == {length{1'b0}};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_q (
cke, q, rst, clk);
parameter length = 4;
input cke;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_clear_q (
clear, cke, q, rst, clk);
parameter length = 4;
input clear;
input cke;
output [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_q_zq (
cke, q, zq, rst, clk);
parameter length = 4;
input cke;
output [length:1] q;
output reg zq;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
reg lfsr_fb;
wire [length:1] q_next;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
assign q = qi;
always @ (posedge clk or posedge rst)
if (rst)
zq <= 1'b1;
else
if (cke)
zq <= q_next == {length{1'b0}};
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// LFSR counter
module vl_cnt_lfsr_ce_rew_l1 (
cke, rew, level1, rst, clk);
parameter length = 4;
input cke;
input rew;
output reg level1;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
wire clear;
assign clear = 1'b0;
reg [length:1] qi;
reg lfsr_fb, lfsr_fb_rew;
wire [length:1] q_next, q_next_fw, q_next_rew;
reg [32:1] polynom_rew;
integer j;
reg [32:1] polynom;
integer i;
always @ (qi)
begin
case (length)
2: polynom = 32'b11; // 0x3
3: polynom = 32'b110; // 0x6
4: polynom = 32'b1100; // 0xC
5: polynom = 32'b10100; // 0x14
6: polynom = 32'b110000; // 0x30
7: polynom = 32'b1100000; // 0x60
8: polynom = 32'b10111000; // 0xb8
9: polynom = 32'b100010000; // 0x110
10: polynom = 32'b1001000000; // 0x240
11: polynom = 32'b10100000000; // 0x500
12: polynom = 32'b100000101001; // 0x829
13: polynom = 32'b1000000001100; // 0x100C
14: polynom = 32'b10000000010101; // 0x2015
15: polynom = 32'b110000000000000; // 0x6000
16: polynom = 32'b1101000000001000; // 0xD008
17: polynom = 32'b10010000000000000; // 0x12000
18: polynom = 32'b100000010000000000; // 0x20400
19: polynom = 32'b1000000000000100011; // 0x40023
20: polynom = 32'b10010000000000000000; // 0x90000
21: polynom = 32'b101000000000000000000; // 0x140000
22: polynom = 32'b1100000000000000000000; // 0x300000
23: polynom = 32'b10000100000000000000000; // 0x420000
24: polynom = 32'b111000010000000000000000; // 0xE10000
25: polynom = 32'b1001000000000000000000000; // 0x1200000
26: polynom = 32'b10000000000000000000100011; // 0x2000023
27: polynom = 32'b100000000000000000000010011; // 0x4000013
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
default: polynom = 32'b0;
endcase
lfsr_fb = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom[i])
lfsr_fb = lfsr_fb ~^ qi[i];
end
end
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
always @ (qi)
begin
case (length)
2: polynom_rew = 32'b11;
3: polynom_rew = 32'b110;
4: polynom_rew = 32'b1100;
5: polynom_rew = 32'b10100;
6: polynom_rew = 32'b110000;
7: polynom_rew = 32'b1100000;
8: polynom_rew = 32'b10111000;
9: polynom_rew = 32'b100010000;
10: polynom_rew = 32'b1001000000;
11: polynom_rew = 32'b10100000000;
12: polynom_rew = 32'b100000101001;
13: polynom_rew = 32'b1000000001100;
14: polynom_rew = 32'b10000000010101;
15: polynom_rew = 32'b110000000000000;
16: polynom_rew = 32'b1101000000001000;
17: polynom_rew = 32'b10010000000000000;
18: polynom_rew = 32'b100000010000000000;
19: polynom_rew = 32'b1000000000000100011;
20: polynom_rew = 32'b10000010000000000000;
21: polynom_rew = 32'b101000000000000000000;
22: polynom_rew = 32'b1100000000000000000000;
23: polynom_rew = 32'b10000100000000000000000;
24: polynom_rew = 32'b111000010000000000000000;
25: polynom_rew = 32'b1001000000000000000000000;
26: polynom_rew = 32'b10000000000000000000100011;
27: polynom_rew = 32'b100000000000000000000010011;
28: polynom_rew = 32'b1100100000000000000000000000;
29: polynom_rew = 32'b10100000000000000000000000000;
30: polynom_rew = 32'b100000000000000000000000101001;
31: polynom_rew = 32'b1001000000000000000000000000000;
32: polynom_rew = 32'b10000000001000000000000000000011;
default: polynom_rew = 32'b0;
endcase
// rotate left
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
lfsr_fb_rew = qi[length];
for (i=length-1; i>=1; i=i-1) begin
if (polynom_rew[i])
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
end
end
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
assign q_next = rew ? q_next_rew : q_next_fw;
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
level1 <= 1'b0;
else
if (cke)
if (clear)
level1 <= 1'b0;
else if (q_next == level1_value)
level1 <= 1'b1;
else if (qi == level1_value & rew)
level1 <= 1'b0;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray (
q, rst, clk);
parameter length = 4;
output reg [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
q <= {length{1'b0}};
else
q <= (q_next>>1) ^ q_next;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce (
cke, q, rst, clk);
parameter length = 4;
input cke;
output reg [length:1] q;
input rst;
input clk;
parameter clear_value = 0;
parameter set_value = 1;
parameter wrap_value = 8;
parameter level1_value = 15;
reg [length:1] qi;
wire [length:1] q_next;
assign q_next = qi + {{length-1{1'b0}},1'b1};
always @ (posedge clk or posedge rst)
if (rst)
qi <= {length{1'b0}};
else
if (cke)
qi <= q_next;
always @ (posedge clk or posedge rst)
if (rst)
q <= {length{1'b0}};
else
if (cke)
q <= (q_next>>1) ^ q_next;
endmodule
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// GRAY counter
module vl_cnt_gray_ce_bin (
cke, q, q_bin, rst, clk);
parameter length = 4;
/verilog/io.v
72,7 → 72,6
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = 1'b0;
input [width-1:0] d_o;
output reg [width-1:0] d_i;
input oe;
92,12 → 91,12
oe_q[i] <= oe_d[i];
always @ (posedge clk or posedge rst)
if (rst)
d_o_q[i] <= reset_value;
d_o_q[i] <= 1'b0;
else
d_o_q[i] <= d_o[i];
always @ (posedge clk or posedge rst)
if (rst)
d_i[i] <= reset_value;
d_i[i] <= 1'b0;
else
d_i[i] <= io_pad[i];
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
/verilog/defines.v
35,26 → 35,6
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define CNT_BIN
`define CNT_BIN_CE
`define CNT_BIN_CLEAR
`define CNT_BIN_CE_CLEAR
`define CNT_BIN_CE_CLEAR_L1_L2
`define CNT_BIN_CE_CLEAR_SET_REW
`define CNT_BIN_CE_REW_L1
`define CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_GRAY
`define CNT_GRAY_CE
`define CNT_GRAY_CE_BIN
`define CNT_LFSR_ZQ
`define CNT_LFSR_CE
`define CNT_LFSR_CE_CLEAR_Q
`define CNT_LFSR_CE_Q
`define CNT_LFSR_CE_ZQ
`define CNT_LFSR_CE_Q_ZQ
`define CNT_LFSR_CE_REW_L1
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
/verilog/registers.v
45,7 → 45,7
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
 
input [width-1:0] d;
input clk, rst;
95,7 → 95,7
`undef MODULE
 
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clk, rst;
117,7 → 117,7
`undef MODULE
 
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, clear, clk, rst;
142,7 → 142,7
`undef MODULE
 
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = 0;
input [width-1:0] d;
input ce, set, clk, rst;
/verilog/Makefile
70,8 → 70,6
$(OUT_FILE): $(VERILOG_FILES)
vppreproc --noline --noblank $(DEFINE_FILE) $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > $(OUT_FILE)
 
config:
configurator custom_defines.v
 
all: $(VERSATILE_LIBRARIES)
 
/verilog/clk_and_reset.v
380,47 → 380,36
`undef MODULE
parameter index = 0;
parameter number_of_clk = 1;
parameter period_time = 20000;
parameter clk0_mult_by = 1;
parameter clk0_div_by = 1;
parameter clk1_mult_by = 1;
parameter clk1_div_by = 1;
parameter clk2_mult_by = 1;
parameter clk3_div_by = 1;
parameter clk3_mult_by = 1;
parameter clk3_div_by = 1;
parameter clk4_mult_by = 1;
parameter clk4_div_by = 1;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
initial
clk_o = {number_of_clk{1'b0}};
always
#((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <= (!rst_n_i) ? 1'b0 : ~clk_o[0];
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
 
generate if (number_of_clk > 1)
always
#((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <= (!rst_n_i) ? 1'b0 : ~clk_o[1];
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
 
generate if (number_of_clk > 2)
always
#((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <= (!rst_n_i) ? 1'b0 : ~clk_o[2];
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
 
generate if (number_of_clk > 3)
always
#((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <= (!rst_n_i) ? 1'b0 : ~clk_o[3];
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
`define MODULE sync_rst
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`undef MODULE
end
endgenerate
 
generate if (number_of_clk > 4)
always
#((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <= (!rst_n_i) ? 1'b0 : ~clk_o[4];
endgenerate
 
assign #lock_delay lock = rst_n_i;
endmodule

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