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URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

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    /versatile_library/trunk/rtl
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Rev 2 → Rev 3

/verilog/cnt_gray_bin_ce.csv
0,0 → 1,14
Name,type,,,,
cnt_gray_bin_ce,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
,,,,,
q,q_bin,z,zq,level1,level2
1,1,0,0,0,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/verilog/cnt_gray.csv
0,0 → 1,14
Name,type,,,,
cnt_gray,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,0,0,,
,,,,,
q,q_bin,z,zq,level1,level2
1,0,0,0,0,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/verilog/clk_and_reset.v
0,0 → 1,224
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, clock and reset ////
//// ////
//// Description ////
//// Logic related to clock and reset ////
//// ////
//// ////
//// To Do: ////
//// - add more different registers ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`define EXPAND_TO_IFDEF `ifdef
`define EXPAND_TO_ELSE `else
`define EXPAND_TO_ENDIF `endif
// Global buffer
// usage:
// use to enable global buffers for high fan out signal such as clock and reset
 
`ifdef ACTEL
 
`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
output GL;
input CLK;
 
wire GND;
GND GND_1_net(.Y(GND));
CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
endmodule
`timescale 1 ns/1 ns
module vl_gbuf ( i, o);
input i;
output o;
gbuf gbuf_i0 ( .CLK(i), .GL(o));
endmodule
`else
`ifdef ALTERA
altera
`else
 
`timescale 1 ns/1 ns
module vl_gbuf ( i, o);
input i;
output o;
assign o = i;
endmodule
`endif // ALTERA
`endif //ACTEL
 
// sync reset
// input active lo async reset, normally from external reset generetaor and/or switch
// output active high global reset sync with two DFFs
`timescale 1 ns/1 ns
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
output rst_o;
reg [0:1] tmp;
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
tmp <= 2'b00;
else
tmp <= {1'b1,tmp[0]};
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
endmodule
 
// vl_pll
`ifdef ACTEL
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter number_of_clk = 3;
parameter clk_i_period_time = 20;
parameter [0:number_of_clk-1] mult = {32'd1,32'd2,32'd2};
parameter [0:number_of_clk-1] div = {32'd1,32'd3,32'd3};
parameter lock_delay = 200;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
//E2_ifdef SIM_PLL
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
always
#((clk_i_period_time*div[i]/mult[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
endgenerate
 
assign #lock_delay lock = rst_n_i;
 
endmodule
//E2_else
generate if (number_of_clk==1 & index==0) begin
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==0
generate if (number_of_clk==1 & index==1) begin
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==1
generate if (number_of_clk==1 & index==2) begin
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==2
generate if (number_of_clk==1 & index==3) begin
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==0
 
generate if (number_of_clk==2 & index==0) begin
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==0
generate if (number_of_clk==2 & index==1) begin
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==1
generate if (number_of_clk==2 & index==2) begin
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==2
generate if (number_of_clk==2 & index==3) begin
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==0
 
generate if (number_of_clk==3 & index==0) begin
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==0
generate if (number_of_clk==3 & index==1) begin
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==1
generate if (number_of_clk==3 & index==2) begin
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==2
generate if (number_of_clk==3 & index==3) begin
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==0
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
end
endgenerate
endmodule
//E2_endif
 
`else
 
`ifdef ALTERA
 
`else
 
// generic PLL
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter number_of_clk = 3;
parameter clk_i_period_time = 20;
parameter clk0_feedthrough = 0;
parameter mult = 1;
parameter div = 1;
parameter [0:number_of_clk-1] post_div = {32'd1,32'd3,32'd3};
parameter lock_delay = 2000;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
genvar i;
generate if (clk0_feedthrough==1) begin: clk0_feedthrough
always #(clk_i_period_time/2+0.200) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
generate for (i=clk0_feedthrough;i<number_of_clk;i=i+1) begin: clock
always
#((clk_i_period_time*div/mult*post_div[i])/2) clk_o[i] <= (!rst_n_i) ? 0 : ~clk_o[i];
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
endgenerate
 
assign #lock_delay lock = rst_n_i;
endmodule
 
`endif //altera
`endif //actel
/verilog/cnt_lfsr.csv
0,0 → 1,14
Name,type,,,,
cnt_lfsr,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,0,0,,
,,,,,
q,q_bin,z,zq,level1,level2
0,1,0,1,0,0
,,,,,
wrap,wrap_around,,,,
1,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/verilog/counters.v
0,0 → 1,42
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, counters ////
//// ////
//// Description ////
//// counters ////
//// ////
//// ////
//// To Do: ////
//// - add more counters ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
/verilog/cnt_gray_ce.csv
0,0 → 1,14
Name,type,,,,
cnt_gray_ce,GRAY,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
,,,,,
q,q_bin,z,zq,level1,level2
1,0,0,0,0,0
,,,,,
wrap,wrap_around,,,,
0,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,8,15,
/verilog/cnt_lfsr_ce.csv
0,0 → 1,14
Name,type,,,,
cnt_lfsr_ce,LFSR,,,,
,,,,,
clear,set,cke,rew,,
0,0,1,0,,
,,,,,
q,q_bin,z,zq,level1,level2
0,1,0,1,0,0
,,,,,
wrap,wrap_around,,,,
1,1,,,,
,,,,,
length,clear_value,set_value,wrap_value,level1,level2
4,0,1,0,15,
/verilog/registers.v
0,0 → 1,220
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile library, registers ////
//// ////
//// Description ////
//// Different type of registers ////
//// ////
//// ////
//// To Do: ////
//// - add more different registers ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module dff ( d, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
 
input [width-1:0] d;
input clk, rst;
output reg [width-1:0] q;
always @ (posedge clk or posedge rst)
if (rst)
q <= reset_value;
else
q <= d;
 
endmodule
 
module dff_ce ( d, ce, q, clk, rst);
 
parameter width = 1;
parameter reset_value = 0;
input [width-1:0] d;
input ce, clk, rst;
output reg [width-1:0] q;
 
always @ (posedge clk or posedge rst)
if (rst)
q <= reset_value;
else
if (ce)
q <= d;
 
endmodule
 
`ifdef ALTERA
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ff
 
// ============================================================
// File Name: dff_sr.v
// Megafunction Name(s):
// lpm_ff
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dff_sr (
aclr,
aset,
clock,
data,
q);
 
input aclr;
input aset;
input clock;
input data;
output q;
 
wire [0:0] sub_wire0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire q = sub_wire1;
wire sub_wire2 = data;
wire sub_wire3 = sub_wire2;
 
lpm_ff lpm_ff_component (
.aclr (aclr),
.clock (clock),
.data (sub_wire3),
.aset (aset),
.q (sub_wire0)
// synopsys translate_off
,
.aload (),
.enable (),
.sclr (),
.sload (),
.sset ()
// synopsys translate_on
);
defparam
lpm_ff_component.lpm_fftype = "DFF",
lpm_ff_component.lpm_type = "LPM_FF",
lpm_ff_component.lpm_width = 1;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "1"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
 
 
`else
 
 
module dff_sr ( aclr, aset, clock, data, q);
 
input aclr;
input aset;
input clock;
input data;
output reg q;
 
always @ (posedge clock or posedge aclr or posedge aset)
if (aclr)
q <= 1'b0;
else if (aset)
q <= 1'b1;
else
q <= data;
 
endmodule
 
`endif
/verilog/Makefile
0,0 → 1,42
VERILOG_FILES = clk_and_reset.v
VERILOG_FILES += registers.v
 
VERILOG_FILES_CNT = cnt_lfsr.v
VERILOG_FILES_CNT += cnt_lfsr_ce.v
VERILOG_FILES_CNT += cnt_gray.v
VERILOG_FILES_CNT += cnt_gray_ce.v
VERILOG_FILES_CNT += cnt_gray_bin_ce.v
 
VERILOG_FILES += $(VERILOG_FILES_CNT)
VERILOG_FILES += counters.v
 
VERSATILE_LIBRARIES = versatile_library.v
VERSATILE_LIBRARIES += versatile_library_actel.v
VERSATILE_LIBRARIES += versatile_library_altera.v
 
svn_export:
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php
svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/CSV.class.php
 
#.PHONY: $(VERILOG_FILES_CNT)
$(VERILOG_FILES_CNT):
./versatile_counter_generator.php cnt_lfsr.csv > cnt_lfsr.v
./versatile_counter_generator.php cnt_lfsr_ce.csv > cnt_lfsr_ce.v
./versatile_counter_generator.php cnt_gray.csv > cnt_gray.v
./versatile_counter_generator.php cnt_gray_ce.csv > cnt_gray_ce.v
./versatile_counter_generator.php cnt_gray_bin_ce.csv > cnt_gray_bin_ce.v
 
versatile_library.v: $(VERILOG_FILES)
cat $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library.v
versatile_library_actel.v: $(VERILOG_FILES)
vppreproc --noline --noblank +define+ACTEL $(VERILOG_FILES) | sed -r -e 's/\/\/E2_([a-z]+)/`\1/' > versatile_library_actel.v
versatile_library_altera.v: $(VERILOG_FILES)
vppreproc --noline --noblank +define+ALTERA $(VERILOG_FILES) > versatile_library_altera.v
 
all: $(VERSATILE_LIBRARIES)
 
clean:
rm $(VERSATILE_LIBRARIES)
rm $(VERILOG_FILES_CNT)
/verilog/versatile_counter_defines.v
0,0 → 1,42
// defines from cmd

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